forked from Imagelibrary/rtems
724 lines
19 KiB
C
724 lines
19 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* @ingroup RTEMSDeviceGRCAN
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*
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* @brief This header file defines the GRCAN register block interface.
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*/
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/*
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* Copyright (C) 2021 embedded brains GmbH & Co. KG
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* This file is part of the RTEMS quality process and was automatically
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* generated. If you find something that needs to be fixed or
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* worded better please post a report or patch to an RTEMS mailing list
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* or raise a bug report:
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*
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* https://www.rtems.org/bugs.html
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*
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* For information on updating and regenerating please refer to the How-To
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* section in the Software Requirements Engineering chapter of the
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* RTEMS Software Engineering manual. The manual is provided as a part of
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* a release. For development sources please refer to the online
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* documentation at:
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*
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* https://docs.rtems.org
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*/
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/* Generated from spec:/dev/grlib/if/grcan-header */
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#ifndef _GRLIB_GRCAN_REGS_H
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#define _GRLIB_GRCAN_REGS_H
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Generated from spec:/dev/grlib/if/grcan */
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/**
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* @defgroup RTEMSDeviceGRCAN GRCAN
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*
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* @ingroup RTEMSDeviceGRLIB
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*
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* @brief This group contains the GRCAN interfaces.
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*
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* @{
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*/
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/**
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* @defgroup RTEMSDeviceGRCANCanCONF Configuration Register (CanCONF)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRCAN_CANCONF_SCALER_SHIFT 24
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#define GRCAN_CANCONF_SCALER_MASK 0xff000000U
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#define GRCAN_CANCONF_SCALER_GET( _reg ) \
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( ( ( _reg ) & GRCAN_CANCONF_SCALER_MASK ) >> \
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GRCAN_CANCONF_SCALER_SHIFT )
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#define GRCAN_CANCONF_SCALER_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRCAN_CANCONF_SCALER_MASK ) | \
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( ( ( _val ) << GRCAN_CANCONF_SCALER_SHIFT ) & \
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GRCAN_CANCONF_SCALER_MASK ) )
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#define GRCAN_CANCONF_SCALER( _val ) \
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( ( ( _val ) << GRCAN_CANCONF_SCALER_SHIFT ) & \
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GRCAN_CANCONF_SCALER_MASK )
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#define GRCAN_CANCONF_PS1_SHIFT 20
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#define GRCAN_CANCONF_PS1_MASK 0xf00000U
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#define GRCAN_CANCONF_PS1_GET( _reg ) \
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( ( ( _reg ) & GRCAN_CANCONF_PS1_MASK ) >> \
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GRCAN_CANCONF_PS1_SHIFT )
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#define GRCAN_CANCONF_PS1_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRCAN_CANCONF_PS1_MASK ) | \
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( ( ( _val ) << GRCAN_CANCONF_PS1_SHIFT ) & \
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GRCAN_CANCONF_PS1_MASK ) )
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#define GRCAN_CANCONF_PS1( _val ) \
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( ( ( _val ) << GRCAN_CANCONF_PS1_SHIFT ) & \
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GRCAN_CANCONF_PS1_MASK )
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#define GRCAN_CANCONF_PS2_SHIFT 16
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#define GRCAN_CANCONF_PS2_MASK 0xf0000U
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#define GRCAN_CANCONF_PS2_GET( _reg ) \
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( ( ( _reg ) & GRCAN_CANCONF_PS2_MASK ) >> \
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GRCAN_CANCONF_PS2_SHIFT )
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#define GRCAN_CANCONF_PS2_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRCAN_CANCONF_PS2_MASK ) | \
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( ( ( _val ) << GRCAN_CANCONF_PS2_SHIFT ) & \
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GRCAN_CANCONF_PS2_MASK ) )
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#define GRCAN_CANCONF_PS2( _val ) \
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( ( ( _val ) << GRCAN_CANCONF_PS2_SHIFT ) & \
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GRCAN_CANCONF_PS2_MASK )
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#define GRCAN_CANCONF_RSJ_SHIFT 12
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#define GRCAN_CANCONF_RSJ_MASK 0x7000U
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#define GRCAN_CANCONF_RSJ_GET( _reg ) \
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( ( ( _reg ) & GRCAN_CANCONF_RSJ_MASK ) >> \
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GRCAN_CANCONF_RSJ_SHIFT )
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#define GRCAN_CANCONF_RSJ_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRCAN_CANCONF_RSJ_MASK ) | \
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( ( ( _val ) << GRCAN_CANCONF_RSJ_SHIFT ) & \
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GRCAN_CANCONF_RSJ_MASK ) )
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#define GRCAN_CANCONF_RSJ( _val ) \
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( ( ( _val ) << GRCAN_CANCONF_RSJ_SHIFT ) & \
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GRCAN_CANCONF_RSJ_MASK )
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#define GRCAN_CANCONF_BPR_SHIFT 8
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#define GRCAN_CANCONF_BPR_MASK 0x300U
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#define GRCAN_CANCONF_BPR_GET( _reg ) \
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( ( ( _reg ) & GRCAN_CANCONF_BPR_MASK ) >> \
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GRCAN_CANCONF_BPR_SHIFT )
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#define GRCAN_CANCONF_BPR_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRCAN_CANCONF_BPR_MASK ) | \
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( ( ( _val ) << GRCAN_CANCONF_BPR_SHIFT ) & \
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GRCAN_CANCONF_BPR_MASK ) )
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#define GRCAN_CANCONF_BPR( _val ) \
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( ( ( _val ) << GRCAN_CANCONF_BPR_SHIFT ) & \
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GRCAN_CANCONF_BPR_MASK )
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#define GRCAN_CANCONF_SAM 0x20U
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#define GRCAN_CANCONF_SILNT 0x10U
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#define GRCAN_CANCONF_SELECT 0x8U
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#define GRCAN_CANCONF_ENABLE1 0x4U
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#define GRCAN_CANCONF_ENABLE0 0x2U
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#define GRCAN_CANCONF_ABORT 0x1U
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRCANCanSTAT Status Register (CanSTAT)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRCAN_CANSTAT_TXCHANNELS_SHIFT 28
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#define GRCAN_CANSTAT_TXCHANNELS_MASK 0xf0000000U
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#define GRCAN_CANSTAT_TXCHANNELS_GET( _reg ) \
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( ( ( _reg ) & GRCAN_CANSTAT_TXCHANNELS_MASK ) >> \
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GRCAN_CANSTAT_TXCHANNELS_SHIFT )
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#define GRCAN_CANSTAT_TXCHANNELS_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRCAN_CANSTAT_TXCHANNELS_MASK ) | \
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( ( ( _val ) << GRCAN_CANSTAT_TXCHANNELS_SHIFT ) & \
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GRCAN_CANSTAT_TXCHANNELS_MASK ) )
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#define GRCAN_CANSTAT_TXCHANNELS( _val ) \
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( ( ( _val ) << GRCAN_CANSTAT_TXCHANNELS_SHIFT ) & \
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GRCAN_CANSTAT_TXCHANNELS_MASK )
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#define GRCAN_CANSTAT_RXCHANNELS_SHIFT 24
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#define GRCAN_CANSTAT_RXCHANNELS_MASK 0xf000000U
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#define GRCAN_CANSTAT_RXCHANNELS_GET( _reg ) \
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( ( ( _reg ) & GRCAN_CANSTAT_RXCHANNELS_MASK ) >> \
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GRCAN_CANSTAT_RXCHANNELS_SHIFT )
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#define GRCAN_CANSTAT_RXCHANNELS_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRCAN_CANSTAT_RXCHANNELS_MASK ) | \
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( ( ( _val ) << GRCAN_CANSTAT_RXCHANNELS_SHIFT ) & \
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GRCAN_CANSTAT_RXCHANNELS_MASK ) )
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#define GRCAN_CANSTAT_RXCHANNELS( _val ) \
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( ( ( _val ) << GRCAN_CANSTAT_RXCHANNELS_SHIFT ) & \
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GRCAN_CANSTAT_RXCHANNELS_MASK )
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#define GRCAN_CANSTAT_TXERRCNT_SHIFT 16
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#define GRCAN_CANSTAT_TXERRCNT_MASK 0xff0000U
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#define GRCAN_CANSTAT_TXERRCNT_GET( _reg ) \
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( ( ( _reg ) & GRCAN_CANSTAT_TXERRCNT_MASK ) >> \
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GRCAN_CANSTAT_TXERRCNT_SHIFT )
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#define GRCAN_CANSTAT_TXERRCNT_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRCAN_CANSTAT_TXERRCNT_MASK ) | \
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( ( ( _val ) << GRCAN_CANSTAT_TXERRCNT_SHIFT ) & \
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GRCAN_CANSTAT_TXERRCNT_MASK ) )
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#define GRCAN_CANSTAT_TXERRCNT( _val ) \
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( ( ( _val ) << GRCAN_CANSTAT_TXERRCNT_SHIFT ) & \
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GRCAN_CANSTAT_TXERRCNT_MASK )
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#define GRCAN_CANSTAT_RXERRCNT_SHIFT 8
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#define GRCAN_CANSTAT_RXERRCNT_MASK 0xff00U
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#define GRCAN_CANSTAT_RXERRCNT_GET( _reg ) \
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( ( ( _reg ) & GRCAN_CANSTAT_RXERRCNT_MASK ) >> \
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GRCAN_CANSTAT_RXERRCNT_SHIFT )
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#define GRCAN_CANSTAT_RXERRCNT_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRCAN_CANSTAT_RXERRCNT_MASK ) | \
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( ( ( _val ) << GRCAN_CANSTAT_RXERRCNT_SHIFT ) & \
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GRCAN_CANSTAT_RXERRCNT_MASK ) )
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#define GRCAN_CANSTAT_RXERRCNT( _val ) \
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( ( ( _val ) << GRCAN_CANSTAT_RXERRCNT_SHIFT ) & \
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GRCAN_CANSTAT_RXERRCNT_MASK )
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#define GRCAN_CANSTAT_ACTIVE 0x10U
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#define GRCAN_CANSTAT_AHBERR 0x8U
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#define GRCAN_CANSTAT_OR 0x4U
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#define GRCAN_CANSTAT_OFF 0x2U
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#define GRCAN_CANSTAT_PASS 0x1U
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRCANCanCTRL Control Register (CanCTRL)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRCAN_CANCTRL_RESET 0x2U
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#define GRCAN_CANCTRL_ENABLE 0x1U
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRCANCanMASK SYNC Mask Filter Register (CanMASK)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRCAN_CANMASK_MASK_SHIFT 0
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#define GRCAN_CANMASK_MASK_MASK 0x1fffffffU
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#define GRCAN_CANMASK_MASK_GET( _reg ) \
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( ( ( _reg ) & GRCAN_CANMASK_MASK_MASK ) >> \
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GRCAN_CANMASK_MASK_SHIFT )
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#define GRCAN_CANMASK_MASK_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRCAN_CANMASK_MASK_MASK ) | \
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( ( ( _val ) << GRCAN_CANMASK_MASK_SHIFT ) & \
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GRCAN_CANMASK_MASK_MASK ) )
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#define GRCAN_CANMASK_MASK( _val ) \
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( ( ( _val ) << GRCAN_CANMASK_MASK_SHIFT ) & \
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GRCAN_CANMASK_MASK_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRCANCanCODE SYNC Code Filter Register (CanCODE)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRCAN_CANCODE_SYNC_SHIFT 0
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#define GRCAN_CANCODE_SYNC_MASK 0x1fffffffU
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#define GRCAN_CANCODE_SYNC_GET( _reg ) \
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( ( ( _reg ) & GRCAN_CANCODE_SYNC_MASK ) >> \
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GRCAN_CANCODE_SYNC_SHIFT )
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#define GRCAN_CANCODE_SYNC_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRCAN_CANCODE_SYNC_MASK ) | \
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( ( ( _val ) << GRCAN_CANCODE_SYNC_SHIFT ) & \
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GRCAN_CANCODE_SYNC_MASK ) )
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#define GRCAN_CANCODE_SYNC( _val ) \
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( ( ( _val ) << GRCAN_CANCODE_SYNC_SHIFT ) & \
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GRCAN_CANCODE_SYNC_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRCANCanTxCTRL \
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* Transmit Channel Control Register (CanTxCTRL)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRCAN_CANTXCTRL_SINGLE 0x4U
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#define GRCAN_CANTXCTRL_ONGOING 0x2U
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#define GRCAN_CANTXCTRL_ENABLE 0x1U
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRCANCanTxADDR \
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* Transmit Channel Address Register (CanTxADDR)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRCAN_CANTXADDR_ADDR_SHIFT 10
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#define GRCAN_CANTXADDR_ADDR_MASK 0xfffffc00U
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#define GRCAN_CANTXADDR_ADDR_GET( _reg ) \
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( ( ( _reg ) & GRCAN_CANTXADDR_ADDR_MASK ) >> \
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GRCAN_CANTXADDR_ADDR_SHIFT )
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#define GRCAN_CANTXADDR_ADDR_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRCAN_CANTXADDR_ADDR_MASK ) | \
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( ( ( _val ) << GRCAN_CANTXADDR_ADDR_SHIFT ) & \
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GRCAN_CANTXADDR_ADDR_MASK ) )
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#define GRCAN_CANTXADDR_ADDR( _val ) \
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( ( ( _val ) << GRCAN_CANTXADDR_ADDR_SHIFT ) & \
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GRCAN_CANTXADDR_ADDR_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRCANCanTxSIZE \
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* Transmit Channel Size Register (CanTxSIZE)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRCAN_CANTXSIZE_SIZE_SHIFT 6
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#define GRCAN_CANTXSIZE_SIZE_MASK 0x1fffc0U
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#define GRCAN_CANTXSIZE_SIZE_GET( _reg ) \
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( ( ( _reg ) & GRCAN_CANTXSIZE_SIZE_MASK ) >> \
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GRCAN_CANTXSIZE_SIZE_SHIFT )
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#define GRCAN_CANTXSIZE_SIZE_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRCAN_CANTXSIZE_SIZE_MASK ) | \
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( ( ( _val ) << GRCAN_CANTXSIZE_SIZE_SHIFT ) & \
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GRCAN_CANTXSIZE_SIZE_MASK ) )
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#define GRCAN_CANTXSIZE_SIZE( _val ) \
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( ( ( _val ) << GRCAN_CANTXSIZE_SIZE_SHIFT ) & \
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GRCAN_CANTXSIZE_SIZE_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRCANCanTxWR Transmit Channel Write Register (CanTxWR)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRCAN_CANTXWR_WRITE_SHIFT 4
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#define GRCAN_CANTXWR_WRITE_MASK 0xffff0U
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#define GRCAN_CANTXWR_WRITE_GET( _reg ) \
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( ( ( _reg ) & GRCAN_CANTXWR_WRITE_MASK ) >> \
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GRCAN_CANTXWR_WRITE_SHIFT )
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#define GRCAN_CANTXWR_WRITE_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRCAN_CANTXWR_WRITE_MASK ) | \
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( ( ( _val ) << GRCAN_CANTXWR_WRITE_SHIFT ) & \
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GRCAN_CANTXWR_WRITE_MASK ) )
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#define GRCAN_CANTXWR_WRITE( _val ) \
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( ( ( _val ) << GRCAN_CANTXWR_WRITE_SHIFT ) & \
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GRCAN_CANTXWR_WRITE_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRCANCanTxRD Transmit Channel Read Register (CanTxRD)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRCAN_CANTXRD_READ_SHIFT 4
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#define GRCAN_CANTXRD_READ_MASK 0xffff0U
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#define GRCAN_CANTXRD_READ_GET( _reg ) \
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( ( ( _reg ) & GRCAN_CANTXRD_READ_MASK ) >> \
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GRCAN_CANTXRD_READ_SHIFT )
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#define GRCAN_CANTXRD_READ_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRCAN_CANTXRD_READ_MASK ) | \
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( ( ( _val ) << GRCAN_CANTXRD_READ_SHIFT ) & \
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GRCAN_CANTXRD_READ_MASK ) )
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#define GRCAN_CANTXRD_READ( _val ) \
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( ( ( _val ) << GRCAN_CANTXRD_READ_SHIFT ) & \
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GRCAN_CANTXRD_READ_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRCANCanTxIRQ \
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* Transmit Channel Interrupt Register (CanTxIRQ)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRCAN_CANTXIRQ_IRQ_SHIFT 4
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#define GRCAN_CANTXIRQ_IRQ_MASK 0xffff0U
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#define GRCAN_CANTXIRQ_IRQ_GET( _reg ) \
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( ( ( _reg ) & GRCAN_CANTXIRQ_IRQ_MASK ) >> \
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GRCAN_CANTXIRQ_IRQ_SHIFT )
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#define GRCAN_CANTXIRQ_IRQ_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRCAN_CANTXIRQ_IRQ_MASK ) | \
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( ( ( _val ) << GRCAN_CANTXIRQ_IRQ_SHIFT ) & \
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GRCAN_CANTXIRQ_IRQ_MASK ) )
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#define GRCAN_CANTXIRQ_IRQ( _val ) \
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( ( ( _val ) << GRCAN_CANTXIRQ_IRQ_SHIFT ) & \
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GRCAN_CANTXIRQ_IRQ_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRCANCanRxCTRL \
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* Receive Channel Control Register (CanRxCTRL)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRCAN_CANRXCTRL_ONGOING 0x2U
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#define GRCAN_CANRXCTRL_ENABLE 0x1U
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRCANCanRxADDR \
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* Receive Channel Address Register (CanRxADDR)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRCAN_CANRXADDR_ADDR_SHIFT 10
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#define GRCAN_CANRXADDR_ADDR_MASK 0xfffffc00U
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#define GRCAN_CANRXADDR_ADDR_GET( _reg ) \
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( ( ( _reg ) & GRCAN_CANRXADDR_ADDR_MASK ) >> \
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GRCAN_CANRXADDR_ADDR_SHIFT )
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#define GRCAN_CANRXADDR_ADDR_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRCAN_CANRXADDR_ADDR_MASK ) | \
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( ( ( _val ) << GRCAN_CANRXADDR_ADDR_SHIFT ) & \
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GRCAN_CANRXADDR_ADDR_MASK ) )
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#define GRCAN_CANRXADDR_ADDR( _val ) \
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( ( ( _val ) << GRCAN_CANRXADDR_ADDR_SHIFT ) & \
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GRCAN_CANRXADDR_ADDR_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRCANCanRxSIZE \
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* Receive Channel Size Register (CanRxSIZE)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRCAN_CANRXSIZE_SIZE_SHIFT 6
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#define GRCAN_CANRXSIZE_SIZE_MASK 0x1fffc0U
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#define GRCAN_CANRXSIZE_SIZE_GET( _reg ) \
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( ( ( _reg ) & GRCAN_CANRXSIZE_SIZE_MASK ) >> \
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GRCAN_CANRXSIZE_SIZE_SHIFT )
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#define GRCAN_CANRXSIZE_SIZE_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRCAN_CANRXSIZE_SIZE_MASK ) | \
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( ( ( _val ) << GRCAN_CANRXSIZE_SIZE_SHIFT ) & \
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GRCAN_CANRXSIZE_SIZE_MASK ) )
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#define GRCAN_CANRXSIZE_SIZE( _val ) \
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( ( ( _val ) << GRCAN_CANRXSIZE_SIZE_SHIFT ) & \
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GRCAN_CANRXSIZE_SIZE_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRCANCanRxWR Receive Channel Write Register (CanRxWR)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRCAN_CANRXWR_WRITE_SHIFT 4
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#define GRCAN_CANRXWR_WRITE_MASK 0xffff0U
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#define GRCAN_CANRXWR_WRITE_GET( _reg ) \
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( ( ( _reg ) & GRCAN_CANRXWR_WRITE_MASK ) >> \
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GRCAN_CANRXWR_WRITE_SHIFT )
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#define GRCAN_CANRXWR_WRITE_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRCAN_CANRXWR_WRITE_MASK ) | \
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( ( ( _val ) << GRCAN_CANRXWR_WRITE_SHIFT ) & \
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GRCAN_CANRXWR_WRITE_MASK ) )
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#define GRCAN_CANRXWR_WRITE( _val ) \
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( ( ( _val ) << GRCAN_CANRXWR_WRITE_SHIFT ) & \
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GRCAN_CANRXWR_WRITE_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRCANCanRxRD Receive Channel Read Register (CanRxRD)
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*
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* @brief This group contains register bit definitions.
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*
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* @{
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*/
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#define GRCAN_CANRXRD_READ_SHIFT 4
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#define GRCAN_CANRXRD_READ_MASK 0xffff0U
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#define GRCAN_CANRXRD_READ_GET( _reg ) \
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( ( ( _reg ) & GRCAN_CANRXRD_READ_MASK ) >> \
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GRCAN_CANRXRD_READ_SHIFT )
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#define GRCAN_CANRXRD_READ_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRCAN_CANRXRD_READ_MASK ) | \
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( ( ( _val ) << GRCAN_CANRXRD_READ_SHIFT ) & \
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GRCAN_CANRXRD_READ_MASK ) )
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#define GRCAN_CANRXRD_READ( _val ) \
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( ( ( _val ) << GRCAN_CANRXRD_READ_SHIFT ) & \
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GRCAN_CANRXRD_READ_MASK )
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/** @} */
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/**
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* @defgroup RTEMSDeviceGRCANCanRxIRQ \
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* Receive Channel Interrupt Register (CanRxIRQ)
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*
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* @brief This group contains register bit definitions.
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|
*
|
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* @{
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*/
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#define GRCAN_CANRXIRQ_IRQ_SHIFT 4
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#define GRCAN_CANRXIRQ_IRQ_MASK 0xffff0U
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#define GRCAN_CANRXIRQ_IRQ_GET( _reg ) \
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( ( ( _reg ) & GRCAN_CANRXIRQ_IRQ_MASK ) >> \
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GRCAN_CANRXIRQ_IRQ_SHIFT )
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#define GRCAN_CANRXIRQ_IRQ_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRCAN_CANRXIRQ_IRQ_MASK ) | \
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( ( ( _val ) << GRCAN_CANRXIRQ_IRQ_SHIFT ) & \
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GRCAN_CANRXIRQ_IRQ_MASK ) )
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#define GRCAN_CANRXIRQ_IRQ( _val ) \
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( ( ( _val ) << GRCAN_CANRXIRQ_IRQ_SHIFT ) & \
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GRCAN_CANRXIRQ_IRQ_MASK )
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/** @} */
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/**
|
|
* @defgroup RTEMSDeviceGRCANCanRxMASK \
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* Receive Channel Mask Register (CanRxMASK)
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*
|
|
* @brief This group contains register bit definitions.
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|
*
|
|
* @{
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|
*/
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#define GRCAN_CANRXMASK_AM_SHIFT 0
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#define GRCAN_CANRXMASK_AM_MASK 0x1fffffffU
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#define GRCAN_CANRXMASK_AM_GET( _reg ) \
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( ( ( _reg ) & GRCAN_CANRXMASK_AM_MASK ) >> \
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GRCAN_CANRXMASK_AM_SHIFT )
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#define GRCAN_CANRXMASK_AM_SET( _reg, _val ) \
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( ( ( _reg ) & ~GRCAN_CANRXMASK_AM_MASK ) | \
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( ( ( _val ) << GRCAN_CANRXMASK_AM_SHIFT ) & \
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GRCAN_CANRXMASK_AM_MASK ) )
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#define GRCAN_CANRXMASK_AM( _val ) \
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( ( ( _val ) << GRCAN_CANRXMASK_AM_SHIFT ) & \
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GRCAN_CANRXMASK_AM_MASK )
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/** @} */
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|
|
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/**
|
|
* @defgroup RTEMSDeviceGRCANCanRxCODE \
|
|
* Receive Channel Code Register (CanRxCODE)
|
|
*
|
|
* @brief This group contains register bit definitions.
|
|
*
|
|
* @{
|
|
*/
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|
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#define GRCAN_CANRXCODE_AC_SHIFT 0
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#define GRCAN_CANRXCODE_AC_MASK 0x1fffffffU
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|
#define GRCAN_CANRXCODE_AC_GET( _reg ) \
|
|
( ( ( _reg ) & GRCAN_CANRXCODE_AC_MASK ) >> \
|
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GRCAN_CANRXCODE_AC_SHIFT )
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|
#define GRCAN_CANRXCODE_AC_SET( _reg, _val ) \
|
|
( ( ( _reg ) & ~GRCAN_CANRXCODE_AC_MASK ) | \
|
|
( ( ( _val ) << GRCAN_CANRXCODE_AC_SHIFT ) & \
|
|
GRCAN_CANRXCODE_AC_MASK ) )
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|
#define GRCAN_CANRXCODE_AC( _val ) \
|
|
( ( ( _val ) << GRCAN_CANRXCODE_AC_SHIFT ) & \
|
|
GRCAN_CANRXCODE_AC_MASK )
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|
|
|
/** @} */
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|
|
|
/**
|
|
* @brief This structure defines the GRCAN register block memory map.
|
|
*/
|
|
typedef struct grcan {
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|
/**
|
|
* @brief See @ref RTEMSDeviceGRCANCanCONF.
|
|
*/
|
|
uint32_t canconf;
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|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRCANCanSTAT.
|
|
*/
|
|
uint32_t canstat;
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|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRCANCanCTRL.
|
|
*/
|
|
uint32_t canctrl;
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|
|
|
uint32_t reserved_c_18[ 3 ];
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|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRCANCanMASK.
|
|
*/
|
|
uint32_t canmask;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRCANCanCODE.
|
|
*/
|
|
uint32_t cancode;
|
|
|
|
uint32_t reserved_20_200[ 120 ];
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRCANCanTxCTRL.
|
|
*/
|
|
uint32_t cantxctrl;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRCANCanTxADDR.
|
|
*/
|
|
uint32_t cantxaddr;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRCANCanTxSIZE.
|
|
*/
|
|
uint32_t cantxsize;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRCANCanTxWR.
|
|
*/
|
|
uint32_t cantxwr;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRCANCanTxRD.
|
|
*/
|
|
uint32_t cantxrd;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRCANCanTxIRQ.
|
|
*/
|
|
uint32_t cantxirq;
|
|
|
|
uint32_t reserved_218_300[ 58 ];
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRCANCanRxCTRL.
|
|
*/
|
|
uint32_t canrxctrl;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRCANCanRxADDR.
|
|
*/
|
|
uint32_t canrxaddr;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRCANCanRxSIZE.
|
|
*/
|
|
uint32_t canrxsize;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRCANCanRxWR.
|
|
*/
|
|
uint32_t canrxwr;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRCANCanRxRD.
|
|
*/
|
|
uint32_t canrxrd;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRCANCanRxIRQ.
|
|
*/
|
|
uint32_t canrxirq;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRCANCanRxMASK.
|
|
*/
|
|
uint32_t canrxmask;
|
|
|
|
/**
|
|
* @brief See @ref RTEMSDeviceGRCANCanRxCODE.
|
|
*/
|
|
uint32_t canrxcode;
|
|
} grcan;
|
|
|
|
/** @} */
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* _GRLIB_GRCAN_REGS_H */
|