forked from Imagelibrary/rtems
33f6e34b2d
This patch changes the license to BSD-2 for all source files where the copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research. Some files also includes copyright right statements from OAR and/or embedded Brains in addition to Gaisler. Updates #3053.
221 lines
7.7 KiB
C
221 lines
7.7 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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* GRLIB L2CACHE Driver
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*
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* COPYRIGHT (c) 2017
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* Cobham Gaisler AB
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* OVERVIEW
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* ========
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* This driver controls the L2CACHE device located
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* at an on-chip AMBA.
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*/
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#ifndef __L2CACHE_H__
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#define __L2CACHE_H__
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#include <stdint.h>
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#include <stdio.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern void l2cache_register_drv(void);
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#define L2CACHE_ERR_OK 0
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#define L2CACHE_ERR_NOINIT -1
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#define L2CACHE_ERR_EINVAL -2
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#define L2CACHE_ERR_TOOMANY -3
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#define L2CACHE_ERR_ERROR -4
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/* L2C Flush options */
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#define L2CACHE_OPTIONS_FLUSH_WAIT (0x1 << 2)
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#define L2CACHE_OPTIONS_FLUSH_INVALIDATE (0x3 << 0)
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#define L2CACHE_OPTIONS_FLUSH_WRITEBACK (0x2 << 0)
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#define L2CACHE_OPTIONS_FLUSH_INV_WBACK (0x1 << 0)
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#define L2CACHE_OPTIONS_FLUSH_NONE (0 << 0)
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/* L2C Status */
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#define L2CACHE_STATUS_ENABLED 1
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#define L2CACHE_STATUS_SPLIT_ENABLED (0x1 << 1)
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#define L2CACHE_STATUS_EDAC_ENABLED (0x1 << 2)
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#define L2CACHE_STATUS_REPL (0x3 << L2CACHE_STATUS_REPL_BIT)
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#define L2CACHE_STATUS_REPL_BIT 3
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#define L2CACHE_STATUS_WRITETHROUGH (0x1 << 5)
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#define L2CACHE_STATUS_LOCK (0xf << L2CACHE_STATUS_LOCK_BIT)
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#define L2CACHE_STATUS_LOCK_BIT 6
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#define L2CACHE_STATUS_SCRUB_ENABLED (0x1 << 10)
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#define L2CACHE_STATUS_INT (0xf << L2CACHE_STATUS_INT_BIT)
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#define L2CACHE_STATUS_INT_BIT 11
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#define L2CACHE_STATUS_INT_BCKEND (0x1 << 11)
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#define L2CACHE_STATUS_INT_WPHIT (0x1 << 12)
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#define L2CACHE_STATUS_INT_UEE (0x1 << 13)
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#define L2CACHE_STATUS_INT_CEE (0x1 << 14)
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#define L2CACHE_STATUS_SCRUB_DELAY (0xffff << L2CACHE_STATUS_SCRUB_DELAY_BIT)
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#define L2CACHE_STATUS_SCRUB_DELAY_BIT 15
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#define L2CACHE_STATUS_SIGN_BIT 31
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/* status helper macros */
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#define L2CACHE_ENABLED(status) (status & L2CACHE_STATUS_ENABLED)
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#define L2CACHE_DISABLED(status) (!(status & L2CACHE_STATUS_ENABLED))
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#define L2CACHE_SPLIT_ENABLED(status) (status & L2CACHE_STATUS_SPLIT_ENABLED)
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#define L2CACHE_SPLIT_DISABLED(status) \
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(!(status & L2CACHE_STATUS_SPLIT_ENABLED))
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#define L2CACHE_EDAC_ENABLED(status) (status & L2CACHE_STATUS_EDAC_ENABLED)
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#define L2CACHE_EDAC_DISABLED(status) (!(status & L2CACHE_STATUS_EDAC_ENABLED))
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#define L2CACHE_REPL(status) \
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((status & L2CACHE_STATUS_REPL) >> L2CACHE_STATUS_REPL_BIT)
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#define L2CACHE_WRITETHROUGH(status) (status & L2CACHE_STATUS_WRITETHROUGH)
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#define L2CACHE_WRITEBACK(status) (!(status & L2CACHE_STATUS_WRITETHROUGH))
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#define L2CACHE_LOCKED_WAYS(status) \
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((status & L2CACHE_STATUS_LOCK) >> L2CACHE_STATUS_LOCK_BIT)
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#define L2CACHE_SCRUB_ENABLED(status) (status & L2CACHE_STATUS_SCRUB_ENABLED)
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#define L2CACHE_SCRUB_DISABLED(status) \
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(!(status & L2CACHE_STATUS_SCRUB_ENABLED))
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#define L2CACHE_SCRUB_DELAY(status) \
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((status & L2CACHE_STATUS_SCRUB_DELAY) >> L2CACHE_STATUS_SCRUB_DELAY_BIT)
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#define L2CACHE_INT_ENABLED(status) (status & L2CACHE_STATUS_INT)
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#define L2CACHE_INT_DISABLED(status) (!(status & L2CACHE_STATUS_INT))
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extern int l2cache_status(void);
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/* L2C Setup */
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extern int l2cache_enable(int flush);
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extern int l2cache_disable(int flush);
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extern int l2cache_split_enable(void);
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extern int l2cache_split_disable(void);
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extern int l2cache_edac_enable(int flush);
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extern int l2cache_edac_disable(int flush);
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extern int l2cache_scrub_enable(int delay);
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extern int l2cache_scrub_disable(void);
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extern int l2cache_scrub_line(int way, int index);
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extern int l2cache_writethrough(int flush);
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extern int l2cache_writeback(int flush);
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#define L2CACHE_OPTIONS_REPL_INDEX_WAY_BIT (2)
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#define L2CACHE_OPTIONS_REPL_MASTERIDX_MOD (3 << 0)
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#define L2CACHE_OPTIONS_REPL_MASTERIDX_IDX (2 << 0)
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#define L2CACHE_OPTIONS_REPL_RANDOM (1 << 0)
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#define L2CACHE_OPTIONS_REPL_LRU (0 << 0)
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extern int l2cache_replacement(int options, int flush);
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/* L2C Flush */
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extern int l2cache_flush(int flush);
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extern int l2cache_flush_address(uint32_t addr, int size, int flush);
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extern int l2cache_flush_line(int way, int index, int flush);
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extern int l2cache_flush_way(int way, int flush);
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/* L2C Lock way */
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#define L2CACHE_OPTIONS_DIRTY (0x1 << 2)
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#define L2CACHE_OPTIONS_VALID (0x1 << 1)
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#define L2CACHE_OPTIONS_FETCH (0x1 << 0)
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#define L2CACHE_OPTIONS_DISABLE 2
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#define L2CACHE_OPTIONS_ENABLE 1
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#define L2CACHE_OPTIONS_NONE 0
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extern int l2cache_lock_way(uint32_t tag, int options, int flush, int enable);
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extern int l2cache_unlock(void);
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/* L2C Fill a way */
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extern int l2cache_fill_way(int way, uint32_t tag, int options, int flush);
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/* L2C MTRR */
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#define L2CACHE_OPTIONS_MTRR_ACCESS_WRITETHROUGH (0x1 << 2)
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#define L2CACHE_OPTIONS_MTRR_ACCESS_UNCACHED (0x0 << 2)
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#define L2CACHE_OPTIONS_MTRR_WRITEPROT_ENABLE (0x1 << 1)
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#define L2CACHE_OPTIONS_MTRR_WRITEPROT_DISABLE (0x0 << 1)
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extern int l2cache_mtrr_enable(int id, uint32_t addr, uint32_t mask,
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int options, int flush);
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extern int l2cache_mtrr_disable(int id);
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/* L2C Debug print */
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extern int l2cache_print(void);
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/* L2C Interrupts */
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/* Function Interrupt-Code ISR callback prototype.
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* arg - Custom arg provided by user
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* addr - Cacheline addr that generated the error
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* status - Error status register of the L2CACHE core
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*/
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typedef void (*l2cache_isr_t)(void *arg, uint32_t addr, uint32_t status);
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#define L2CACHE_INTERRUPT_ALL (0xf << 0)
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#define L2CACHE_INTERRUPT_BACKENDERROR (0x1 << 3)
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#define L2CACHE_INTERRUPT_WPROTHIT (0x1 << 2)
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#define L2CACHE_INTERRUPT_UNCORRERROR (0x1 << 1)
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#define L2CACHE_INTERRUPT_CORRERROR (0x1 << 0)
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extern int l2cache_isr_register( l2cache_isr_t isr, void * arg, int options);
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extern int l2cache_isr_unregister(void);
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extern int l2cache_interrupt_mask(int options);
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extern int l2cache_interrupt_unmask(int options);
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/* L2C error interface */
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#define L2CACHE_STATUS_MULTIPLEERRORS 2
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#define L2CACHE_STATUS_NEWERROR 1
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#define L2CACHE_STATUS_NOERROR 0
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extern int l2cache_error_status(uint32_t * addr, uint32_t * status);
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/*#define TEST_L2CACHE*/
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#ifdef TEST_L2CACHE
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/* Used for internal testing */
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/*
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* L2CACHE Tag private data struture
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*/
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struct l2cache_tag {
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uint32_t tag;
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int valid;
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int dirty;
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int lru;
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};
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/*
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* L2CACHE Line private data struture
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*/
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struct l2cache_dataline {
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uint32_t data[16];
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int words;
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};
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extern int l2cache_get_index( uint32_t addr);
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extern uint32_t l2cache_get_tag( uint32_t addr);
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extern int l2cache_diag_tag( int way, int index, struct l2cache_tag * tag);
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extern int l2cache_diag_line( int way, int index,
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struct l2cache_dataline * dataline);
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#define L2CACHE_HIT 1
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#define L2CACHE_MISS 0
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extern int l2cache_lookup(uint32_t addr, int * way);
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extern int l2cache_error_inject_address( uint32_t addr, uint32_t mask);
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#endif /* TEST_L2CACHE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __L2CACHE_H__ */
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