forked from Imagelibrary/rtems
5cc075712e
Use the existing WRITE_SR() abstraction to access the interrupt group 0 and 1 enable registers. This fixes the build for the AArch32 target. Add BSP options which define the initial values of CPU Interface registers.
32 lines
746 B
YAML
32 lines
746 B
YAML
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
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build-type: objects
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cflags: []
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copyrights:
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- Copyright (C) 2022 embedded brains GmbH (http://www.embedded-brains.de)
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cppflags: []
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cxxflags: []
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enabled-by: true
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includes: []
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install:
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- destination: ${BSP_INCLUDEDIR}/dev/irq
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source:
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- bsps/include/dev/irq/arm-gicv3.h
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links:
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- role: build-dependency
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uid: optarmgic-icc-bpr0
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- role: build-dependency
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uid: optarmgic-icc-bpr1
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- role: build-dependency
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uid: optarmgic-icc-ctrl
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- role: build-dependency
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uid: optarmgic-icc-igrpen0
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- role: build-dependency
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uid: optarmgic-icc-igrpen1
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- role: build-dependency
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uid: optarmgic-icc-pmr
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- role: build-dependency
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uid: optarmgic-icc-sre
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source:
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- bsps/shared/dev/irq/arm-gicv3.c
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type: build
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