forked from Imagelibrary/rtems
8a2c3af9cf
This fixes some issues in the Xilinx support code that are critical to support the Cortex-R5F cores present in my Xilinx SoCs. The imported Cortex-R5 xil_cache.c matches the existing information in bsps/shared/xil/VERSION.
25 lines
669 B
YAML
25 lines
669 B
YAML
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
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build-type: objects
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cflags: []
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copyrights:
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- Copyright (C) 2022 On-Line Applications Research (OAR)
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cppflags: []
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cxxflags: []
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enabled-by:
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- bsps/aarch64/xilinx_versal
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- aarch64/xilinx_zynqmp_lp64_cfc400x
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- aarch64/xilinx_zynqmp_lp64_qemu
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- aarch64/xilinx_zynqmp_lp64_zu3eg
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includes: []
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install:
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- destination: ${BSP_INCLUDEDIR}
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source:
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- bsps/include/xil/arm/ARMv8/64bit/xil_cache.h
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- bsps/include/xil/arm/ARMv8/64bit/xil_exception.h
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- bsps/include/xil/arm/ARMv8/64bit/xpseudo_asm.h
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- bsps/include/xil/arm/ARMv8/64bit/xreg_cortexa53.h
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links: []
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source:
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- bsps/shared/xil/arm/ARMv8/xil_cache.c
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type: build
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