forked from Imagelibrary/rtems
9964895866
Adjust build support files to new directory layout. This patch is a part of the BSP source reorganization. Update #3285.
921 lines
19 KiB
ArmAsm
921 lines
19 KiB
ArmAsm
/*
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Based upon IDT provided code with the following release:
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This source code has been made available to you by IDT on an AS-IS
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basis. Anyone receiving this source is licensed under IDT copyrights
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to use it in any way he or she deems fit, including copying it,
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modifying it, compiling it, and redistributing it either with or
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without modifications. No license under IDT patents or patent
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applications is to be implied by the copyright license.
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Any user of this software should understand that IDT cannot provide
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technical support for this software and will not be responsible for
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any consequences resulting from the use of this software.
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Any person who transfers this source code or any derivative work must
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include the IDT copyright notice, this paragraph, and the preceeding
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two paragraphs in the transferred software.
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COPYRIGHT IDT CORPORATION 1996
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LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
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*/
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/************************************************************************
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**
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** idtmem.s - memory and cache functions
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**
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** Copyright 1991 Integrated Device Technology, Inc.
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** All Rights Reserved
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**
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**************************************************************************/
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/*
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* 950313: Ketan fixed bugs in mfc0/mtc0 hazards, and removed hack
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* to set mem_size.
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*/
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#include <rtems/mips/iregdef.h>
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#include <rtems/mips/idtcpu.h>
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#include <rtems/asm.h>
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.data
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mem_size:
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.word 0
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dcache_size:
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.word 0
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icache_size:
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#if __mips == 1
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.word MINCACHE
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#endif
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#if __mips == 3
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.word 0
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#endif
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#if __mips == 3
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.data
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scache_size:
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.word 0
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icache_linesize:
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.word 0
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dcache_linesize:
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.word 0
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scache_linesize:
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.word 0
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#endif
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.text
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#if __mips == 1
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#define CONFIGFRM ((2*4)+4)
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/*************************************************************************
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**
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** Config_Dcache() -- determine size of Data cache
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**
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**************************************************************************/
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FRAME(config_Dcache,sp, CONFIGFRM, ra)
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.set noreorder
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subu sp,CONFIGFRM
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sw ra,CONFIGFRM-4(sp) /* save return address */
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sw s0,4*4(sp) /* save s0 in first regsave slot */
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mfc0 s0,C0_SR /* save SR */
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nop
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mtc0 zero,C0_SR /* disable interrupts */
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.set reorder
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jal _size_cache /* returns Data cache size in v0 */
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sw v0, dcache_size /* save it */
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and s0, ~SR_PE /* do not clear PE */
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.set noreorder
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mtc0 s0,C0_SR /* restore SR */
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nop
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.set reorder
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lw s0, 4*4(sp) /* restore s0 */
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lw ra,CONFIGFRM-4(sp) /* restore ra */
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addu sp,CONFIGFRM /* pop stack */
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j ra
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ENDFRAME(config_Dcache)
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/*************************************************************************
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**
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** Config_Icache() -- determine size of Instruction cache
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** MUST be run in uncached mode/handled in idt_csu.s
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**
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**************************************************************************/
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FRAME(config_Icache,sp, CONFIGFRM, ra)
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.set noreorder
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subu sp,CONFIGFRM
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sw ra,CONFIGFRM-4(sp) /* save return address */
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sw s0,4*4(sp) /* save s0 in first regsave slot */
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mfc0 s0,C0_SR /* save SR */
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nop
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mtc0 zero, C0_SR /* disable interrupts */
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li v0,SR_SWC /* swap caches/disable ints */
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mtc0 v0,C0_SR
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nop
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.set reorder
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jal _size_cache /* returns instruction cache size */
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.set noreorder
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mtc0 zero,C0_SR /* swap back caches */
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nop
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and s0,~SR_PE /* do not inadvertantly clear PE */
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mtc0 s0,C0_SR /* restore SR */
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nop
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.set reorder
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sw v0, icache_size /* save it AFTER caches back */
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lw s0,4*4(sp) /* restore s0 */
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lw ra,CONFIGFRM-4(sp) /* restore ra */
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addu sp,CONFIGFRM /* pop stack */
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j ra
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ENDFRAME(config_Icache)
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/************************************************************************
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**
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** _size_cache()
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** returns cache size in v0
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**
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************************************************************************/
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FRAME(_size_cache,sp,0,ra)
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.set noreorder
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mfc0 t0,C0_SR /* save current sr */
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nop
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and t0,~SR_PE /* do not inadvertently clear PE */
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or v0,t0,SR_ISC /* isolate cache */
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mtc0 v0,C0_SR
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/*
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* First check if there is a cache there at all
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*/
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move v0,zero
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li v1,0xa5a5a5a5 /* distinctive pattern */
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sw v1,K0BASE /* try to write into cache */
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lw t1,K0BASE /* try to read from cache */
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nop
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mfc0 t2,C0_SR
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nop
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.set reorder
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and t2,SR_CM
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bne t2,zero,3f /* cache miss, must be no cache */
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bne v1,t1,3f /* data not equal -> no cache */
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/*
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* Clear cache size boundries to known state.
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*/
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li v0,MINCACHE
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1:
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sw zero,K0BASE(v0)
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sll v0,1
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ble v0,MAXCACHE,1b
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li v0,-1
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sw v0,K0BASE(zero) /* store marker in cache */
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li v0,MINCACHE /* MIN cache size */
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2: lw v1,K0BASE(v0) /* Look for marker */
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bne v1,zero,3f /* found marker */
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sll v0,1 /* cache size * 2 */
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ble v0,MAXCACHE,2b /* keep looking */
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move v0,zero /* must be no cache */
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.set noreorder
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3: mtc0 t0,C0_SR /* restore sr */
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j ra
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nop
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ENDFRAME(_size_cache)
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.set reorder
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#define FLUSHFRM (2*4)
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/***************************************************************************
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**
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** flush_Dcache() - flush entire Data cache
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**
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****************************************************************************/
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FRAME(flush_Dcache,sp,FLUSHFRM,ra)
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lw t2, dcache_size
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.set noreorder
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mfc0 t3,C0_SR /* save SR */
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nop
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and t3,~SR_PE /* dont inadvertently clear PE */
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beq t2,zero,_Dflush_done /* no D cache, get out! */
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nop
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li v0, SR_ISC /* isolate cache */
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mtc0 v0, C0_SR
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nop
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.set reorder
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li t0,K0BASE /* set loop registers */
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or t1,t0,t2
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2: sb zero,0(t0)
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sb zero,4(t0)
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sb zero,8(t0)
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sb zero,12(t0)
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sb zero,16(t0)
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sb zero,20(t0)
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sb zero,24(t0)
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addu t0,32
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sb zero,-4(t0)
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bne t0,t1,2b
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.set noreorder
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_Dflush_done:
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mtc0 t3,C0_SR /* restore Status Register */
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.set reorder
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j ra
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ENDFRAME(flush_Dcache)
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/***************************************************************************
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**
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** flush_Icache() - flush entire Instruction cache
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**
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** NOTE: Icache can only be flushed/cleared when uncached
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** Code forces into uncached memory regardless of calling mode
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**
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****************************************************************************/
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FRAME(flush_Icache,sp,FLUSHFRM,ra)
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lw t1,icache_size
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.set noreorder
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mfc0 t3,C0_SR /* save SR */
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nop
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la v0,1f
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li v1,K1BASE
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or v0,v1
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j v0 /* force into non-cached space */
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nop
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1:
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and t3,~SR_PE /* dont inadvertently clear PE */
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beq t1,zero,_Iflush_done /* no i-cache get out */
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nop
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li v0,SR_ISC|SR_SWC /* disable intr, isolate and swap */
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mtc0 v0,C0_SR
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li t0,K0BASE
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.set reorder
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or t1,t0,t1
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1: sb zero,0(t0)
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sb zero,4(t0)
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sb zero,8(t0)
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sb zero,12(t0)
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sb zero,16(t0)
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sb zero,20(t0)
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sb zero,24(t0)
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addu t0,32
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sb zero,-4(t0)
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bne t0,t1,1b
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.set noreorder
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_Iflush_done:
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mtc0 t3,C0_SR /* un-isolate, enable interrupts */
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.set reorder
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j ra
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ENDFRAME(flush_Icache)
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/**************************************************************************
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**
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** clear_Dcache(base_addr, byte_count) - flush portion of Data cache
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**
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** a0 = base address of portion to be cleared
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** a1 = byte count of length
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**
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***************************************************************************/
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FRAME(clear_Dcache,sp,0,ra)
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lw t2, dcache_size /* Data cache size */
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.set noreorder
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mfc0 t3,C0_SR /* save SR */
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nop
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and t3,~SR_PE /* dont inadvertently clear PE */
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nop
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nop
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.set reorder
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/*
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* flush data cache
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*/
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.set noreorder
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nop
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li v0,SR_ISC /* isolate data cache */
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mtc0 v0,C0_SR
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.set reorder
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bltu t2,a1,1f /* cache is smaller than region */
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move t2,a1
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1: addu t2,a0 /* ending address + 1 */
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move t0,a0
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1: sb zero,0(t0)
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sb zero,4(t0)
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sb zero,8(t0)
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sb zero,12(t0)
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sb zero,16(t0)
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sb zero,20(t0)
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sb zero,24(t0)
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addu t0,32
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sb zero,-4(t0)
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bltu t0,t2,1b
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.set noreorder
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mtc0 t3,C0_SR /* un-isolate, enable interrupts */
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nop
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.set reorder
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j ra
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ENDFRAME(clear_Dcache)
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/**************************************************************************
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**
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** clear_Icache(base_addr, byte_count) - flush portion of Instruction cache
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**
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** a0 = base address of portion to be cleared
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** a1 = byte count of length
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**
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** NOTE: Icache can only be flushed/cleared when uncached
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** Code forces into uncached memory regardless of calling mode
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**
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***************************************************************************/
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FRAME(clear_Icache,sp,0,ra)
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lw t1, icache_size /* Instruction cache size */
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/*
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* flush text cache
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*/
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.set noreorder
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mfc0 t3,C0_SR /* save SR */
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nop
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la v0,1f
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li v1,K1BASE
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or v0,v1
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j v0 /* force into non-cached space */
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nop
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1:
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and t3,~SR_PE /* dont inadvertently clear PE */
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nop
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nop
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li v0,SR_ISC|SR_SWC /* disable intr, isolate and swap */
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mtc0 v0,C0_SR
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.set reorder
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bltu t1,a1,1f /* cache is smaller than region */
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move t1,a1
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1: addu t1,a0 /* ending address + 1 */
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move t0,a0
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sb zero,0(t0)
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sb zero,4(t0)
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sb zero,8(t0)
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sb zero,12(t0)
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sb zero,16(t0)
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sb zero,20(t0)
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sb zero,24(t0)
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addu t0,32
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sb zero,-4(t0)
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bltu t0,t1,1b
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.set noreorder
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mtc0 t3,C0_SR /* un-isolate, enable interrupts */
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nop
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nop
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nop /* allow time for caches to swap */
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.set reorder
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j ra
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ENDFRAME(clear_Icache)
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/**************************************************************************
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**
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** get_mem_conf - get memory configuration
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**
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***************************************************************************/
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FRAME(get_mem_conf,sp,0,ra)
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lw t6, mem_size
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sw t6, 0(a0)
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lw t7, icache_size
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sw t7, 4(a0)
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lw t8, dcache_size
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sw t8, 8(a0)
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j ra
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ENDFRAME(get_mem_conf)
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#endif /* __mips == 1 */
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#if __mips == 3
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#define LEAF(label) FRAME(label,sp,0,ra)
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#define XLEAF(label) \
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.globl label ; \
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label:
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/*
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* cacheop macro to automate cache operations
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* first some helpers...
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*/
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#define _mincache(size, maxsize) \
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bltu size,maxsize,8f ; \
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move size,maxsize ; \
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8:
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#define _align(tmp, minaddr, maxaddr, linesize) \
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subu tmp,linesize,1 ; \
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not tmp ; \
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and minaddr,tmp ; \
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addu maxaddr,-1 ; \
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and maxaddr,tmp
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/* This is a bit of a hack really because it relies on minaddr=a0 */
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#define _doop1(op1) \
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cache op1,0(a0)
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#define _doop2(op1, op2) \
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cache op1,0(a0) ; \
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cache op2,0(a0)
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/* specials for cache initialisation */
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#define _doop1lw1(op1) \
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cache op1,0(a0) ; \
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lw zero,0(a0) ; \
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cache op1,0(a0)
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#define _doop121(op1,op2) \
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cache op1,0(a0) ; \
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nop; \
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cache op2,0(a0) ; \
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nop; \
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cache op1,0(a0)
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#define _oploopn(minaddr, maxaddr, linesize, tag, ops) \
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.set noreorder ; \
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7: _doop##tag##ops ; \
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bne minaddr,maxaddr,7b ; \
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addu minaddr,linesize ; \
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.set reorder
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/* finally the cache operation macros */
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#define icacheopn(kva, n, cache_size, cache_linesize, tag, ops) \
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_mincache(n, cache_size); \
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blez n,9f ; \
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addu n,kva ; \
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_align(t1, kva, n, cache_linesize) ; \
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_oploopn(kva, n, cache_linesize, tag, ops) ; \
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9:
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#define vcacheopn(kva, n, cache_size, cache_linesize, tag, ops) \
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blez n,9f ; \
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addu n,kva ; \
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_align(t1, kva, n, cache_linesize) ; \
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_oploopn(kva, n, cache_linesize, tag, ops) ; \
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9:
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#define icacheop(kva, n, cache_size, cache_linesize, op) \
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icacheopn(kva, n, cache_size, cache_linesize, 1, (op))
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#define vcacheop(kva, n, cache_size, cache_linesize, op) \
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vcacheopn(kva, n, cache_size, cache_linesize, 1, (op))
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.text
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/*
|
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* static void _size_cache() R4000
|
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*
|
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* Internal routine to determine cache sizes by looking at R4000 config
|
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* register. Sizes are returned in registers, as follows:
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* t2 icache size
|
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* t3 dcache size
|
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* t6 scache size
|
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* t4 icache line size
|
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* t5 dcache line size
|
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* t7 scache line size
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*/
|
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LEAF(_size_cache)
|
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mfc0 t0,C0_CONFIG
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|
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and t1,t0,CFG_ICMASK
|
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srl t1,CFG_ICSHIFT
|
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li t2,0x1000
|
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sll t2,t1
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|
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and t1,t0,CFG_DCMASK
|
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srl t1,CFG_DCSHIFT
|
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li t3,0x1000
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sll t3,t1
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li t4,32
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and t1,t0,CFG_IB
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bnez t1,1f
|
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li t4,16
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1:
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li t5,32
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and t1,t0,CFG_DB
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bnez t1,1f
|
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li t5,16
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1:
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move t6,zero # default to no scache
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move t7,zero #
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and t1,t0,CFG_C_UNCACHED # test config register
|
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bnez t1,1f # no scache if uncached/non-coherent
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|
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li t6,0x100000 # assume 1Mb scache <<-NOTE
|
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and t1,t0,CFG_SBMASK
|
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srl t1,CFG_SBSHIFT
|
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li t7,16
|
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sll t7,t1
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1: j ra
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ENDFRAME(_size_cache)
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|
|
/*
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* void config_cache() R4000
|
|
*
|
|
* Work out size of I, D & S caches, assuming they are already initialised.
|
|
*/
|
|
LEAF(config_cache)
|
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lw t0,icache_size
|
|
bgtz t0,8f # already known?
|
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move v0,ra
|
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bal _size_cache
|
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move ra,v0
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|
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sw t2,icache_size
|
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sw t3,dcache_size
|
|
sw t6,scache_size
|
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sw t4,icache_linesize
|
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sw t5,dcache_linesize
|
|
sw t7,scache_linesize
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8: j ra
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ENDFRAME(config_cache)
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|
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/*
|
|
* void _init_cache() R4000
|
|
*/
|
|
LEAF(_init_cache)
|
|
/*
|
|
* First work out the sizes
|
|
*/
|
|
move v0,ra
|
|
bal _size_cache
|
|
move ra,v0
|
|
|
|
/*
|
|
* The caches may be in an indeterminate state,
|
|
* so we force good parity into them by doing an
|
|
* invalidate, load/fill, invalidate for each line.
|
|
*/
|
|
|
|
/* disable all i/u and cache exceptions */
|
|
mfc0 v0,C0_SR
|
|
and v1,v0,~SR_IE
|
|
or v1,SR_DE
|
|
mtc0 v1,C0_SR
|
|
|
|
mtc0 zero,C0_TAGLO
|
|
mtc0 zero,C0_TAGHI
|
|
|
|
/* assume bottom of RAM will generate good parity for the cache */
|
|
li a0,PHYS_TO_K0(0)
|
|
move a2,t2 # icache_size
|
|
move a3,t4 # icache_linesize
|
|
move a1,a2
|
|
icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill_I))
|
|
|
|
li a0,PHYS_TO_K0(0)
|
|
move a2,t3 # dcache_size
|
|
move a3,t5 # dcache_linesize
|
|
move a1,a2
|
|
icacheopn(a0,a1,a2,a3,1lw1,(Index_Store_Tag_D))
|
|
|
|
/* assume unified I & D in scache <<-NOTE */
|
|
blez t6,1f
|
|
li a0,PHYS_TO_K0(0)
|
|
move a2,t6
|
|
move a3,t7
|
|
move a1,a2
|
|
icacheopn(a0,a1,a2,a3,1lw1,(Index_Store_Tag_SD))
|
|
|
|
1: mtc0 v0,C0_SR
|
|
j ra
|
|
ENDFRAME(_init_cache)
|
|
|
|
/*
|
|
* void flush_cache (void) R4000
|
|
*
|
|
* Flush and invalidate all caches
|
|
*/
|
|
LEAF(flush_cache)
|
|
/* secondary cacheops do all the work if present */
|
|
lw a2,scache_size
|
|
blez a2,1f
|
|
lw a3,scache_linesize
|
|
li a0,PHYS_TO_K0(0)
|
|
move a1,a2
|
|
icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD)
|
|
b 2f
|
|
|
|
1:
|
|
lw a2,icache_size
|
|
blez a2,2f
|
|
lw a3,icache_linesize
|
|
li a0,PHYS_TO_K0(0)
|
|
move a1,a2
|
|
icacheop(a0,a1,a2,a3,Index_Invalidate_I)
|
|
|
|
lw a2,dcache_size
|
|
lw a3,dcache_linesize
|
|
li a0,PHYS_TO_K0(0)
|
|
move a1,a2
|
|
icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)
|
|
|
|
2: j ra
|
|
ENDFRAME(flush_cache)
|
|
|
|
/*
|
|
* void flush_cache_nowrite (void) R4000
|
|
*
|
|
* Invalidate all caches
|
|
*/
|
|
LEAF(flush_cache_nowrite)
|
|
mfc0 v0,C0_SR
|
|
and v1,v0,~SR_IE
|
|
mtc0 v1,C0_SR
|
|
|
|
mtc0 zero,C0_TAGLO
|
|
mtc0 zero,C0_TAGHI
|
|
|
|
lw a2,icache_size
|
|
blez a2,2f
|
|
lw a3,icache_linesize
|
|
li a0,PHYS_TO_K0(0)
|
|
move a1,a2
|
|
icacheop(a0,a1,a2,a3,Index_Invalidate_I)
|
|
|
|
lw a2,dcache_size
|
|
lw a3,dcache_linesize
|
|
li a0,PHYS_TO_K0(0)
|
|
move a1,a2
|
|
icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
|
|
|
|
lw a2,scache_size
|
|
blez a2,2f
|
|
lw a3,scache_linesize
|
|
li a0,PHYS_TO_K0(0)
|
|
move a1,a2
|
|
icacheop(a0,a1,a2,a3,Index_Store_Tag_SD)
|
|
|
|
2: mtc0 v0,C0_SR
|
|
j ra
|
|
ENDFRAME(flush_cache_nowrite)
|
|
|
|
/*
|
|
* void clean_cache (unsigned kva, size_t n) R4000
|
|
*
|
|
* Writeback and invalidate address range in all caches
|
|
*/
|
|
LEAF(clean_cache)
|
|
XLEAF(clear_cache)
|
|
|
|
/* secondary cacheops do all the work (if fitted) */
|
|
lw a2,scache_size
|
|
blez a2,1f
|
|
lw a3,scache_linesize
|
|
vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_SD)
|
|
b 2f
|
|
|
|
1: lw a2,icache_size
|
|
blez a2,2f
|
|
lw a3,icache_linesize
|
|
/* save kva & n for subsequent loop */
|
|
move t8,a0
|
|
move t9,a1
|
|
vcacheop(a0,a1,a2,a3,Hit_Invalidate_I)
|
|
|
|
lw a2,dcache_size
|
|
lw a3,dcache_linesize
|
|
/* restore kva & n */
|
|
move a0,t8
|
|
move a1,t9
|
|
vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)
|
|
|
|
2: j ra
|
|
ENDFRAME(clean_cache)
|
|
|
|
/*
|
|
* void clean_dcache (unsigned kva, size_t n) R4000
|
|
*
|
|
* Writeback and invalidate address range in primary data cache
|
|
*/
|
|
LEAF(clean_dcache)
|
|
lw a2,dcache_size
|
|
blez a2,2f
|
|
lw a3,dcache_linesize
|
|
|
|
vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)
|
|
|
|
2: j ra
|
|
ENDFRAME(clean_dcache)
|
|
|
|
/*
|
|
* void clean_dcache_indexed (unsigned kva, size_t n) R4000
|
|
*
|
|
* Writeback and invalidate indexed range in primary data cache
|
|
*/
|
|
LEAF(clean_dcache_indexed)
|
|
lw a2,dcache_size
|
|
blez a2,2f
|
|
lw a3,dcache_linesize
|
|
|
|
#ifdef CPU_ORION
|
|
srl a2,1 # do one set (half cache) at a time
|
|
move t8,a0 # save kva & n
|
|
move t9,a1
|
|
icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)
|
|
|
|
addu a0,t8,a2 # do next set
|
|
move a1,t9 # restore n
|
|
#endif
|
|
icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)
|
|
|
|
2: j ra
|
|
ENDFRAME(clean_dcache_indexed)
|
|
|
|
/*
|
|
* void clean_dcache_nowrite (unsigned kva, size_t n) R4000
|
|
*
|
|
* Invalidate an address range in primary data cache
|
|
*/
|
|
LEAF(clean_dcache_nowrite)
|
|
lw a2,dcache_size
|
|
blez a2,2f
|
|
lw a3,dcache_linesize
|
|
|
|
vcacheop(a0,a1,a2,a3,Hit_Invalidate_D)
|
|
|
|
2: j ra
|
|
ENDFRAME(clean_dcache_nowrite)
|
|
|
|
/*
|
|
* void clean_dcache_nowrite_indexed (unsigned kva, size_t n) R4000
|
|
*
|
|
* Invalidate indexed range in primary data cache
|
|
*/
|
|
LEAF(clean_dcache_nowrite_indexed)
|
|
mfc0 v0,C0_SR
|
|
and v1,v0,~SR_IE
|
|
mtc0 v1,C0_SR
|
|
|
|
mtc0 zero,C0_TAGLO
|
|
mtc0 zero,C0_TAGHI
|
|
|
|
lw a2,dcache_size
|
|
blez a2,2f
|
|
lw a3,dcache_linesize
|
|
|
|
#ifdef CPU_ORION
|
|
srl a2,1 # do one set (half cache) at a time
|
|
move t8,a0 # save kva & n
|
|
move t9,a1
|
|
icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
|
|
|
|
addu a0,t8,a2 # do next set
|
|
move a1,t9 # restore n
|
|
#endif
|
|
icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
|
|
|
|
2: mtc0 v0,C0_SR
|
|
j ra
|
|
ENDFRAME(clean_dcache_nowrite_indexed)
|
|
|
|
/*
|
|
* void clean_icache (unsigned kva, size_t n) R4000
|
|
*
|
|
* Invalidate address range in primary instruction cache
|
|
*/
|
|
LEAF(clean_icache)
|
|
lw a2,icache_size
|
|
blez a2,2f
|
|
lw a3,icache_linesize
|
|
|
|
vcacheop(a0,a1,a2,a3,Hit_Invalidate_I)
|
|
|
|
2: j ra
|
|
ENDFRAME(clean_icache)
|
|
|
|
/*
|
|
* void clean_icache_indexed (unsigned kva, size_t n) R4000
|
|
*
|
|
* Invalidate indexed range in primary instruction cache
|
|
*/
|
|
LEAF(clean_icache_indexed)
|
|
lw a2,icache_size
|
|
blez a2,2f
|
|
lw a3,icache_linesize
|
|
|
|
#ifdef CPU_ORION
|
|
srl a2,1 # do one set (half cache) at a time
|
|
move t8,a0 # save kva & n
|
|
move t9,a1
|
|
icacheop(a0,a1,a2,a3,Index_Invalidate_I)
|
|
|
|
addu a0,t8,a2 # do next set
|
|
move a1,t9 # restore n
|
|
#endif
|
|
icacheop(a0,a1,a2,a3,Index_Invalidate_I)
|
|
|
|
2: j ra
|
|
ENDFRAME(clean_icache_indexed)
|
|
|
|
/*
|
|
* void clean_scache (unsigned kva, size_t n) R4000
|
|
*
|
|
* Writeback and invalidate address range in secondary cache
|
|
*/
|
|
LEAF(clean_scache)
|
|
lw a2,scache_size
|
|
blez a2,2f
|
|
lw a3,scache_linesize
|
|
vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_SD)
|
|
|
|
2: j ra
|
|
ENDFRAME(clean_scache)
|
|
|
|
/*
|
|
* void clean_scache_indexed (unsigned kva, size_t n) R4000
|
|
*
|
|
* Writeback and invalidate indexed range in secondary cache
|
|
*/
|
|
LEAF(clean_scache_indexed)
|
|
lw a2,scache_size
|
|
blez a2,2f
|
|
lw a3,scache_linesize
|
|
|
|
icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD)
|
|
|
|
2: j ra
|
|
ENDFRAME(clean_scache_indexed)
|
|
|
|
/*
|
|
* void clean_scache_nowrite (unsigned kva, size_t n) R4000
|
|
*
|
|
* Invalidate an address range in secondary cache
|
|
*/
|
|
LEAF(clean_scache_nowrite)
|
|
lw a2,scache_size
|
|
blez a2,2f
|
|
lw a3,scache_linesize
|
|
|
|
vcacheop(a0,a1,a2,a3,Hit_Invalidate_SD)
|
|
|
|
2: j ra
|
|
ENDFRAME(clean_scache_nowrite)
|
|
|
|
/*
|
|
* void clean_scache_nowrite_indexed (unsigned kva, size_t n) R4000
|
|
*
|
|
* Invalidate indexed range in secondary cache
|
|
*/
|
|
LEAF(clean_scache_nowrite_indexed)
|
|
mfc0 v0,C0_SR
|
|
and v1,v0,~SR_IE
|
|
mtc0 v1,C0_SR
|
|
|
|
mtc0 zero,C0_TAGLO
|
|
mtc0 zero,C0_TAGHI
|
|
|
|
lw a2,scache_size
|
|
blez a2,2f
|
|
lw a3,scache_linesize
|
|
|
|
icacheop(a0,a1,a2,a3,Index_Store_Tag_SD)
|
|
|
|
2: mtc0 v0,C0_SR
|
|
j ra
|
|
ENDFRAME(clean_scache_nowrite_indexed)
|
|
|
|
/**************************************************************************
|
|
**
|
|
** get_mem_conf - get memory configuration R4000
|
|
**
|
|
***************************************************************************/
|
|
|
|
FRAME(get_mem_conf,sp,0,ra)
|
|
|
|
lw t6, mem_size
|
|
sw t6, 0(a0)
|
|
lw t7, icache_size
|
|
sw t7, 4(a0)
|
|
lw t8, dcache_size
|
|
sw t8, 8(a0)
|
|
lw t7, scache_size
|
|
sw t7, 12(a0)
|
|
j ra
|
|
|
|
ENDFRAME(get_mem_conf)
|
|
|
|
#endif /* __mips == 3 */
|
|
|
|
/*
|
|
* void set_mem_size (mem_size)
|
|
*
|
|
* config_memory()'s memory size gets written into mem_size here.
|
|
* Now we don't need to call config_cache() with memory size - New to IDTC6.0
|
|
*/
|
|
FRAME(set_memory_size,sp,0,ra)
|
|
sw a0, mem_size
|
|
j ra
|
|
ENDFRAME(set_memory_size)
|