forked from Imagelibrary/rtems
299 lines
8.4 KiB
C
299 lines
8.4 KiB
C
/*
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* Copyright (c) 2014 Aeroflex Gaisler AB. All rights reserved.
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <rtems/score/atomic.h>
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#include <rtems/score/smpbarrier.h>
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#include <rtems.h>
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#include <limits.h>
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#include <string.h>
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#include "tmacros.h"
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const char rtems_test_name[] = "SMPCACHE 1";
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CPU_STRUCTURE_ALIGNMENT static int data_to_flush[1024];
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#define CPU_COUNT 32
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#define WORKER_PRIORITY 100
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typedef void (*Cache_manager_Function_ptr)(const void *d_addr, size_t n_bytes);
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void
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_Cache_manager_Send_smp_msg(
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const size_t setsize,
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const cpu_set_t *set,
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Cache_manager_Function_ptr func,
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const void * addr,
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size_t size
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);
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typedef struct {
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SMP_barrier_Control barrier;
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uint32_t count[CPU_COUNT];
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} test_context;
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static test_context ctx = {
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.barrier = SMP_BARRIER_CONTROL_INITIALIZER,
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};
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static void function_to_flush( void )
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{
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/* Does nothing. Used to give a pointer to instruction address space. */
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}
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static void test_cache_message( const void *d_addr, size_t n_bytes )
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{
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rtems_test_assert(n_bytes == 123);
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rtems_test_assert(d_addr == 0);
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ctx.count[rtems_get_current_processor()]++;
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}
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static void cache_manager_smp_functions( size_t set_size,
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cpu_set_t *cpu_set )
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{
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rtems_cache_flush_multiple_data_lines_processor_set( &data_to_flush,
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sizeof(data_to_flush), set_size, cpu_set );
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rtems_cache_invalidate_multiple_data_lines_processor_set( &data_to_flush,
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sizeof(data_to_flush), set_size, cpu_set );
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rtems_cache_flush_entire_data_processor_set( set_size, cpu_set );
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rtems_cache_invalidate_entire_instruction();
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rtems_cache_invalidate_multiple_instruction_lines( &function_to_flush,
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4 /* arbitrary size */ );
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}
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static void standard_funcs_test( size_t set_size, cpu_set_t *cpu_set )
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{
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cache_manager_smp_functions( set_size, cpu_set );
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}
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static void standard_funcs_isrdisabled_test( size_t set_size,
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cpu_set_t *cpu_set, SMP_barrier_State *bs )
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{
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ISR_Level isr_level;
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_ISR_Disable_without_giant( isr_level );
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_SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() );
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cache_manager_smp_functions( set_size, cpu_set );
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_ISR_Enable_without_giant( isr_level );
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}
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static void standard_funcs_giant_taken_test( size_t set_size,
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cpu_set_t *cpu_set, SMP_barrier_State *bs )
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{
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if ( rtems_get_current_processor() == 0)
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_Giant_Acquire();
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_SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() );
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cache_manager_smp_functions( set_size, cpu_set );
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if ( rtems_get_current_processor() == 0)
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_Giant_Release();
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}
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static void test_func_test( size_t set_size, cpu_set_t *cpu_set,
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SMP_barrier_State *bs )
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{
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ctx.count[rtems_get_current_processor()] = 0;
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_SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() );
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_Cache_manager_Send_smp_msg( set_size, cpu_set, test_cache_message, 0, 123 );
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_SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() );
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rtems_test_assert( ctx.count[rtems_get_current_processor()] ==
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rtems_get_processor_count() );
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}
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static void test_func_isrdisabled_test( size_t set_size, cpu_set_t *cpu_set,
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SMP_barrier_State *bs )
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{
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ISR_Level isr_level;
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ctx.count[rtems_get_current_processor()] = 0;
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_ISR_Disable_without_giant( isr_level );
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_SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() );
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_Cache_manager_Send_smp_msg( set_size, cpu_set, test_cache_message, 0, 123 );
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_SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() );
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rtems_test_assert( ctx.count[rtems_get_current_processor()] ==
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rtems_get_processor_count() );
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_ISR_Enable_without_giant( isr_level );
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}
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static void test_func_giant_taken_test( size_t set_size, cpu_set_t *cpu_set,
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SMP_barrier_State *bs )
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{
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ctx.count[rtems_get_current_processor()] = 0;
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if ( rtems_get_current_processor() == 0)
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_Giant_Acquire();
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_SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() );
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_Cache_manager_Send_smp_msg( set_size, cpu_set, test_cache_message, 0, 123 );
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_SMP_barrier_Wait( &ctx.barrier, bs, rtems_get_processor_count() );
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rtems_test_assert( ctx.count[rtems_get_current_processor()] ==
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rtems_get_processor_count() );
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if ( rtems_get_current_processor() == 0)
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_Giant_Release();
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}
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static void cmlog( const char* str )
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{
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if ( rtems_get_current_processor() == 0 )
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printf( "%s", str );
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}
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static void all_tests( void )
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{
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uint32_t cpu_count = rtems_get_processor_count();
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size_t set_size = CPU_ALLOC_SIZE( rtems_get_processor_count() );
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cpu_set_t *cpu_set = CPU_ALLOC( rtems_get_processor_count() );
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SMP_barrier_State bs = SMP_BARRIER_STATE_INITIALIZER;
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/* Send message to all available CPUs */
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CPU_FILL_S( set_size, cpu_set );
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/* Call SMP cache manager functions */
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cmlog( "Calling standard SMP cache functions. " );
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_SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count );
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standard_funcs_test( set_size, cpu_set );
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_SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count );
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cmlog( "Done!\n");
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/* Call SMP cache manager functions with ISR disabled */
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cmlog( "Calling standard SMP cache functions with ISR disabled. " );
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_SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count );
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standard_funcs_isrdisabled_test( set_size, cpu_set, &bs );
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_SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count );
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cmlog( "Done!\n" );
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/* Call SMP cache manager functions with core 0 holding the giant lock */
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cmlog( "Calling standard SMP cache functions with CPU0 holding "
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"the giant lock. " );
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_SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count );
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standard_funcs_giant_taken_test( set_size, cpu_set, &bs );
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_SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count );
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cmlog( "Done!\n");
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/* Call a test function using SMP cache manager and verify that all
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* cores invoke the function */
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cmlog( "Calling a test function using the SMP cache manager to "
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"verify that all CPUs receive the SMP message. " );
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_SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count );
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test_func_test( set_size, cpu_set, &bs );
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_SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count );
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cmlog( "Done!\n");
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/* Call a test function using SMP cache manager and verify that all
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* cores invoke the function. ISR disabled. */
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cmlog( "Calling a test function using the SMP cache manager to "
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"verify that all CPUs receive the SMP message. With ISR disabled. " );
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_SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count );
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test_func_isrdisabled_test( set_size, cpu_set, &bs );
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_SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count );
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cmlog( "Done!\n" );
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/* Call a test function using SMP cache manager and verify that all
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* cores invoke the function. Core 0 holding giant lock. */
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cmlog( "Calling a test function using the SMP cache manager to "
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"verify that all CPUs receive the SMP message. With CPU0 "
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"holding the giant lock. " );
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_SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count );
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test_func_giant_taken_test( set_size, cpu_set, &bs );
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_SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count );
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cmlog( "Done!\n" );
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/* Done. Free up memory. */
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_SMP_barrier_Wait( &ctx.barrier, &bs, cpu_count);
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CPU_FREE( cpu_set );
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}
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static void worker_task(rtems_task_argument arg)
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{
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rtems_status_code sc;
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all_tests();
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sc = rtems_task_suspend(RTEMS_SELF);
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rtems_test_assert(sc == RTEMS_SUCCESSFUL);
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}
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static void test_smp_cache_manager( void )
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{
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rtems_status_code sc;
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size_t worker_index;
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uint32_t cpu_count = rtems_get_processor_count();
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for (worker_index = 1; worker_index < cpu_count; ++worker_index) {
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rtems_id worker_id;
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sc = rtems_task_create(
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rtems_build_name('W', 'R', 'K', '0'+worker_index),
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WORKER_PRIORITY,
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RTEMS_MINIMUM_STACK_SIZE,
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RTEMS_DEFAULT_MODES,
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RTEMS_DEFAULT_ATTRIBUTES,
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&worker_id
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);
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rtems_test_assert( sc == RTEMS_SUCCESSFUL );
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sc = rtems_task_start( worker_id, worker_task, 0 );
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rtems_test_assert( sc == RTEMS_SUCCESSFUL );
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}
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all_tests();
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}
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static void Init(rtems_task_argument arg)
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{
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TEST_BEGIN();
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test_smp_cache_manager();
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TEST_END();
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rtems_test_exit(0);
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}
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#define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
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#define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER
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#define CONFIGURE_SMP_APPLICATION
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#define CONFIGURE_SMP_MAXIMUM_PROCESSORS CPU_COUNT
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#define CONFIGURE_MAXIMUM_TASKS CPU_COUNT
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#define CONFIGURE_MAXIMUM_TIMERS 1
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#define CONFIGURE_INITIAL_EXTENSIONS RTEMS_TEST_INITIAL_EXTENSION
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#define CONFIGURE_RTEMS_INIT_TASKS_TABLE
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#define CONFIGURE_INIT
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#include <rtems/confdefs.h>
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