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PR 1793/doc * .cvsignore, Makefile.am, README, configure.ac, index.html.in, main.am, project.am, ada_user/.cvsignore, ada_user/ada_user.texi, ada_user/example.texi, bsp_howto/.cvsignore, bsp_howto/bsp_howto.texi, cpu_supplement/.cvsignore, cpu_supplement/cpu_supplement.texi, cpu_supplement/preface.texi, develenv/.cvsignore, develenv/develenv.texi, develenv/intro.texi, filesystem/.cvsignore, filesystem/filesystem.texi, filesystem/preface.texi, networking/.cvsignore, networking/networking.texi, networking/preface.texi, porting/.cvsignore, porting/porting.texi, porting/preface.texi, posix1003.1/.cvsignore, posix1003.1/posix1003_1.texi, posix_users/.cvsignore, posix_users/posix_users.texi, posix_users/preface.texi, shell/.cvsignore, shell/preface.texi, shell/shell.texi, started/.cvsignore, started/started.texi, user/.cvsignore, user/c_user.texi, user/dirstat.texi, user/example.texi, user/glossary.texi, user/preface.texi: Convert from texi2www to texi2html. * texi2html_init.in: New file. * rtems_footer.html.in, rtems_header.html.in: Removed.
54 lines
2.2 KiB
Plaintext
54 lines
2.2 KiB
Plaintext
@c
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@c COPYRIGHT (c) 1989-2011.
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@c On-Line Applications Research Corporation (OAR).
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@c All rights reserved.
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@c
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@c $Id$
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@c
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@node Preface, Port Specific Information, Top, Top
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@unnumbered Preface
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The Real Time Executive for Multiprocessor Systems
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(RTEMS) is designed to be portable across multiple processor
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architectures. However, the nature of real-time systems makes
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it essential that the application designer understand certain
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processor dependent implementation details. These processor
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dependencies include calling convention, board support package
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issues, interrupt processing, exact RTEMS memory requirements,
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performance data, header files, and the assembly language
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interface to the executive.
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Each architecture represents a CPU family and usually there are
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a wide variety of CPU models within it. These models share a
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common Instruction Set Architecture (ISA) which often varies
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based upon some well-defined rules. There are often
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multiple implementations of the ISA and these may be from
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one or multiple vendors.
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On top of variations in the ISA, there may also be variations
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which occur when a CPU core implementation is combined with
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a set of peripherals to form a system on chip. For example,
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there are many ARM CPU models from numerous semiconductor
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vendors and a wide variety of peripherals. But at the
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ISA level, they share a common compatibility.
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RTEMS depends upon this core similarity across the CPU models
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and leverages that to minimize the source code that is specific
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to any particular CPU core implementation or CPU model.
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This manual is separate and distinct from the RTEMS Porting
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Guide. That manual is a guide on porting RTEMS to a new
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architecture. This manual is focused on the more mundane
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CPU architecture specific issues that may impact
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application development. For example, if you need to write
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a subroutine in assembly language, it is critical to understand
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the calling conventions for the target architecture.
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The first chapter in this manual describes these issues
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in general terms. In a sense, it is posing the questions
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one should be aware may need to be answered and understood
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when porting an RTEMS application to a new architecture.
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Each subsequent chapter gives the answers to those questions
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for a particular CPU architecture.
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