forked from Imagelibrary/rtems
21ff802c7f
Delete _ISR_Enable_on_this_core(), _ISR_Flash_on_this_core(), _ISR_SMP_Disable(), _ISR_SMP_Enable(), _ISR_SMP_Flash(). The ISR disable/enable interface has no parameter to pass a specific object. Thus it is only possible to implement a single global lock object with this interface. Using the ISR disable/enable as the giant lock on SMP configurations is not feasible. Potentially blocking resource obtain sequences protected by the thread dispatch disable level are subdivided into smaller ISR disabled critical sections. This works since on single processor configurations there is only one thread of execution that can block. On SMP this is different (image a mutex obtained concurrently by different threads on different processors). The thread dispatch disable level is currently used as the giant lock. There is not need to complicate things with this unused interface.
133 lines
3.3 KiB
C
133 lines
3.3 KiB
C
/**
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* @file
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*
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* @brief Thread Dispatch Disable Functions
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*
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* @ingroup ScoreThread
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*/
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/*
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* COPYRIGHT (c) 1989-2011.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license/LICENSE.
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*/
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#include <rtems/system.h>
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#include <rtems/score/apiext.h>
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#include <rtems/score/context.h>
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#include <rtems/score/interr.h>
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#include <rtems/score/isr.h>
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#include <rtems/score/priority.h>
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#include <rtems/score/threaddispatch.h>
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#define NO_OWNER_CPU 0xffffffffU
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void _Thread_Dispatch_initialization( void )
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{
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Thread_Dispatch_disable_level_lock_control *level_lock =
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&_Thread_Dispatch_disable_level_lock;
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_Thread_Dispatch_disable_level = 0;
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_SMP_lock_Initialize( &level_lock->lock );
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level_lock->owner_cpu = NO_OWNER_CPU;
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_Thread_Dispatch_set_disable_level( 1 );
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}
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uint32_t _Thread_Dispatch_get_disable_level(void)
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{
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return _Thread_Dispatch_disable_level;
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}
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uint32_t _Thread_Dispatch_increment_disable_level( void )
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{
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Thread_Dispatch_disable_level_lock_control *level_lock =
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&_Thread_Dispatch_disable_level_lock;
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ISR_Level isr_level;
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uint32_t self_cpu;
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uint32_t disable_level;
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_ISR_Disable( isr_level );
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/*
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* We must obtain the processor ID after interrupts are disabled since a
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* non-optimizing compiler may store the value on the stack and read it back.
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*/
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self_cpu = _SMP_Get_current_processor();
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if ( level_lock->owner_cpu != self_cpu ) {
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_SMP_lock_Acquire( &level_lock->lock );
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level_lock->owner_cpu = self_cpu;
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level_lock->nest_level = 1;
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} else {
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++level_lock->nest_level;
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}
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disable_level = _Thread_Dispatch_disable_level;
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++disable_level;
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_Thread_Dispatch_disable_level = disable_level;
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_ISR_Enable( isr_level );
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return disable_level;
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}
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uint32_t _Thread_Dispatch_decrement_disable_level( void )
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{
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Thread_Dispatch_disable_level_lock_control *level_lock =
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&_Thread_Dispatch_disable_level_lock;
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ISR_Level isr_level;
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uint32_t disable_level;
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_ISR_Disable( isr_level );
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disable_level = _Thread_Dispatch_disable_level;
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--disable_level;
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_Thread_Dispatch_disable_level = disable_level;
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--level_lock->nest_level;
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if ( level_lock->nest_level == 0 ) {
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level_lock->owner_cpu = NO_OWNER_CPU;
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_SMP_lock_Release( &level_lock->lock );
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}
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_ISR_Enable( isr_level );
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return disable_level;
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}
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/*
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* Note this method is taking a heavy handed approach to
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* setting the dispatch level. This may be optimized at a
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* later timee, but it must be in such a way that the nesting
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* level is decremented by the same number as the dispatch level.
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* This approach is safest until we are sure the nested spinlock
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* is successfully working with smp isr source code.
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*/
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uint32_t _Thread_Dispatch_set_disable_level(uint32_t value)
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{
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/*
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* If we need the dispatch level to go higher
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* call increment method the desired number of times.
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*/
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while ( value > _Thread_Dispatch_disable_level ) {
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_Thread_Dispatch_increment_disable_level();
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}
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/*
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* If we need the dispatch level to go lower
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* call increment method the desired number of times.
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*/
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while ( value < _Thread_Dispatch_disable_level ) {
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_Thread_Dispatch_decrement_disable_level();
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}
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return value;
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}
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