forked from Imagelibrary/rtems
1eed6f8bfc
Pass the parameter of the clock interrupt handler to Clock_driver_support_at_tick() and Clock_driver_timecounter_tick(). This makes it possible to use the interrupt handler argument in clock drivers. Use the interrupt handler provided by Clock_driver_support_install_isr() to avoid local delarations of Clock_isr(). Update #4862.
125 lines
4.5 KiB
C
125 lines
4.5 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* Instantiate the clock driver shell.
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*/
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/*
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* COPYRIGHT (c) 1989-2012.
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* On-Line Applications Research Corporation (OAR).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <rtems.h>
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#include <bsp/irq.h>
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#include <bsp.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include "yamon_api.h"
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/* #define CLOCK_DRIVER_USE_FAST_IDLE 1 */
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#define CLOCK_VECTOR TX4938_IRQ_TMR0
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#define TX4938_TIMER_INTERVAL_MODE 1
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#define TX4938_TIMER_MODE TX4938_TIMER_INTERVAL_MODE
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#if (TX4938_TIMER_MODE == TX4938_TIMER_INTERVAL_MODE)
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#define TX4938_TIMER_INTERRUPT_FLAG TIIS
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#define Clock_driver_support_initialize_hardware() \
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Initialize_timer0_in_interval_mode()
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#else
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#error "Build Error: unsupported timer mode"
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#endif
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void new_brk_esr(void);
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t_yamon_retfunc esr_retfunc = 0;
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t_yamon_ref original_brk_esr = 0;
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t_yamon_ref original_tmr0_isr = 0;
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void new_brk_esr(void)
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{
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if (original_tmr0_isr)
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{
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YAMON_FUNC_DEREGISTER_IC_ISR( original_tmr0_isr );
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original_tmr0_isr = 0;
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}
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if (esr_retfunc)
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esr_retfunc();
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}
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#define Clock_driver_support_install_isr( _new ) \
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do { \
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rtems_interrupt_handler_install( \
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CLOCK_VECTOR, \
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"clock", \
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0, \
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_new, \
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NULL \
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); \
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YAMON_FUNC_REGISTER_IC_ISR(17,(t_yamon_isr)_new,0,&original_tmr0_isr); /* Call Yamon to enable interrupt */ \
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} while(0)
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#define Clock_driver_support_at_tick(arg) \
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do { \
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uint32_t interrupt_flag; \
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do { \
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int loop_count; \
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TX4938_REG_WRITE( TX4938_REG_BASE, TX4938_TIMER0_BASE + TX4938_TIMER_TISR, 0x0 ); /* Clear timer 0 interrupt */ \
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loop_count = 0; \
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do { /* Wait until interrupt flag is cleared (this prevents re-entering interrupt) */ \
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/* Read back interrupt status register and isolate interval timer flag */ \
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interrupt_flag = TX4938_REG_READ( TX4938_REG_BASE, TX4938_TIMER0_BASE + TX4938_TIMER_TISR ) & TX4938_TIMER_INTERRUPT_FLAG; \
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} while (interrupt_flag && (++loop_count < 10)); /* Loop while timer interrupt bit is set, or loop count is lees than 10 */ \
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} while(interrupt_flag); \
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} while(0)
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/* Setup timer in interval mode to generate peiodic interrupts */
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#define Initialize_timer0_in_interval_mode() \
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do { \
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uint32_t temp; \
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TX4938_REG_WRITE( TX4938_REG_BASE, TX4938_TIMER0_BASE + TX4938_TIMER_TCR, 0x0 ); /* Disable timer */ \
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TX4938_REG_WRITE( TX4938_REG_BASE, TX4938_TIMER0_BASE + TX4938_TIMER_CCDR, 0x0 ); /* Set register for divide by 2 clock */ \
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TX4938_REG_WRITE( TX4938_REG_BASE, TX4938_TIMER0_BASE + TX4938_TIMER_ITMR, TIMER_CLEAR_ENABLE_MASK ); /* Set interval timer mode register */ \
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TX4938_REG_WRITE( TX4938_REG_BASE, TX4938_TIMER0_BASE + TX4938_TIMER_CPRA, 0x3d090 ); /* Set tmier period ,10.0 msec (25 MHz timer clock) */ \
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TX4938_REG_WRITE( TX4938_REG_BASE, TX4938_TIMER0_BASE + TX4938_TIMER_TCR, 0xC0 ); /* Enable timer in interval mode */ \
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temp = TX4938_REG_READ( TX4938_REG_BASE, TX4938_TIMER0_BASE + TX4938_TIMER_ITMR ); /* Enable interval timer interrupts */ \
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temp |= TIMER_INT_ENABLE_MASK; \
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TX4938_REG_WRITE( TX4938_REG_BASE, TX4938_TIMER0_BASE + TX4938_TIMER_ITMR, temp ); \
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} while(0)
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#define CLOCK_DRIVER_USE_DUMMY_TIMECOUNTER
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#include "../../../shared/dev/clock/clockimpl.h"
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