forked from Imagelibrary/rtems
1e6380baf2
This fixes the corruption of r3 by the call to bsp_start_arm_drop_hyp_mode(). Moving the code makes it easier to review changes in start.S. Close #3773.
488 lines
10 KiB
ArmAsm
488 lines
10 KiB
ArmAsm
/**
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* @file
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*
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* @brief Boot and system start code.
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*/
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/*
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* Copyright (c) 2008, 2018 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Dornierstr. 4
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* 82178 Puchheim
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* Germany
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* <rtems@embedded-brains.de>
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*
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* Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz>
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*
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* Czech Technical University in Prague
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* Zikova 1903/4
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* 166 36 Praha 6
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* Czech Republic
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <rtems/asm.h>
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#include <rtems/score/percpu.h>
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#include <bspopts.h>
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#include <bsp/irq.h>
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/* Global symbols */
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.globl _start
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.globl bsp_start_vector_table_begin
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.globl bsp_start_vector_table_end
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.globl bsp_start_vector_table_size
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.globl bsp_vector_table_size
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.section ".bsp_start_text", "ax"
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#if defined(ARM_MULTILIB_ARCH_V4)
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#ifdef BSP_START_IN_HYP_SUPPORT
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.globl bsp_start_hyp_vector_table_begin
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#endif
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.arm
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/*
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* This is the exception vector table and the pointers to the default
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* exceptions handlers.
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*/
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bsp_start_vector_table_begin:
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ldr pc, .Lhandler_addr_reset
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ldr pc, .Lhandler_addr_undef
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ldr pc, .Lhandler_addr_swi
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ldr pc, .Lhandler_addr_prefetch
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ldr pc, .Lhandler_addr_abort
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/* Program signature checked by boot loader */
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.word 0xb8a06f58
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ldr pc, .Lhandler_addr_irq
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ldr pc, .Lhandler_addr_fiq
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.Lhandler_addr_reset:
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#ifdef BSP_START_RESET_VECTOR
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.word BSP_START_RESET_VECTOR
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#else
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.word _start
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#endif
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.Lhandler_addr_undef:
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.word _ARMV4_Exception_undef_default
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.Lhandler_addr_swi:
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.word _ARMV4_Exception_swi_default
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.Lhandler_addr_prefetch:
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.word _ARMV4_Exception_pref_abort_default
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.Lhandler_addr_abort:
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.word _ARMV4_Exception_data_abort_default
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.Lhandler_addr_reserved:
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.word _ARMV4_Exception_reserved_default
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.Lhandler_addr_irq:
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.word _ARMV4_Exception_interrupt
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.Lhandler_addr_fiq:
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.word _ARMV4_Exception_fiq_default
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bsp_start_vector_table_end:
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#ifdef BSP_START_IN_HYP_SUPPORT
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bsp_start_hyp_vector_table_begin:
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ldr pc, .Lhandler_addr_hyp_reset
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ldr pc, .Lhandler_addr_hyp_undef
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ldr pc, .Lhandler_addr_hyp_swi
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ldr pc, .Lhandler_addr_hyp_prefetch
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ldr pc, .Lhandler_addr_hyp_abort
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ldr pc, .Lhandler_addr_hyp_hyp
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ldr pc, .Lhandler_addr_hyp_irq
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ldr pc, .Lhandler_addr_hyp_fiq
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.Lhandler_addr_hyp_reset:
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.word _ARMV4_Exception_reserved_default
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.Lhandler_addr_hyp_undef:
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.word _ARMV4_Exception_reserved_default
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.Lhandler_addr_hyp_swi:
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.word _ARMV4_Exception_reserved_default
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.Lhandler_addr_hyp_prefetch:
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.word _ARMV4_Exception_reserved_default
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.Lhandler_addr_hyp_abort:
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.word _ARMV4_Exception_reserved_default
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.Lhandler_addr_hyp_hyp:
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.word _ARMV4_Exception_reserved_default
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.Lhandler_addr_hyp_irq:
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.word _ARMV4_Exception_reserved_default
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.Lhandler_addr_hyp_fiq:
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.word _ARMV4_Exception_reserved_default
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#endif
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/* Start entry */
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_start:
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/*
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* We do not save the context since we do not return to the boot
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* loader but preserve r1 and r2 to allow access to bootloader parameters
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*/
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#ifndef BSP_START_NEEDS_REGISTER_INITIALIZATION
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mov r5, r1 /* machine type number or ~0 for DT boot */
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mov r6, r2 /* physical address of ATAGs or DTB */
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#else /* BSP_START_NEEDS_REGISTER_INITIALIZATION */
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mov r0, #0
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mov r1, #0
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mov r2, #0
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mov r3, #0
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mov r4, #0
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mov r5, #0
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mov r6, #0
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mov r7, #0
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mov r8, #0
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mov r9, #0
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mov r10, #0
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mov r11, #0
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mov r12, #0
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mov r13, #0
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#endif
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#ifdef RTEMS_SMP
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/* Read MPIDR and get current processor index */
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mrc p15, 0, r7, c0, c0, 5
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and r7, #0xff
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#endif
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#ifdef RTEMS_SMP
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/*
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* Get current per-CPU control and store it in PL1 only Thread ID
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* Register (TPIDRPRW).
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*/
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ldr r1, =_Per_CPU_Information
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add r1, r1, r7, asl #PER_CPU_CONTROL_SIZE_LOG2
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mcr p15, 0, r1, c13, c0, 4
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#endif
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/* Calculate interrupt stack area end for current processor */
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ldr r1, =_ISR_Stack_size
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#ifdef RTEMS_SMP
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add r3, r7, #1
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mul r1, r1, r3
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#endif
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ldr r2, =_ISR_Stack_area_begin
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add r3, r1, r2
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/* Save original CPSR value */
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mrs r4, cpsr
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#ifdef BSP_START_IN_HYP_SUPPORT
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orr r0, r4, #(ARM_PSR_I | ARM_PSR_F)
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msr cpsr, r4
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and r0, r4, #ARM_PSR_M_MASK
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cmp r0, #ARM_PSR_M_HYP
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bne .L_skip_hyp_svc_switch
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/* Boot loader starts kernel in HYP mode, switch to SVC necessary */
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ldr r1, =bsp_stack_hyp_size
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mov sp, r3
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sub r3, r3, r1
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ldr r2, =bsp_start_hyp_vector_table_begin
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mcr p15, 4, r2, c12, c0, 0
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mov r2, #0
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mcr p15, 4, r2, c1, c1, 0
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mcr p15, 4, r2, c1, c1, 2
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mcr p15, 4, r2, c1, c1, 3
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/*
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* HSCTLR.TE
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* optional start of hypervisor handlers in Thumb mode
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* orr r0, #(1 << 30)
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*/
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mcr p15, 4, r2, c1, c0, 0 /* HSCTLR */
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mrc p15, 4, r2, c1, c1, 1 /* HDCR */
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and r2, #0x1f /* Preserve HPMN */
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mcr p15, 4, r2, c1, c1, 1 /* HDCR */
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/* Prepare SVC mode for eret */
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mrs r2, cpsr
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bic r2, r2, #ARM_PSR_M_MASK
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orr r2, r2, #ARM_PSR_M_SVC
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msr spsr_cxsf, r2
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adr r2, .L_hyp_to_svc_return
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.inst 0xe12ef302 /* msr ELR_hyp, r2 */
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mov r2, sp
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.inst 0xe160006e /* eret */
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.L_hyp_to_svc_return:
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mov sp, r2
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.L_skip_hyp_svc_switch:
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#endif /* BSP_START_IN_HYP_SUPPORT */
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/* Initialize stack pointer registers for the various modes */
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/* Enter FIQ mode and set up the FIQ stack pointer */
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mov r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
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msr cpsr, r0
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ldr r1, =bsp_stack_fiq_size
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mov sp, r3
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sub r3, r3, r1
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#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
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mov r8, #0
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mov r9, #0
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mov r10, #0
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mov r11, #0
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mov r12, #0
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#endif
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/* Enter ABT mode and set up the ABT stack pointer */
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mov r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
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msr cpsr, r0
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ldr r1, =bsp_stack_abt_size
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mov sp, r3
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sub r3, r3, r1
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/* Enter UND mode and set up the UND stack pointer */
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mov r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
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msr cpsr, r0
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ldr r1, =bsp_stack_und_size
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mov sp, r3
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sub r3, r3, r1
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/* Enter IRQ mode and set up the IRQ stack pointer */
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mov r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
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msr cpsr, r0
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mov sp, r3
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/*
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* Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
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* (interrupts are disabled).
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*/
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mov r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
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msr cpsr, r0
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mov sp, r3
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/* Stay in SVC mode */
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/* Copy device tree from boot loader */
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#ifdef BSP_START_COPY_FDT_FROM_U_BOOT
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#ifdef RTEMS_SMP
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cmp r7, #0
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bne 1f
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#endif
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mov r0, r6
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bl bsp_fdt_copy
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1:
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#endif
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#ifdef ARM_MULTILIB_VFP
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#ifdef ARM_MULTILIB_HAS_CPACR
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/* Read CPACR */
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mrc p15, 0, r0, c1, c0, 2
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/* Enable CP10 and CP11 */
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orr r0, r0, #(1 << 20)
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orr r0, r0, #(1 << 22)
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/*
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* Clear ASEDIS and D32DIS. Writes to D32DIS are ignored for VFP-D16.
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*/
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bic r0, r0, #(3 << 30)
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/* Write CPACR */
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mcr p15, 0, r0, c1, c0, 2
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isb
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#endif
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/* Enable FPU */
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mov r0, #(1 << 30)
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vmsr FPEXC, r0
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#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
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mov r0, #0
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vmov d0, r0, r0
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vmov d1, r0, r0
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vmov d2, r0, r0
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vmov d3, r0, r0
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vmov d4, r0, r0
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vmov d5, r0, r0
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vmov d6, r0, r0
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vmov d7, r0, r0
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vmov d8, r0, r0
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vmov d9, r0, r0
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vmov d10, r0, r0
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vmov d11, r0, r0
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vmov d12, r0, r0
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vmov d13, r0, r0
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vmov d14, r0, r0
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vmov d15, r0, r0
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#ifdef ARM_MULTILIB_VFP_D32
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vmov d16, r0, r0
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vmov d17, r0, r0
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vmov d18, r0, r0
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vmov d19, r0, r0
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vmov d20, r0, r0
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vmov d21, r0, r0
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vmov d22, r0, r0
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vmov d23, r0, r0
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vmov d24, r0, r0
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vmov d25, r0, r0
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vmov d26, r0, r0
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vmov d27, r0, r0
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vmov d28, r0, r0
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vmov d29, r0, r0
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vmov d30, r0, r0
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vmov d31, r0, r0
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#endif /* ARM_MULTILIB_VFP_D32 */
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#endif /* BSP_START_NEEDS_REGISTER_INITIALIZATION */
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#endif /* ARM_MULTILIB_VFP */
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/*
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* Invoke the start hook 0.
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*
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* The previous code and parts of the start hook 0 may run with an
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* address offset. After the return from start hook 0 it is assumed
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* that the code can run at its intended position. Thus the link
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* register will be loaded with the absolute address and the branch
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* link instruction cannot be used. In THUMB mode the branch
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* instruction as a very limited address range of 2KiB. Use a bx to
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* the start hook 0 address instead corrected by the address offset.
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*/
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ldr lr, =.Lstart_hook_0_done
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mov r0, pc
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ldr r1, =.Lget_absolute_pc
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.Lget_absolute_pc:
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sub r1, r0
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ldr r7, =bsp_start_hook_0
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add r7, r1
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mov r0, r4 /* original CPSR value */
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mov r1, r5 /* machine type number or ~0 for DT boot */
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mov r2, r6 /* physical address of ATAGs or DTB */
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bx r7
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.Lstart_hook_0_done:
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/*
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* Initialize the exception vectors. This includes the exceptions
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* vectors and the pointers to the default exception handlers.
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*/
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stmdb sp!, {r4, r5, r6}
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ldr r0, =bsp_vector_table_begin
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adr r1, bsp_start_vector_table_begin
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cmp r0, r1
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beq .Lvector_table_copy_done
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ldmia r1!, {r2-r9}
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stmia r0!, {r2-r9}
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ldmia r1!, {r2-r9}
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stmia r0!, {r2-r9}
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.Lvector_table_copy_done:
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ldmia sp!, {r0, r1, r2}
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SWITCH_FROM_ARM_TO_THUMB r3
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/* Branch to start hook 1 */
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bl bsp_start_hook_1
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/* Branch to boot card */
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mov r0, #0
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bl boot_card
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#elif defined(ARM_MULTILIB_ARCH_V7M)
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#include <rtems/score/armv7m.h>
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.syntax unified
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.thumb
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bsp_start_vector_table_begin:
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.word _ISR_Stack_area_end
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.word _start /* Reset */
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.word _ARMV7M_Exception_default /* NMI */
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.word _ARMV7M_Exception_default /* Hard Fault */
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.word _ARMV7M_Exception_default /* MPU Fault */
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.word _ARMV7M_Exception_default /* Bus Fault */
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.word _ARMV7M_Exception_default /* Usage Fault */
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.word _ARMV7M_Exception_default /* Reserved */
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.word _ARMV7M_Exception_default /* Reserved */
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.word _ARMV7M_Exception_default /* Reserved */
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.word _ARMV7M_Exception_default /* Reserved */
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.word _ARMV7M_Exception_default /* SVC */
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.word _ARMV7M_Exception_default /* Debug Monitor */
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.word _ARMV7M_Exception_default /* Reserved */
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.word _ARMV7M_Exception_default /* PendSV */
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.word _ARMV7M_Exception_default /* SysTick */
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.rept BSP_INTERRUPT_VECTOR_MAX + 1
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.word _ARMV7M_Exception_default /* IRQ */
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.endr
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bsp_start_vector_table_end:
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.thumb_func
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_start:
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#if defined(ARM_MULTILIB_VFP) && defined(ARM_MULTILIB_HAS_CPACR)
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/*
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* Enable CP10 and CP11 coprocessors for privileged and user mode in
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* CPACR (bits 20-23). Ensure that write to register completes.
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*/
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ldr r0, =ARMV7M_CPACR
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ldr r1, [r0]
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orr r1, r1, #(0xf << 20)
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str r1, [r0]
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dsb
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isb
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#endif
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ldr sp, =_ISR_Stack_area_end
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ldr lr, =.Lstart_hook_0_done + 1
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b bsp_start_hook_0
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.Lstart_hook_0_done:
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bl bsp_start_hook_1
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movs r0, #0
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bl boot_card
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#endif /* defined(ARM_MULTILIB_ARCH_V7M) */
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.set bsp_start_vector_table_size, bsp_start_vector_table_end - bsp_start_vector_table_begin
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.set bsp_vector_table_size, bsp_start_vector_table_size
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