forked from Imagelibrary/rtems
2afb22b7e1
A speciality of the RTEMS build system was the make preinstall step. It copied header files from arbitrary locations into the build tree. The header files were included via the -Bsome/build/tree/path GCC command line option. This has at least seven problems: * The make preinstall step itself needs time and disk space. * Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error. * There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult. * The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit. * An introduction of a new build system is difficult. * Include paths specified by the -B option are system headers. This may suppress warnings. * The parallel build had sporadic failures on some hosts. This patch removes the make preinstall step. All installed header files are moved to dedicated include directories in the source tree. Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc, etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g. erc32, imx, qoriq, etc. The new cpukit include directories are: * cpukit/include * cpukit/score/cpu/@RTEMS_CPU@/include * cpukit/libnetworking The new BSP include directories are: * bsps/include * bsps/@RTEMS_CPU@/include * bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include There are build tree include directories for generated files. The include directory order favours the most general header file, e.g. it is not possible to override general header files via the include path order. The "bootstrap -p" option was removed. The new "bootstrap -H" option should be used to regenerate the "headers.am" files. Update #3254.
128 lines
4.8 KiB
C
128 lines
4.8 KiB
C
/*
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* GRPWM PWM Driver interface.
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*
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* COPYRIGHT (c) 2009.
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* Cobham Gaisler AB.
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#ifndef __GRPWM_H__
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#define __GRPWM_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern void grpwm_register_drv (void);
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#define GRPWM_IOCTL_GET_CAP 1 /* Get Capabilities */
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#define GRPWM_IOCTL_SET_CONFIG 2 /* Configure one PWM Channel */
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#define GRPWM_IOCTL_SET_SCALER 3 /* Set one scaler */
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#define GRPWM_IOCTL_UPDATE 4 /* Set current period and compare value */
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#define GRPWM_IOCTL_IRQ 5 /* Set up IRQ handling */
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/*** Argument for GRPWM_IOCTL_GET_CAP ***/
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/* The Capability of the PWM core */
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struct grpwm_ioctl_cap {
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int channel_cnt; /* Number of channels */
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unsigned int pwm; /* Capability1 register */
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unsigned int wave; /* Capability2 register, Wave form capabilities of last PWM channel, otherwise 0 */
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};
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/*** Argument for GRPWM_IOCTL_GET_CONFIG and GRPWM_IOCTL_SET_CONFIG ***/
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/* Config One PWM */
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struct grpwm_ioctl_config {
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unsigned int channel; /* Select channel to configure */
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/* Specific for one PWM channel */
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unsigned int options; /* PWM options */
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unsigned char dbscaler; /* value greater than 15 disable Dead band */
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unsigned char scaler_index; /* Select scaler used by PWM channel */
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/* IRQ Setup */
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unsigned char irqscaler; /* IRQ scaler */
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void *isr_arg; /* Argument of IRQ handler */
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void (*isr)(int channel, void *arg); /* Interrupt service routine for this PWM Channel */
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/* Waveform set up */
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int wave_activate; /* Enables Waveform functionality */
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unsigned int wave_synccfg; /* Bits [29,30,31] is written into Wave-Config register */
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unsigned int wave_sync; /* Sets sync compare register */
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unsigned int *wave_data; /* If not NULL, the Wave RAM is filled with data */
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unsigned int wave_data_length; /* Length of Wave RAM Data, Also used for wstopaddr */
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};
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#define GRPWM_CONFIG_OPTION_FLIP 0x04000000 /* Set this to Flip PWM output pair */
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#define GRPWM_CONFIG_OPTION_DEAD_BAND 0x00200000 /* Dead Band enable */
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#define GRPWM_CONFIG_OPTION_SYMMETRIC 0x00000040 /* If not defined, asymmetric */
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#define GRPWM_CONFIG_OPTION_ASYMMERTIC 0
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#define GRPWM_CONFIG_OPTION_DUAL 0x00000020 /* Dual Compare Enable */
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#define GRPWM_CONFIG_OPTION_PAIR 0x00000004 /* PWM Pair Enable */
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#define GRPWM_CONFIG_OPTION_SINGLE 0x00000000 /* PWM Pair Disable */
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#define GRPWM_CONFIG_OPTION_POLARITY_HIGH 0x00000002 /* PWM Polarity HIGH */
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#define GRPWM_CONFIG_OPTION_POLARITY_LOW 0x00000000 /* PWM Polarity LOW */
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#define GRPWM_CONFIG_OPTION_MASK ( \
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GRPWM_CONFIG_OPTION_DEAD_BAND | GRPWM_CONFIG_OPTION_SYMMETRIC | \
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GRPWM_CONFIG_OPTION_DUAL | GRPWM_CONFIG_OPTION_PAIR | \
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GRPWM_CONFIG_OPTION_POLARITY_HIGH \
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)
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/*** Argument for GPPWM_IOCTL_SET_SCALER ***/
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struct grpwm_ioctl_scaler {
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unsigned int index_mask;/* Scaler update index mask, bit 0 = Scaler 0, bit 1 = Scaler 1 */
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unsigned int values[8]; /* Scaler update values, values[N] is stored into scaler N, if mask & 1<<N is set */
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};
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/*** Argument for GRPWM_IOCTL_UPDATE ***/
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#define GRPWM_UPDATE_OPTION_ENABLE 0x01 /* Enable the PWM core */
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#define GRPWM_UPDATE_OPTION_DISABLE 0x02 /* Disable the PWM core */
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#define GRPWM_UPDATE_OPTION_PERIOD 0x04 /* Update period register */
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#define GRPWM_UPDATE_OPTION_COMP 0x08 /* Update Compare register */
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#define GRPWM_UPDATE_OPTION_DBCOMP 0x10 /* Update Dead band register */
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#define GRPWM_UPDATE_OPTION_FIX 0x20 /* Update fix output pins (bypass PWM) */
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/* FIX PIN bit-mask */
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#define GRPWM_UPDATE_FIX_ENABLE 1 /* Enable force ouput */
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#define GRPWM_UPDATE_FIX_DISABLE 0 /* Disable force ouput */
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#define GRPWM_UPDATE_FIX_0_LOW 0 /* PIN 0 OUPUT: LOW */
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#define GRPWM_UPDATE_FIX_0_HIGH 2 /* PIN 0 OUPUT: HIGH */
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#define GRPWM_UPDATE_FIX_1_LOW 0 /* PIN 1 OUPUT: LOW */
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#define GRPWM_UPDATE_FIX_1_HIGH 4 /* PIN 1 OUPUT: HIGH */
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struct grpwm_ioctl_update_chan {
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unsigned int options; /* Select what is updated */
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unsigned int period; /* Period register content */
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unsigned int compare; /* Compare register content */
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unsigned int dbcomp; /* Dead band register content */
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unsigned char fix; /* Bit-mask that select output on one or two PWM
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* output pins. Depends on PAIR config value.
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*/
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};
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struct grpwm_ioctl_update {
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unsigned char chanmask; /* Bit Mask select channels */
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struct grpwm_ioctl_update_chan channels[8]; /* */
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};
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/*** Argument for GPPWM_IOCTL_IRQ ***/
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#define GRPWM_IRQ_DISABLE 0 /* Disable IRQ */
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#define GRPWM_IRQ_PERIOD 1 /* Enable IRQ on period match */
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#define GRPWM_IRQ_COMPARE 3 /* Enable IRQ on Compare Match */
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#define GRPWM_IRQ_CLEAR 0x10 /* Clear any pending IRQ on GRPWM and IRQ controller */
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#define GRPWM_IRQ_CHAN 0x100 /* Channel N is selected, by adding 0x100*N */
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#ifdef __cplusplus
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}
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#endif
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#endif
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