forked from Imagelibrary/rtems
511dc4b2be
Statically initialize the interrupt stack area
(_Configuration_Interrupt_stack_area_begin,
_Configuration_Interrupt_stack_area_end, and
_Configuration_Interrupt_stack_size) via <rtems/confdefs.h>. Place the
interrupt stack area in a special section ".rtemsstack.interrupt". Let
BSPs define the optimal placement of this section in their linker
command files (e.g. in a fast on-chip memory).
This change makes makes the CPU_HAS_SOFTWARE_INTERRUPT_STACK and
CPU_HAS_HARDWARE_INTERRUPT_STACK CPU port defines superfluous, since the
low level initialization code has all information available via global
symbols.
This change makes the CPU_ALLOCATE_INTERRUPT_STACK CPU port define
superfluous, since the interrupt stacks are allocated by confdefs.h for
all architectures. There is no need for BSP-specific linker command
file magic (except the section placement), see previous ARM linker
command file as a bad example.
Remove _CPU_Install_interrupt_stack(). Initialize the hardware
interrupt stack in _CPU_Initialize() if necessary (e.g.
m68k_install_interrupt_stack()).
The optional _CPU_Interrupt_stack_setup() is still useful to customize
the registration of the interrupt stack area in the per-CPU information.
The initialization stack can reuse the interrupt stack, since
* interrupts are disabled during the sequential system initialization,
and
* the boot_card() function does not return.
This stack resuse saves memory.
Changes per architecture:
arm:
* Mostly replace the linker symbol based configuration of stacks with
the standard <rtems/confdefs.h> configuration via
CONFIGURE_INTERRUPT_STACK_SIZE. The size of the FIQ, ABT and UND
mode stack is still defined via linker symbols. These modes are
rarely used in applications and the default values provided by the
BSP should be sufficient in most cases.
* Remove the bsp_processor_count linker symbol hack used for the SMP
support. This is possible since the interrupt stack area is now
allocated by the linker and not allocated from the heap. This makes
some configure.ac stuff obsolete. Remove the now superfluous BSP
variants altcycv_devkit_smp and realview_pbx_a9_qemu_smp.
bfin:
* Remove unused magic linker command file allocation of initialization
stack. Maybe a previous linker command file copy and paste problem?
In the start.S the initialization stack is set to a hard coded value.
lm32, m32c, mips, nios2, riscv, sh, v850:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
m68k:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
powerpc:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
* Used dedicated memory region (REGION_RTEMSSTACK) for the interrupt
stack on BSPs using the shared linkcmds.base (replacement for
REGION_RWEXTRA).
sparc:
* Remove the hard coded initialization stack. Use the interrupt stack
for the initialization stack on the boot processor. This saves
16KiB of RAM.
Update #3459.
# Adapted from virtex BSP
BSP NAME: virtex5
BOARD: N/A
BUS: N/A
CPU FAMILY: ppc
CPU: PowerPC 440x5
COPROCESSORS: N/A
MODE: 32 bit mode
DEBUG MONITOR:
PERIPHERALS
===========
TIMERS: 440 internal
SERIAL PORTS: none
REAL-TIME CLOCK: none
DMA: Xilinx virtex internal
VIDEO: none
SCSI: none
NETWORKING: none
DRIVER INFORMATION
==================
CLOCK DRIVER: PPC Decrementer
IOSUPP DRIVER: N/A
SHMSUPP: N/A
TIMER DRIVER: N/A
TTY DRIVER: N/A
STDIO
=====
PORT: N/A
ELECTRICAL: N/A
BAUD: N/A
BITS PER CHARACTER: N/A
PARITY: N/A
STOP BITS: N/A
Notes
=====
Board description
-----------------
clock rate: 465 MHz
ROM: N/A
RAM: 4GByte DRAM
Virtex only supports single processor operations.
Porting
-------
This board support package is written for a naked Virtex 5/PPC FPGA
system. The rough features of such a board are described above.
The BSP itself makes no assumptions on what is loaded in the FPGA,
other than that the CPU has access to some memory, either on-board
or external, from which code can be run.
This BSP has been constructed so that an application of both firmware
and software can be layered on top of it by supplying implementations
for the various 'weak' symbols. These symbols are prefaced with the
term 'app_'. Applications can thus be built outside of the RTEMS
directory tree by linking with the appropriate libraries.
The linkcmds file describes the memory layout. Included in this
definition is a section of memory named MsgArea. Output sent to
stdout is recorded in this area and can be dumped using the JTAG
interface, for example.
For adapting this BSP to other boards, the following files should be
modified:
- c/src/lib/libbsp/powerpc/virtex5/startup/linkcmds
for the memory layout required
- c/src/lib/libbsp/powerpc/virtex5/startup/bspstart.c
Here you can select the clock source for the timers and the
serial interface (system clock or external clock pin), the
clock rates, etc.
- c/src/lib/libbsp/powerpc/virtex5/include/bsp.h
some BSP-related constants
- c/src/lib/libbsp/powerpc/virtex5/*
well, they should be generic, so there _should_ be no reason
to mess around there (but who knows...)