forked from Imagelibrary/rtems
230 lines
7.4 KiB
ArmAsm
230 lines
7.4 KiB
ArmAsm
/*
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* Copyright (c) 2011, 2017 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Dornierstr. 4
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* 82178 Puchheim
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* Germany
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* <rtems@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <bspopts.h>
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#include <rtems/score/percpu.h>
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#include <bsp/vectors.h>
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#define SCRATCH_REGISTER_0 r3
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#define SCRATCH_REGISTER_1 r4
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.global ppc_exc_fatal_normal
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.global ppc_exc_fatal_critical
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.global ppc_exc_fatal_machine_check
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.global ppc_exc_fatal_debug
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ppc_exc_fatal_critical:
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PPC_REG_STORE SCRATCH_REGISTER_1, GPR4_OFFSET(r1)
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mfcsrr0 SCRATCH_REGISTER_1
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PPC_REG_STORE SCRATCH_REGISTER_1, SRR0_FRAME_OFFSET(r1)
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mfcsrr1 SCRATCH_REGISTER_1
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PPC_REG_STORE SCRATCH_REGISTER_1, SRR1_FRAME_OFFSET(r1)
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b .Lppc_exc_fatal
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ppc_exc_fatal_machine_check:
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PPC_REG_STORE SCRATCH_REGISTER_1, GPR4_OFFSET(r1)
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mfmcsrr0 SCRATCH_REGISTER_1
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PPC_REG_STORE SCRATCH_REGISTER_1, SRR0_FRAME_OFFSET(r1)
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mfmcsrr1 SCRATCH_REGISTER_1
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PPC_REG_STORE SCRATCH_REGISTER_1, SRR1_FRAME_OFFSET(r1)
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b .Lppc_exc_fatal
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ppc_exc_fatal_debug:
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PPC_REG_STORE SCRATCH_REGISTER_1, GPR4_OFFSET(r1)
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mfspr SCRATCH_REGISTER_1, BOOKE_DSRR0
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PPC_REG_STORE SCRATCH_REGISTER_1, SRR0_FRAME_OFFSET(r1)
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mfspr SCRATCH_REGISTER_1, BOOKE_DSRR1
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PPC_REG_STORE SCRATCH_REGISTER_1, SRR1_FRAME_OFFSET(r1)
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b .Lppc_exc_fatal
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ppc_exc_fatal_normal:
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PPC_REG_STORE SCRATCH_REGISTER_1, GPR4_OFFSET(r1)
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mfsrr0 SCRATCH_REGISTER_1
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PPC_REG_STORE SCRATCH_REGISTER_1, SRR0_FRAME_OFFSET(r1)
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mfsrr1 SCRATCH_REGISTER_1
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PPC_REG_STORE SCRATCH_REGISTER_1, SRR1_FRAME_OFFSET(r1)
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.Lppc_exc_fatal:
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stw r3, EXCEPTION_NUMBER_OFFSET(r1)
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mfcr SCRATCH_REGISTER_1
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stw SCRATCH_REGISTER_1, EXC_CR_OFFSET(r1)
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mfxer SCRATCH_REGISTER_1
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stw SCRATCH_REGISTER_1, EXC_XER_OFFSET(r1)
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mfctr SCRATCH_REGISTER_1
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PPC_REG_STORE SCRATCH_REGISTER_1, EXC_CTR_OFFSET(r1)
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mflr SCRATCH_REGISTER_1
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PPC_REG_STORE SCRATCH_REGISTER_1, EXC_LR_OFFSET(r1)
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PPC_REG_STORE r0, GPR0_OFFSET(r1)
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PPC_REG_STORE r1, GPR1_OFFSET(r1)
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PPC_REG_STORE r2, GPR2_OFFSET(r1)
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PPC_REG_STORE r5, GPR5_OFFSET(r1)
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PPC_REG_STORE r6, GPR6_OFFSET(r1)
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PPC_REG_STORE r7, GPR7_OFFSET(r1)
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PPC_REG_STORE r8, GPR8_OFFSET(r1)
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PPC_REG_STORE r9, GPR9_OFFSET(r1)
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PPC_REG_STORE r10, GPR10_OFFSET(r1)
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PPC_REG_STORE r11, GPR11_OFFSET(r1)
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PPC_REG_STORE r12, GPR12_OFFSET(r1)
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PPC_REG_STORE r13, GPR13_OFFSET(r1)
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PPC_REG_STORE r14, GPR14_OFFSET(r1)
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PPC_REG_STORE r15, GPR15_OFFSET(r1)
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PPC_REG_STORE r16, GPR16_OFFSET(r1)
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PPC_REG_STORE r17, GPR17_OFFSET(r1)
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PPC_REG_STORE r18, GPR18_OFFSET(r1)
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PPC_REG_STORE r19, GPR19_OFFSET(r1)
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PPC_REG_STORE r20, GPR20_OFFSET(r1)
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PPC_REG_STORE r21, GPR21_OFFSET(r1)
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PPC_REG_STORE r22, GPR22_OFFSET(r1)
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PPC_REG_STORE r23, GPR23_OFFSET(r1)
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PPC_REG_STORE r24, GPR24_OFFSET(r1)
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PPC_REG_STORE r25, GPR25_OFFSET(r1)
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PPC_REG_STORE r26, GPR26_OFFSET(r1)
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PPC_REG_STORE r27, GPR27_OFFSET(r1)
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PPC_REG_STORE r28, GPR28_OFFSET(r1)
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PPC_REG_STORE r29, GPR29_OFFSET(r1)
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PPC_REG_STORE r30, GPR30_OFFSET(r1)
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PPC_REG_STORE r31, GPR31_OFFSET(r1)
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/* Enable FPU and/or AltiVec */
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#if defined(PPC_MULTILIB_FPU) || defined(PPC_MULTILIB_ALTIVEC)
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mfmsr SCRATCH_REGISTER_1
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#ifdef PPC_MULTILIB_FPU
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ori SCRATCH_REGISTER_1, SCRATCH_REGISTER_1, MSR_FP
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#endif
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#ifdef PPC_MULTILIB_ALTIVEC
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oris SCRATCH_REGISTER_1, SCRATCH_REGISTER_1, MSR_VE >> 16
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#endif
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mtmsr SCRATCH_REGISTER_1
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isync
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#endif
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#ifdef PPC_MULTILIB_ALTIVEC
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li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(0)
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stvx v0, r1, SCRATCH_REGISTER_1
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mfvscr v0
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li SCRATCH_REGISTER_1, PPC_EXC_VSCR_OFFSET
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stvewx v0, r1, SCRATCH_REGISTER_1
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li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(1)
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stvx v1, r1, SCRATCH_REGISTER_1
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li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(2)
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stvx v2, r1, SCRATCH_REGISTER_1
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li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(3)
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stvx v3, r1, SCRATCH_REGISTER_1
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li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(4)
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stvx v4, r1, SCRATCH_REGISTER_1
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li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(5)
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stvx v5, r1, SCRATCH_REGISTER_1
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li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(6)
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stvx v6, r1, SCRATCH_REGISTER_1
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li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(7)
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stvx v7, r1, SCRATCH_REGISTER_1
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li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(8)
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stvx v8, r1, SCRATCH_REGISTER_1
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li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(9)
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stvx v9, r1, SCRATCH_REGISTER_1
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li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(10)
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stvx v10, r1, SCRATCH_REGISTER_1
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li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(11)
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stvx v11, r1, SCRATCH_REGISTER_1
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li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(12)
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stvx v12, r1, SCRATCH_REGISTER_1
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li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(13)
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stvx v13, r1, SCRATCH_REGISTER_1
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li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(14)
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stvx v14, r1, SCRATCH_REGISTER_1
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li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(15)
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stvx v15, r1, SCRATCH_REGISTER_1
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li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(16)
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stvx v16, r1, SCRATCH_REGISTER_1
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li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(17)
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stvx v17, r1, SCRATCH_REGISTER_1
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li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(18)
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stvx v18, r1, SCRATCH_REGISTER_1
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li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(19)
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stvx v19, r1, SCRATCH_REGISTER_1
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li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(20)
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stvx v20, r1, SCRATCH_REGISTER_1
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li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(21)
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stvx v21, r1, SCRATCH_REGISTER_1
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li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(22)
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stvx v22, r1, SCRATCH_REGISTER_1
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li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(23)
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stvx v23, r1, SCRATCH_REGISTER_1
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li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(24)
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stvx v24, r1, SCRATCH_REGISTER_1
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li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(25)
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stvx v25, r1, SCRATCH_REGISTER_1
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li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(26)
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stvx v26, r1, SCRATCH_REGISTER_1
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li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(27)
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stvx v27, r1, SCRATCH_REGISTER_1
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li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(28)
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stvx v28, r1, SCRATCH_REGISTER_1
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li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(29)
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stvx v29, r1, SCRATCH_REGISTER_1
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li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(30)
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stvx v30, r1, SCRATCH_REGISTER_1
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li SCRATCH_REGISTER_1, PPC_EXC_VR_OFFSET(31)
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stvx v31, r1, SCRATCH_REGISTER_1
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mfvrsave SCRATCH_REGISTER_1
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stw SCRATCH_REGISTER_1, PPC_EXC_VRSAVE_OFFSET(r1)
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#endif
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#ifdef PPC_MULTILIB_FPU
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stfd f0, PPC_EXC_FR_OFFSET(0)(r1)
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mffs f0
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stfd f0, PPC_EXC_FPSCR_OFFSET(r1)
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stfd f1, PPC_EXC_FR_OFFSET(1)(r1)
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stfd f2, PPC_EXC_FR_OFFSET(2)(r1)
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stfd f3, PPC_EXC_FR_OFFSET(3)(r1)
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stfd f4, PPC_EXC_FR_OFFSET(4)(r1)
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stfd f5, PPC_EXC_FR_OFFSET(5)(r1)
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stfd f6, PPC_EXC_FR_OFFSET(6)(r1)
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stfd f7, PPC_EXC_FR_OFFSET(7)(r1)
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stfd f8, PPC_EXC_FR_OFFSET(8)(r1)
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stfd f9, PPC_EXC_FR_OFFSET(9)(r1)
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stfd f10, PPC_EXC_FR_OFFSET(10)(r1)
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stfd f11, PPC_EXC_FR_OFFSET(11)(r1)
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stfd f12, PPC_EXC_FR_OFFSET(12)(r1)
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stfd f13, PPC_EXC_FR_OFFSET(13)(r1)
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stfd f14, PPC_EXC_FR_OFFSET(14)(r1)
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stfd f15, PPC_EXC_FR_OFFSET(15)(r1)
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stfd f16, PPC_EXC_FR_OFFSET(16)(r1)
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stfd f17, PPC_EXC_FR_OFFSET(17)(r1)
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stfd f18, PPC_EXC_FR_OFFSET(18)(r1)
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stfd f19, PPC_EXC_FR_OFFSET(19)(r1)
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stfd f20, PPC_EXC_FR_OFFSET(20)(r1)
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stfd f21, PPC_EXC_FR_OFFSET(21)(r1)
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stfd f22, PPC_EXC_FR_OFFSET(22)(r1)
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stfd f23, PPC_EXC_FR_OFFSET(23)(r1)
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stfd f24, PPC_EXC_FR_OFFSET(24)(r1)
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stfd f25, PPC_EXC_FR_OFFSET(25)(r1)
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stfd f26, PPC_EXC_FR_OFFSET(26)(r1)
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stfd f27, PPC_EXC_FR_OFFSET(27)(r1)
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stfd f28, PPC_EXC_FR_OFFSET(28)(r1)
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stfd f29, PPC_EXC_FR_OFFSET(29)(r1)
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stfd f30, PPC_EXC_FR_OFFSET(30)(r1)
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stfd f31, PPC_EXC_FR_OFFSET(31)(r1)
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#endif
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li r3, 9
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addi r4, r1, FRAME_LINK_SPACE
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b _Terminate
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PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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