forked from Imagelibrary/rtems
169 lines
3.7 KiB
C
169 lines
3.7 KiB
C
/**
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* @file
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*
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* Au1x00 Interrupt Vectoring
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*/
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/*
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* Copyright (c) 2005 by Cogent Computer Systems
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* Written by Jay Monkman <jtm@lopingdog.com>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <rtems.h>
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#include <stdlib.h>
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#include <libcpu/au1x00.h>
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#include <libcpu/isr_entries.h>
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#include <rtems/irq.h>
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#include <bsp/irq.h>
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#include <bsp/irq-generic.h>
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static void call_vectored_isr(CPU_Interrupt_frame *, uint32_t , void *);
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#include <rtems/bspIo.h> /* for printk */
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void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
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{
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unsigned int sr;
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unsigned int cause;
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mips_get_sr( sr );
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mips_get_cause( cause );
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cause &= (sr & SR_IMASK);
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cause >>= CAUSE_IPSHIFT;
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/* count/compare interrupt */
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if ( cause & 0x80 ) {
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unsigned long zero = 0;
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/*
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* I don't see a good way to disable the compare
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* interrupt, so let's just ignore it.
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*/
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__asm__ volatile ("mtc0 %0, $11\n" :: "r" (zero));
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}
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/* Performance counter */
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if ( cause & 0x40 ) {
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bsp_interrupt_handler_dispatch(AU1X00_IRQ_PERF);
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}
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/* Interrupt controller 0 */
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if ( cause & 0x0c ) {
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call_vectored_isr(frame, cause, (void *)AU1X00_IC0_ADDR);
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}
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/* Interrupt controller 1 */
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if ( cause & 0x30 ) {
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call_vectored_isr(frame, cause, (void *)AU1X00_IC1_ADDR);
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}
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/* SW[0] */
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if ( cause & 0x01 )
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bsp_interrupt_handler_dispatch( AU1X00_IRQ_SW0 );
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/* SW[1] */
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if ( cause & 0x02 )
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bsp_interrupt_handler_dispatch( AU1X00_IRQ_SW1 );
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}
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void mips_default_isr( int vector )
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{
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unsigned int sr;
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unsigned int cause;
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mips_get_sr( sr );
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mips_get_cause( cause );
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printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n",
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vector, cause, sr );
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rtems_fatal_error_occurred(1);
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}
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static void call_vectored_isr(
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CPU_Interrupt_frame *frame,
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uint32_t cause,
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void *ctrlr
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)
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{
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uint32_t src;
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uint32_t mask;
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int index;
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/* get mask register */
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mask = AU1X00_IC_MASKRD(ctrlr);
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/* check request 0 */
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src = AU1X00_IC_REQ0INT(ctrlr);
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src = src & mask;
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index = 0;
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while (src) {
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/* check LSB */
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if (src & 1) {
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/* clear rising/falling edge detects */
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AU1X00_IC_RISINGCLR(ctrlr) = (1 << index);
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AU1X00_IC_FALLINGCLR(ctrlr) = (1 << index);
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au_sync();
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bsp_interrupt_handler_dispatch(AU1X00_IRQ_IC0_BASE + index);
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}
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index ++;
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/* shift, and make sure MSB is clear */
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src = (src >> 1) & 0x7fffffff;
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}
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/* check request 1 */
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src = AU1X00_IC_REQ1INT(ctrlr);
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src = src & mask;
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index = 0;
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while (src) {
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/* check LSB */
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if (src & 1) {
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/* clear rising/falling edge detects */
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AU1X00_IC_RISINGCLR(ctrlr) = (1 << index);
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AU1X00_IC_FALLINGCLR(ctrlr) = (1 << index);
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au_sync();
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bsp_interrupt_handler_dispatch(AU1X00_IRQ_IC0_BASE + index);
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}
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index ++;
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/* shift, and make sure MSB is clear */
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src = (src >> 1) & 0x7fffffff;
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}
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}
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/* Generate a software interrupt */
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int assert_sw_irq(uint32_t irqnum)
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{
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uint32_t cause;
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if (irqnum <= 1) {
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mips_get_cause(cause);
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cause = cause | ((irqnum + 1) << CAUSE_IPSHIFT);
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mips_set_cause(cause);
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return irqnum;
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} else {
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return -1;
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}
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}
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/* Clear a software interrupt */
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int negate_sw_irq(uint32_t irqnum)
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{
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uint32_t cause;
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if (irqnum <= 1) {
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mips_get_cause(cause);
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cause = cause & ~((irqnum + 1) << CAUSE_IPSHIFT);
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mips_set_cause(cause);
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return irqnum;
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} else {
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return -1;
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}
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}
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