forked from Imagelibrary/rtems
511dc4b2be
Statically initialize the interrupt stack area
(_Configuration_Interrupt_stack_area_begin,
_Configuration_Interrupt_stack_area_end, and
_Configuration_Interrupt_stack_size) via <rtems/confdefs.h>. Place the
interrupt stack area in a special section ".rtemsstack.interrupt". Let
BSPs define the optimal placement of this section in their linker
command files (e.g. in a fast on-chip memory).
This change makes makes the CPU_HAS_SOFTWARE_INTERRUPT_STACK and
CPU_HAS_HARDWARE_INTERRUPT_STACK CPU port defines superfluous, since the
low level initialization code has all information available via global
symbols.
This change makes the CPU_ALLOCATE_INTERRUPT_STACK CPU port define
superfluous, since the interrupt stacks are allocated by confdefs.h for
all architectures. There is no need for BSP-specific linker command
file magic (except the section placement), see previous ARM linker
command file as a bad example.
Remove _CPU_Install_interrupt_stack(). Initialize the hardware
interrupt stack in _CPU_Initialize() if necessary (e.g.
m68k_install_interrupt_stack()).
The optional _CPU_Interrupt_stack_setup() is still useful to customize
the registration of the interrupt stack area in the per-CPU information.
The initialization stack can reuse the interrupt stack, since
* interrupts are disabled during the sequential system initialization,
and
* the boot_card() function does not return.
This stack resuse saves memory.
Changes per architecture:
arm:
* Mostly replace the linker symbol based configuration of stacks with
the standard <rtems/confdefs.h> configuration via
CONFIGURE_INTERRUPT_STACK_SIZE. The size of the FIQ, ABT and UND
mode stack is still defined via linker symbols. These modes are
rarely used in applications and the default values provided by the
BSP should be sufficient in most cases.
* Remove the bsp_processor_count linker symbol hack used for the SMP
support. This is possible since the interrupt stack area is now
allocated by the linker and not allocated from the heap. This makes
some configure.ac stuff obsolete. Remove the now superfluous BSP
variants altcycv_devkit_smp and realview_pbx_a9_qemu_smp.
bfin:
* Remove unused magic linker command file allocation of initialization
stack. Maybe a previous linker command file copy and paste problem?
In the start.S the initialization stack is set to a hard coded value.
lm32, m32c, mips, nios2, riscv, sh, v850:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
m68k:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
powerpc:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
* Used dedicated memory region (REGION_RTEMSSTACK) for the interrupt
stack on BSPs using the shared linkcmds.base (replacement for
REGION_RWEXTRA).
sparc:
* Remove the hard coded initialization stack. Use the interrupt stack
for the initialization stack on the boot processor. This saves
16KiB of RAM.
Update #3459.
# Author: Alexandra Kossovsky <sasha@oktet.ru>
# Victor Vengerov <vvv@oktet.ru>
# OKTET Ltd, http://www.oktet.ru
#
BSP NAME: generic SH4 (gensh4)
BOARD: n/a
BUS: n/a
CPU FAMILY: Hitachi SH
CPU: SH 7750
COPROCESSORS: none
MODE: n/a
DEBUG MONITOR: gdb (sh-ipl-g+ loader/stub)
PERIPHERALS
===========
TIMERS: on-chip
SERIAL PORTS: on-chip (with 2 ports)
REAL-TIME CLOCK: none
DMA: not used
VIDEO: none
SCSI: none
NETWORKING: none
DRIVER INFORMATION
==================
CLOCK DRIVER: on-chip timer
IOSUPP DRIVER: default
SHMSUPP: n/a
TIMER DRIVER: on-chip timer
TTY DRIVER: /dev/console
STDIO
=====
PORT: /dev/console
ELECTRICAL: n/a
BAUD: n/a
BITS PER CHARACTER: n/a
PARITY: n/a
STOP BITS: n/a
NOTES
=====
(1) Driver for the on-chip serial devices is tested only with 1st serial
port. We cannot test it on serial port with FIFO.
Console driver has 4 modes -- 2 with termios (interrupt-driven &
poll-driven modes), one raw mode working with serial port directly,
without termios, and one mode working with gdb stub (using 'trapa'
handled by sh-ipl-g+).
(2) The present 'hw_init.c' file provides 'early_hw_init'(void) which
is normally called from 'start.S' to provide such minimal HW setup.
It is written in C, but it should be noted that any accesses to memory
(except hardware registers) are prohibited until hardware not
initialized. To avoid access to stack, hw_init.c should be compiled with
-fomit-frame-pointer.
hw_init.c also provides 'bsp_cache_on'(void) normally called from
'start.S' after copying all data from rom to ram.
(3) In 'configure.ac' you should properly set 'CPU_CLOCK_RATE_HZ'.
It is frequency fed to the CPU core (external clock frequency can be
multiplied by on-chip PLLs). Please note that it is not a frequency of
external oscillator! See Hardware Manual, section 10, for details.
Global variable 'SH4_CPU_HZ_Frequency' is declared in 'bsp.h' and
initilized in 'bspstart.c' to ${HZ}. It is used by sci driver,
which exists in 'libcpu/sh/sh7750'.
(4) There is SH4_WITH_IPL macro in console driver 'sh4_uart.h'.
When it is defined, the application works under
gdb-stub (it is able to turn cache on by 'trapa', use gdb mode in console
driver and get out from gdb to use other console modes).
(5) There are 3 likcmds:
- linkcmds: code and data loaded to RAM. No code/data moving required.
- linkcmds.rom: code executed from the ROM; .data section moved to the
RAM on initialization.
- linkcmds.rom2ram: execution started from the ROM (after reset); code
and data moved to the RAM and execution continued from RAM.
The same 'start.S' is used for all cases.
(6) You can get gdb stub from http://www.oktet.ru/download/sh4/sh-ipl.tar.gz.
It is based on 'sh-ipl-g+' package used in sh-linux project.
(7) This project was done in cooperation with Transas company
http://www.transas.com