forked from Imagelibrary/rtems
1b5549ae69
When using QEMU configurations that support SMP for Zynq7000 systems, the second core is started at the same time as the first core instead of waiting for an event to trigger a check for the value at 0xfffffff0 before jumping into RTEMS code. This makes the erroneously started core wait as expected and prevents prefetch and data aborts from occurring before the MMU has been properly configured. This was recently exposed by cleanup done to the ARM GICv2 driver that removed some delays which were allowing this to operate normally.
Xilinx Zynq Support
The Zynq is supports the common hard IP that is common to all versions of the Zynq device family.
MMU
To access the PL (FPGA Logic) create an MMU table in your application and create the entries that map to your FPGA IP.
QEMU
Tested only on Qemu.
git clone git://git.qemu.org/qemu.git qemu cd qemu git checkout 1b0d3845b454eaaac0b2064c78926ca4d739a080 mkdir build cd build ../configure --prefix=/opt/qemu --interp-prefix=/opt/qemu make make install export PATH="$PATH:/opt/qemu/bin"
qemu-system-arm -no-reboot -serial null -serial mon:stdio -net none -nographic -M xilinx-zynq-a9 -m 256M -kernel ticker.exe