forked from Imagelibrary/rtems
10ef7087f6
This alters the AArch64 page table generation and mapping code and MMU configuration to use page table level 0 in addition to levels 1, 2, and 3. This allows the mapping of up to 48 bits of memory space and is the maximum that can be mapped without relying on additional processor extensions. Mappings are restricted based on the number of physical address bits that the CPU supports.
75 lines
2.3 KiB
C
75 lines
2.3 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* @ingroup RTEMSBSPsAArch64Shared
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*
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* @brief AArch64 MMU implementation.
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*/
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/*
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* Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
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* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <bsp/aarch64-mmu.h>
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#include <rtems/score/cpu.h>
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/*
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* This must have a non-header implementation because it is used by libdebugger.
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*/
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rtems_status_code aarch64_mmu_map(
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uintptr_t addr,
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uint64_t size,
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uint64_t flags
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)
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{
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rtems_status_code sc;
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uint64_t max_mappable = 1LLU << aarch64_mmu_get_cpu_pa_bits();
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if ( addr >= max_mappable || (addr + size) > max_mappable ) {
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return RTEMS_INVALID_ADDRESS;
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}
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aarch64_mmu_disable();
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sc = aarch64_mmu_map_block(
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(uint64_t *) bsp_translation_table_base,
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0x0,
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addr,
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size,
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-1,
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flags
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);
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_AARCH64_Data_synchronization_barrier();
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__asm__ volatile(
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"tlbi vmalle1\n"
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);
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_AARCH64_Data_synchronization_barrier();
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_AARCH64_Instruction_synchronization_barrier();
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aarch64_mmu_enable();
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return sc;
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}
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