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rtems/bsps/arm/shared/start/start.S
Sebastian Huber 511dc4b2be Rework initialization and interrupt stack support 
Statically initialize the interrupt stack area
(_Configuration_Interrupt_stack_area_begin,
_Configuration_Interrupt_stack_area_end, and
_Configuration_Interrupt_stack_size) via <rtems/confdefs.h>.  Place the
interrupt stack area in a special section ".rtemsstack.interrupt".  Let
BSPs define the optimal placement of this section in their linker
command files (e.g. in a fast on-chip memory).

This change makes makes the CPU_HAS_SOFTWARE_INTERRUPT_STACK and
CPU_HAS_HARDWARE_INTERRUPT_STACK CPU port defines superfluous, since the
low level initialization code has all information available via global
symbols.

This change makes the CPU_ALLOCATE_INTERRUPT_STACK CPU port define
superfluous, since the interrupt stacks are allocated by confdefs.h for
all architectures.  There is no need for BSP-specific linker command
file magic (except the section placement), see previous ARM linker
command file as a bad example.

Remove _CPU_Install_interrupt_stack().  Initialize the hardware
interrupt stack in _CPU_Initialize() if necessary (e.g.
m68k_install_interrupt_stack()).

The optional _CPU_Interrupt_stack_setup() is still useful to customize
the registration of the interrupt stack area in the per-CPU information.

The initialization stack can reuse the interrupt stack, since

  * interrupts are disabled during the sequential system initialization,
    and

  * the boot_card() function does not return.

This stack resuse saves memory.

Changes per architecture:

arm:

  * Mostly replace the linker symbol based configuration of stacks with
    the standard <rtems/confdefs.h> configuration via
    CONFIGURE_INTERRUPT_STACK_SIZE.  The size of the FIQ, ABT and UND
    mode stack is still defined via linker symbols.  These modes are
    rarely used in applications and the default values provided by the
    BSP should be sufficient in most cases.

  * Remove the bsp_processor_count linker symbol hack used for the SMP
    support. This is possible since the interrupt stack area is now
    allocated by the linker and not allocated from the heap.  This makes
    some configure.ac stuff obsolete.  Remove the now superfluous BSP
    variants altcycv_devkit_smp and realview_pbx_a9_qemu_smp.

bfin:

  * Remove unused magic linker command file allocation of initialization
    stack.  Maybe a previous linker command file copy and paste problem?
    In the start.S the initialization stack is set to a hard coded value.

lm32, m32c, mips, nios2, riscv, sh, v850:

  * Remove magic linker command file allocation of initialization stack.
    Reuse interrupt stack for initialization stack.

m68k:

  * Remove magic linker command file allocation of initialization stack.
    Reuse interrupt stack for initialization stack.

powerpc:

  * Remove magic linker command file allocation of initialization stack.
    Reuse interrupt stack for initialization stack.

  * Used dedicated memory region (REGION_RTEMSSTACK) for the interrupt
    stack on BSPs using the shared linkcmds.base (replacement for
    REGION_RWEXTRA).

sparc:

  * Remove the hard coded initialization stack.  Use the interrupt stack
    for the initialization stack on the boot processor.  This saves
    16KiB of RAM.

Update #3459.
2018-06-27 08:58:16 +02:00

426 lines
9.0 KiB
ArmAsm
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/**
* @file
*
* @brief Boot and system start code.
*/
/*
* Copyright (c) 2008, 2018 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems/asm.h>
#include <rtems/score/percpu.h>
#include <bspopts.h>
#include <bsp/irq.h>
/* Global symbols */
.globl _start
.globl bsp_start_vector_table_begin
.globl bsp_start_vector_table_end
.globl bsp_start_vector_table_size
.globl bsp_vector_table_size
.section ".bsp_start_text", "ax"
#if defined(ARM_MULTILIB_ARCH_V4)
.globl bsp_start_hook_0_done
#ifdef BSP_START_IN_HYP_SUPPORT
.globl bsp_start_hyp_vector_table_begin
#endif
.arm
/*
* This is the exception vector table and the pointers to the default
* exceptions handlers.
*/
bsp_start_vector_table_begin:
ldr pc, handler_addr_reset
ldr pc, handler_addr_undef
ldr pc, handler_addr_swi
ldr pc, handler_addr_prefetch
ldr pc, handler_addr_abort
/* Program signature checked by boot loader */
.word 0xb8a06f58
ldr pc, handler_addr_irq
ldr pc, handler_addr_fiq
handler_addr_reset:
#ifdef BSP_START_RESET_VECTOR
.word BSP_START_RESET_VECTOR
#else
.word _start
#endif
handler_addr_undef:
.word _ARMV4_Exception_undef_default
handler_addr_swi:
.word _ARMV4_Exception_swi_default
handler_addr_prefetch:
.word _ARMV4_Exception_pref_abort_default
handler_addr_abort:
.word _ARMV4_Exception_data_abort_default
handler_addr_reserved:
.word _ARMV4_Exception_reserved_default
handler_addr_irq:
.word _ARMV4_Exception_interrupt
handler_addr_fiq:
.word _ARMV4_Exception_fiq_default
bsp_start_vector_table_end:
#ifdef BSP_START_IN_HYP_SUPPORT
bsp_start_hyp_vector_table_begin:
ldr pc, handler_addr_hyp_reset
ldr pc, handler_addr_hyp_undef
ldr pc, handler_addr_hyp_swi
ldr pc, handler_addr_hyp_prefetch
ldr pc, handler_addr_hyp_abort
ldr pc, handler_addr_hyp_hyp
ldr pc, handler_addr_hyp_irq
ldr pc, handler_addr_hyp_fiq
handler_addr_hyp_reset:
.word _ARMV4_Exception_reserved_default
handler_addr_hyp_undef:
.word _ARMV4_Exception_reserved_default
handler_addr_hyp_swi:
.word _ARMV4_Exception_reserved_default
handler_addr_hyp_prefetch:
.word _ARMV4_Exception_reserved_default
handler_addr_hyp_abort:
.word _ARMV4_Exception_reserved_default
handler_addr_hyp_hyp:
.word _ARMV4_Exception_reserved_default
handler_addr_hyp_irq:
.word _ARMV4_Exception_reserved_default
handler_addr_hyp_fiq:
.word _ARMV4_Exception_reserved_default
bsp_start_hyp_vector_table_end:
#endif
/* Start entry */
_start:
/*
* We do not save the context since we do not return to the boot
* loader but preserve r1 and r2 to allow access to bootloader parameters
*/
#ifndef BSP_START_NEEDS_REGISTER_INITIALIZATION
mov r5, r1 /* machine type number or ~0 for DT boot */
mov r6, r2 /* physical address of ATAGs or DTB */
#else /* BSP_START_NEEDS_REGISTER_INITIALIZATION */
bl bsp_start_init_registers_core
#endif
#ifdef RTEMS_SMP
/* Read MPIDR and get current processor index */
mrc p15, 0, r7, c0, c0, 5
and r7, #0xff
#endif
#ifdef BSP_START_COPY_FDT_FROM_U_BOOT
#ifdef RTEMS_SMP
cmp r7, #0
bne 1f
#endif
mov r0, r6
bl bsp_fdt_copy
1:
#endif
#ifdef RTEMS_SMP
/*
* Get current per-CPU control and store it in PL1 only Thread ID
* Register (TPIDRPRW).
*/
ldr r1, =_Per_CPU_Information
add r1, r1, r7, asl #PER_CPU_CONTROL_SIZE_LOG2
mcr p15, 0, r1, c13, c0, 4
#endif
/* Calculate interrupt stack area end for current processor */
ldr r1, =_Configuration_Interrupt_stack_size
#ifdef RTEMS_SMP
add r7, #1
mul r1, r1, r7
#endif
ldr r2, =_Configuration_Interrupt_stack_area_begin
add r7, r1, r2
/* Save original CPSR value */
mrs r4, cpsr
#ifdef BSP_START_IN_HYP_SUPPORT
orr r0, r4, #(ARM_PSR_I | ARM_PSR_F)
msr cpsr, r4
and r0, r4, #ARM_PSR_M_MASK
cmp r0, #ARM_PSR_M_HYP
bne bsp_start_skip_hyp_svc_switch
/* Boot loader starts kernel in HYP mode, switch to SVC necessary */
ldr r1, =bsp_stack_hyp_size
mov sp, r7
sub r7, r7, r1
bl bsp_start_arm_drop_hyp_mode
bsp_start_skip_hyp_svc_switch:
#endif
/* Initialize stack pointer registers for the various modes */
/* Enter FIQ mode and set up the FIQ stack pointer */
mov r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
msr cpsr, r0
ldr r1, =bsp_stack_fiq_size
mov sp, r7
sub r7, r7, r1
#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
bl bsp_start_init_registers_banked_fiq
#endif
/* Enter ABT mode and set up the ABT stack pointer */
mov r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
msr cpsr, r0
ldr r1, =bsp_stack_abt_size
mov sp, r7
sub r7, r7, r1
/* Enter UND mode and set up the UND stack pointer */
mov r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
msr cpsr, r0
ldr r1, =bsp_stack_und_size
mov sp, r7
sub r7, r7, r1
/* Enter IRQ mode and set up the IRQ stack pointer */
mov r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
msr cpsr, r0
mov sp, r7
/*
* Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
* (interrupts are disabled).
*/
mov r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
msr cpsr, r0
mov sp, r7
/* Stay in SVC mode */
#ifdef ARM_MULTILIB_VFP
#ifdef ARM_MULTILIB_HAS_CPACR
/* Read CPACR */
mrc p15, 0, r0, c1, c0, 2
/* Enable CP10 and CP11 */
orr r0, r0, #(1 << 20)
orr r0, r0, #(1 << 22)
/*
* Clear ASEDIS and D32DIS. Writes to D32DIS are ignored for VFP-D16.
*/
bic r0, r0, #(3 << 30)
/* Write CPACR */
mcr p15, 0, r0, c1, c0, 2
isb
#endif
/* Enable FPU */
mov r0, #(1 << 30)
vmsr FPEXC, r0
#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
bl bsp_start_init_registers_vfp
#endif
#endif /* ARM_MULTILIB_VFP */
/*
* Branch to start hook 0.
*
* The previous code and parts of the start hook 0 may run with an
* address offset. This implies that only branches relative to the
* program counter are allowed. After the start hook 0 it is assumed
* that the code can run at its intended position. Thus the link
* register will be loaded with the absolute address. In THUMB mode
* the start hook 0 must be within a 2kByte range due to the branch
* instruction limitation.
*/
ldr lr, =bsp_start_hook_0_done
#ifdef __thumb__
orr lr, #1
#endif
SWITCH_FROM_ARM_TO_THUMB r0
mov r0, r4 /* original CPSR value */
mov r1, r5 /* machine type number or ~0 for DT boot */
mov r2, r6 /* physical address of ATAGs or DTB */
b bsp_start_hook_0
bsp_start_hook_0_done:
SWITCH_FROM_THUMB_TO_ARM
/*
* Initialize the exception vectors. This includes the exceptions
* vectors and the pointers to the default exception handlers.
*/
stmdb sp!, {r4, r5, r6}
ldr r0, =bsp_vector_table_begin
adr r1, bsp_start_vector_table_begin
cmp r0, r1
beq bsp_vector_table_copy_done
ldmia r1!, {r2-r9}
stmia r0!, {r2-r9}
ldmia r1!, {r2-r9}
stmia r0!, {r2-r9}
bsp_vector_table_copy_done:
ldmia sp!, {r0, r1, r2}
SWITCH_FROM_ARM_TO_THUMB r3
/* Branch to start hook 1 */
bl bsp_start_hook_1
/* Branch to boot card */
mov r0, #0
bl boot_card
twiddle:
/* Branch to reset function */
bl bsp_reset
b twiddle
#elif defined(ARM_MULTILIB_ARCH_V7M)
#include <rtems/score/armv7m.h>
.syntax unified
.thumb
bsp_start_vector_table_begin:
.word _Configuration_Interrupt_stack_area_end
.word _start /* Reset */
.word _ARMV7M_Exception_default /* NMI */
.word _ARMV7M_Exception_default /* Hard Fault */
.word _ARMV7M_Exception_default /* MPU Fault */
.word _ARMV7M_Exception_default /* Bus Fault */
.word _ARMV7M_Exception_default /* Usage Fault */
.word _ARMV7M_Exception_default /* Reserved */
.word _ARMV7M_Exception_default /* Reserved */
.word _ARMV7M_Exception_default /* Reserved */
.word _ARMV7M_Exception_default /* Reserved */
.word _ARMV7M_Exception_default /* SVC */
.word _ARMV7M_Exception_default /* Debug Monitor */
.word _ARMV7M_Exception_default /* Reserved */
.word _ARMV7M_Exception_default /* PendSV */
.word _ARMV7M_Exception_default /* SysTick */
.rept BSP_INTERRUPT_VECTOR_MAX + 1
.word _ARMV7M_Exception_default /* IRQ */
.endr
bsp_start_vector_table_end:
.thumb_func
_start:
#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
bl bsp_start_init_registers_core
#endif
#ifdef ARM_MULTILIB_VFP
#ifdef ARM_MULTILIB_HAS_CPACR
/*
* Enable CP10 and CP11 coprocessors for privileged and user mode in
* CPACR (bits 20-23). Ensure that write to register completes.
*/
ldr r0, =ARMV7M_CPACR
ldr r1, [r0]
orr r1, r1, #(0xf << 20)
str r1, [r0]
dsb
isb
#endif
#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
bl bsp_start_init_registers_vfp
#endif
#endif /* ARM_MULTILIB_VFP */
ldr sp, =_Configuration_Interrupt_stack_area_end
ldr lr, =bsp_start_hook_0_done + 1
b bsp_start_hook_0
bsp_start_hook_0_done:
bl bsp_start_hook_1
movs r0, #0
bl boot_card
twiddle:
bl bsp_reset
b twiddle
#endif /* defined(ARM_MULTILIB_ARCH_V7M) */
.set bsp_start_vector_table_size, bsp_start_vector_table_end - bsp_start_vector_table_begin
.set bsp_vector_table_size, bsp_start_vector_table_size
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