forked from Imagelibrary/rtems
9964895866
Adjust build support files to new directory layout. This patch is a part of the BSP source reorganization. Update #3285.
78 lines
1.7 KiB
ArmAsm
78 lines
1.7 KiB
ArmAsm
/**
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* @file
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*
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* @brief Boot and system start code.
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*/
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/*
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* Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz>
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*
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* Czech Technical University in Prague
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* Zikova 1903/4
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* 166 36 Praha 6
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* Czech Republic
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <rtems/asm.h>
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#include <rtems/system.h>
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#include <rtems/score/cpu.h>
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#include <bspopts.h>
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#include <bsp/irq.h>
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#include <bsp/linker-symbols.h>
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.extern bsp_start_hyp_vector_table_begin
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.globl bsp_start_arm_drop_hyp_mode
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.globl bsp_arm_drop_hyp_mode_only
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.arm
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/*
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* The routine is called from startup code and it should
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* preserve all registers except r2 and r3. r0 can be used
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* as pass though argument in some cases, a1 is used for
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* CPU stack offset during startup and r4 to r6 to preserve
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* booloader arguments
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*/
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bsp_start_arm_drop_hyp_mode:
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ldr r2, bsp_start_hyp_vector_table_begin_addr
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mcr p15, 4, r2, c12, c0, 0
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mov r2, #0
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mcr p15, 4, r2, c1, c1, 0
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mcr p15, 4, r2, c1, c1, 2
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mcr p15, 4, r2, c1, c1, 3
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/*
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* HSCTLR.TE
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* optional start of hypervisor handlers in Thumb mode
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* orr r0, #(1 << 30)
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*/
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mcr p15, 4, r2, c1, c0, 0 /* HSCTLR */
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mrc p15, 4, r2, c1, c1, 1 /* HDCR */
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and r2, #0x1f /* Preserve HPMN */
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mcr p15, 4, r2, c1, c1, 1 /* HDCR */
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bsp_arm_drop_hyp_mode_only:
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/* Prepare SVC mode for eret */
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mrs r2, cpsr
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bic r2, r2, #ARM_PSR_M_MASK
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orr r2, r2, #ARM_PSR_M_SVC
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msr spsr_cxsf, r2
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adr r2, 1f
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.inst 0xe12ef302 /* msr ELR_hyp, r2 */
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mov r2, sp
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mov r3, lr
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.inst 0xe160006e /* eret */
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1: mov sp, r2
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mov lr, r3
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bx lr
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bsp_start_hyp_vector_table_begin_addr:
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.word bsp_start_hyp_vector_table_begin
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