forked from Imagelibrary/rtems
7ee5931393
The aim of this clock driver hook was to stop clock tick interrupts at some late point in the exit() procedure. The use of atexit() pulls in malloc() which pulls in errno. It is incompatible with the intention of the CONFIGURE_DISABLE_NEWLIB_REENTRANCY configuration option. The exit() function must be called from thread context, so accompanied clock tick interrupts should cause no harm. On the contrary, someone may assume a normal operating system operation, e.g. working timeouts. Remove the Clock_driver_support_shutdown_hardware() clock driver hook. Close #3436.
118 lines
3.0 KiB
C
118 lines
3.0 KiB
C
/* ckinit.c
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*
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* This file provides a template for the clock device driver initialization.
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*
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* Modified for sun4v - niagara
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*/
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/*
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* Copyright (c) 2010 Gedare Bloom.
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <stdlib.h>
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#include <rtems.h>
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#include <bsp.h>
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#include <bspopts.h>
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#include <boot/ofw.h>
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#include <rtems/bspIo.h>
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/* This is default frequency for simics simulator of niagara. Use the
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* get_Frequency function to determine the CPU clock frequency at runtime.
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*/
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#define CPU_FREQ (5000000)
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uint64_t sparc64_cycles_per_tick;
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/* TICK_CMPR and STICK_CMPR trigger soft interrupt 14 */
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#define CLOCK_VECTOR SPARC_SYNCHRONOUS_TRAP(0x4E)
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static unsigned int get_Frequency(void)
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{
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phandle root = ofw_find_device("/");
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unsigned int freq;
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if (ofw_get_property(root, "clock-frequency", &freq, sizeof(freq)) <= 0) {
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printk("Unable to determine frequency, default: 0x%x\n",CPU_FREQ);
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return CPU_FREQ;
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}
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return freq;
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}
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#define Clock_driver_support_at_tick() \
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Clock_driver_support_at_tick_helper()
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static void Clock_driver_support_at_tick_helper(void)
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{
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uint64_t tick_reg;
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int bit_mask;
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uint64_t pil_reg;
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bit_mask = SPARC_SOFTINT_TM_MASK | SPARC_SOFTINT_SM_MASK | (1<<14);
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sparc64_clear_interrupt_bits(bit_mask);
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sparc64_get_pil(pil_reg);
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if(pil_reg == 0xe) { /* 0xe is the tick compare interrupt (softint(14)) */
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pil_reg--;
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sparc64_set_pil(pil_reg); /* enable the next timer interrupt */
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}
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/* Note: sun4v uses stick_cmpr for clock driver for M5 simulator, which
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* does not currently have tick_cmpr implemented */
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/* TODO: this could be more efficiently implemented as a single assembly
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* inline */
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#if defined (SUN4U)
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sparc64_read_tick(tick_reg);
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#elif defined (SUN4V)
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sparc64_read_stick(tick_reg);
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#endif
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tick_reg &= ~(1UL<<63); /* mask out NPT bit, prevents int_dis from being set */
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tick_reg += sparc64_cycles_per_tick;
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#if defined (SUN4U)
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sparc64_write_tick_cmpr(tick_reg);
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#elif defined (SUN4V)
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sparc64_write_stick_cmpr(tick_reg);
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#endif
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}
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#define Clock_driver_support_install_isr(_new) \
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set_vector( _new, CLOCK_VECTOR, 1 )
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static void Clock_driver_support_initialize_hardware(void)
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{
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uint64_t tick_reg;
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int bit_mask;
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bit_mask = SPARC_SOFTINT_TM_MASK | SPARC_SOFTINT_SM_MASK | (1<<14);
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sparc64_clear_interrupt_bits(bit_mask);
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sparc64_cycles_per_tick =
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rtems_configuration_get_microseconds_per_tick()*(get_Frequency()/1000000);
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#if defined (SUN4U)
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sparc64_read_tick(tick_reg);
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#elif defined (SUN4V)
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sparc64_read_stick(tick_reg);
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#endif
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tick_reg &= ~(1UL<<63); /* mask out NPT bit, prevents int_dis from being set */
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tick_reg += sparc64_cycles_per_tick;
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#if defined (SUN4U)
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sparc64_write_tick_cmpr(tick_reg);
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#elif defined (SUN4V)
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sparc64_write_stick_cmpr(tick_reg);
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#endif
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}
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#define CLOCK_DRIVER_USE_DUMMY_TIMECOUNTER
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#include "../../../shared/dev/clock/clockimpl.h"
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