forked from Imagelibrary/rtems
87 lines
2.8 KiB
C
87 lines
2.8 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* @ingroup RTEMSBSPsShared
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*
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* @brief PSCI-based BSP CPU start.
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*/
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/*
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* Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
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* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <bsp/start.h>
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#include <bsp.h>
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#if defined( AARCH64_MULTILIB_ARCH_V8 ) || \
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defined( AARCH64_MULTILIB_ARCH_V8_ILP32 )
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#include <rtems/score/aarch64-system-registers.h>
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#else
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#include <rtems/score/aarch32-system-registers.h>
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#endif
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#if defined( AARCH64_MULTILIB_ARCH_V8 ) || \
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defined( AARCH64_MULTILIB_ARCH_V8_ILP32 )
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#define REGISTER_PREFIX "x"
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#else
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#define REGISTER_PREFIX "r"
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#endif
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bool _CPU_SMP_Start_processor( uint32_t cpu_index )
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{
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#if defined( AARCH64_MULTILIB_ARCH_V8 ) || \
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defined( AARCH64_MULTILIB_ARCH_V8_ILP32 )
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uint32_t PSCI_FN_SYSTEM_CPU_ON = 0xC4000003;
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uint64_t target_cpu = _AArch64_Read_mpidr_el1();
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uint64_t ret;
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#else
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uint32_t PSCI_FN_SYSTEM_CPU_ON = 0x84000003;
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uint32_t target_cpu = _AArch32_Read_mpidr();
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uint32_t ret;
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#endif
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target_cpu &= ~( 0xff0000ffUL );
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target_cpu |= cpu_index;
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__asm__ volatile (
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"mov " REGISTER_PREFIX "0, %1\n"
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"mov " REGISTER_PREFIX "1, %2\n"
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"mov " REGISTER_PREFIX "2, %3\n"
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"mov " REGISTER_PREFIX "3, #0\n"
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#ifdef BSP_CPU_ON_USES_SMC
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"smc #0\n"
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#else
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"hvc #0\n"
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#endif
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"mov %0, " REGISTER_PREFIX "0\n"
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: "=r" ( ret ) : "r" ( PSCI_FN_SYSTEM_CPU_ON ), "r" ( target_cpu ),
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"r" ( _start )
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: REGISTER_PREFIX "0", REGISTER_PREFIX "1", REGISTER_PREFIX "2",
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REGISTER_PREFIX "3"
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);
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return ret == 0;
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}
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