forked from Imagelibrary/rtems
04bd261726
Use the previously unused TPIDRPRW register to get the per-CPU control of the current processor. This avoids instructions in GET_SELF_CPU_CONTROL which are not available in Thumb mode.
157 lines
3.4 KiB
ArmAsm
157 lines
3.4 KiB
ArmAsm
/**
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* @file
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*
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* @ingroup ScoreCPU
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*
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* @brief ARM architecture support implementation.
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*/
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/*
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* This file contains all assembly code for the ARM implementation
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* of RTEMS.
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*
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* Copyright (c) 2007 by Ray Xu, <Rayx.cn@gmail.com>
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* Thumb support added.
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*
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* Copyright (c) 2002 by Advent Networks, Inc.
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* Jay Monkman <jmonkman@adventnetworks.com>
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*
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* COPYRIGHT (c) 2000 Canon Research Centre France SA.
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* Emmanuel Raguet, mailto:raguet@crf.canon.fr
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*
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* Copyright (c) 2013-2015 embedded brains GmbH
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <rtems/asm.h>
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#ifdef ARM_MULTILIB_ARCH_V4
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.text
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/*
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* void _CPU_Context_switch( run_context, heir_context )
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* void _CPU_Context_restore( run_context, heir_context )
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*
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* This routine performs a normal non-FP context.
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*
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* R0 = run_context R1 = heir_context
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*
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* This function copies the current registers to where r0 points, then
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* restores the ones from where r1 points.
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*
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* Using the ldm/stm opcodes save 2-3 us on 100 MHz ARM9TDMI with
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* a 16 bit data bus.
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*
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*/
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DEFINE_FUNCTION_ARM(_CPU_Context_switch)
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/* Start saving context */
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mrs r2, CPSR
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stmia r0, {r2, r4, r5, r6, r7, r8, r9, r10, r11, r13, r14}
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#ifdef ARM_MULTILIB_VFP
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add r3, r0, #ARM_CONTEXT_CONTROL_D8_OFFSET
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vstm r3, {d8-d15}
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#endif
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#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
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mrc p15, 0, r3, c13, c0, 3
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str r3, [r0, #ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET]
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#endif
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#ifdef RTEMS_SMP
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/* The executing context no longer executes on this processor */
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dmb
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mov r3, #0
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strb r3, [r0, #ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET]
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.L_check_is_executing:
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/* Check the is executing indicator of the heir context */
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add r3, r1, #ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET
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ldrexb r4, [r3]
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cmp r4, #0
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bne .L_get_potential_new_heir
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/* Try to update the is executing indicator of the heir context */
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mov r4, #1
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strexb r5, r4, [r3]
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cmp r5, #0
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bne .L_get_potential_new_heir
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dmb
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#endif
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/* Start restoring context */
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.L_restore:
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#if !defined(RTEMS_SMP) && defined(ARM_MULTILIB_HAS_LOAD_STORE_EXCLUSIVE)
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clrex
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#endif
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#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
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ldr r3, [r1, #ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET]
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mcr p15, 0, r3, c13, c0, 3
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#endif
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#ifdef ARM_MULTILIB_VFP
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add r3, r1, #ARM_CONTEXT_CONTROL_D8_OFFSET
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vldm r3, {d8-d15}
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#endif
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ldmia r1, {r2, r4, r5, r6, r7, r8, r9, r10, r11, r13, r14}
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msr CPSR_fsxc, r2
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#ifdef __thumb__
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bx lr
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nop
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#else
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mov pc, lr
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#endif
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/*
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* void _CPU_Context_restore( new_context )
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*
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* This function copies the restores the registers from where r0 points.
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* It must match _CPU_Context_switch()
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*
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*/
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DEFINE_FUNCTION_ARM(_CPU_Context_restore)
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mov r1, r0
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b .L_restore
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#ifdef RTEMS_SMP
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.L_get_potential_new_heir:
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GET_SELF_CPU_CONTROL r2
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/* We may have a new heir */
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/* Read the executing and heir */
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ldr r4, [r2, #PER_CPU_OFFSET_EXECUTING]
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ldr r5, [r2, #PER_CPU_OFFSET_HEIR]
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/*
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* Update the executing only if necessary to avoid cache line
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* monopolization.
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*/
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cmp r4, r5
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beq .L_check_is_executing
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/* Calculate the heir context pointer */
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sub r4, r1, r4
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add r1, r5, r4
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/* Update the executing */
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str r5, [r2, #PER_CPU_OFFSET_EXECUTING]
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b .L_check_is_executing
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#endif
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#endif /* ARM_MULTILIB_ARCH_V4 */
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