forked from Imagelibrary/rtems
79 lines
2.3 KiB
Plaintext
79 lines
2.3 KiB
Plaintext
#
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# Description of SIS as related to this BSP
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#
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BSP NAME: sis
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BOARD: any based on the European Space Agency's ERC32
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BUS: N/A
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CPU FAMILY: sparc
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CPU: ERC32 (SPARC V7 + on-CPU peripherals)
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based on Cypress 601/602
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COPROCESSORS: on-chip 602 compatible FPU
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MODE: 32 bit mode
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DEBUG MONITOR: none
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PERIPHERALS
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===========
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TIMERS:
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NAME: General Purpose Timer
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RESOLUTION: 50 nanoseconds - 12.8 microseconds
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NAME: Real Time Clock Timer
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RESOLUTION: 50 nanoseconds - 3.2768 milliseconds
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NAME: Watchdog Timer
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RESOLUTION: XXX
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SERIAL PORTS: 2 using on-chip UART
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REAL-TIME CLOCK: none
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DMA: on-chip
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VIDEO: none
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SCSI: none
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NETWORKING: none
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DRIVER INFORMATION
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==================
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CLOCK DRIVER: ERC32 internal Real Time Clock Timer
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IOSUPP DRIVER: N/A
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SHMSUPP: N/A
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TIMER DRIVER: ERC32 internal General Purpose Timer
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CONSOLE DRIVER: ERC32 internal UART
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STDIO
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=====
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PORT: Channel A
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ELECTRICAL: na since using simulator
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BAUD: na
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BITS PER CHARACTER: na
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PARITY: na
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STOP BITS: na
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Notes
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=====
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ERC32 BSP only supports single processor operations.
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A nice feature of this BSP is that the RAM and PROM size are set in the
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linkcmds file and the startup code programs the Memory Configuration
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Register based on those sizes.
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The Watchdog Timer is disabled.
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This code was developed and tested entirely using the SPARC Instruction
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Simulator (SIS) for the ERC32. All tests were known to run correctly
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against sis v1.7.
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Memory Map
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==========
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0x00000000 - 0x00000000 + _PROM_SIZE code and initialized data
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0x01f80000 on chip peripherals
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0x00000000 - 0x02000000 + _RAM_SIZE destination for initialized data
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BSS (i.e. unitialized data)
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C Heap (i.e. malloc area)
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RTEMS Workspace
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The C heap is assigned all memory between the end of the BSS and the
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RTEMS Workspace. The size of the RTEMS Workspace is based on that
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specified in the application's configuration table.
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