forked from Imagelibrary/rtems
d75b29d95e
Refactored the i2c driver to parse register values from the device tree rather than hardcoding them. But still the clocks have to initialized manually.
373 lines
9.0 KiB
C
373 lines
9.0 KiB
C
/**
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* @file
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*
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* @ingroup RTEMSBSPsARMBeagle
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*
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* @brief Global BSP definitions.
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*/
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/*
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* Copyright (c) 2012 Claas Ziemke. All rights reserved.
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*
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* Claas Ziemke
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* Kernerstrasse 11
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* 70182 Stuttgart
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* Germany
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* <claas.ziemke@gmx.net>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*
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* Modified by Ben Gras <beng@shrike-systems.com> to add lots
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* of beagleboard/beaglebone definitions, delete lpc32xx specific
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* ones, and merge with some other header files.
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*/
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#ifndef LIBBSP_ARM_BEAGLE_BSP_H
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#define LIBBSP_ARM_BEAGLE_BSP_H
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/**
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* @defgroup RTEMSBSPsARMBeagle Beaglebone
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*
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* @ingroup RTEMSBSPsARM
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*
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* @brief Beaglebone Board Support Package.
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*
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* @{
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*/
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#include <bspopts.h>
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#include <stdint.h>
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#include <bsp/start.h>
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#include <bsp/default-initial-extension.h>
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#include <bsp/beagleboneblack.h>
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#include <rtems.h>
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#include <rtems/irq-extension.h>
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#include <libcpu/omap3.h>
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#include <libcpu/am335x.h>
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#include <ofw/ofw.h>
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#define BSP_FEATURE_IRQ_EXTENSION
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/* UART base clock frequency */
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#define UART_CLOCK 48000000
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/* Access memory-mapped I/O devices */
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#define mmio_read(a) (*(volatile uint32_t *)(a))
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#define mmio_write(a,v) (*(volatile uint32_t *)(a) = (v))
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#define mmio_set(a,v) mmio_write((a), mmio_read((a)) | (v))
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#define mmio_clear(a,v) mmio_write((a), mmio_read((a)) & ~(v))
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#define REG16(x)(*((volatile uint16_t *)(x)))
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#define REG(x)(*((volatile uint32_t *)(x)))
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#define BIT(x)(0x1 << (x))
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// Start and End included
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#define BITS(Start, End) (((1 << (End+1)) - 1) & ~((1 << (Start)) - 1))
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#define udelay(u) rtems_task_wake_after(1 + ((u)/rtems_configuration_get_microseconds_per_tick()))
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int beagle_get_node_unit(phandle_t node);
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/* Write a uint32_t value to a memory address. */
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static inline void
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write32(uint32_t address, uint32_t value)
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{
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REG(address) = value;
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}
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/* Read an uint32_t from a memory address */
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static inline uint32_t
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read32(uint32_t address)
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{
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return REG(address);
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}
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/* Set a 32 bits value depending on a mask */
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static inline void
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set32(uint32_t address, uint32_t mask, uint32_t value)
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{
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uint32_t val;
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val = read32(address);
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/* clear the bits */
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val &= ~(mask);
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/* apply the value using the mask */
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val |= (value & mask);
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write32(address, val);
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}
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/* Write a uint16_t value to a memory address. */
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static inline void
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write16(uint32_t address, uint16_t value)
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{
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REG16(address) = value;
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}
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/* Read an uint16_t from a memory address */
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static inline uint16_t
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read16(uint32_t address)
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{
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return REG16(address);
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}
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/* Data synchronization barrier */
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static inline void dsb(void)
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{
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asm volatile("dsb" : : : "memory");
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}
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/* Instruction synchronization barrier */
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static inline void isb(void)
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{
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asm volatile("isb" : : : "memory");
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}
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/* flush data cache */
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static inline void flush_data_cache(void)
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{
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asm volatile(
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"mov r0, #0\n"
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"mcr p15, #0, r0, c7, c10, #4\n"
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: /* No outputs */
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: /* No inputs */
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: "r0","memory"
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);
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}
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#define __arch_getb(a) (*(volatile unsigned char *)(a))
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#define __arch_getw(a) (*(volatile unsigned short *)(a))
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#define __arch_getl(a) (*(volatile unsigned int *)(a))
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#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v))
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#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v))
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#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v))
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#define writeb(v,c) ({ unsigned char __v = v; __arch_putb(__v,c); __v; })
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#define writew(v,c) ({ unsigned short __v = v; __arch_putw(__v,c); __v; })
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#define writel(v,c) ({ unsigned int __v = v; __arch_putl(__v,c); __v; })
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#define readb(c) ({ unsigned char __v = __arch_getb(c); __v; })
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#define readw(c) ({ unsigned short __v = __arch_getw(c); __v; })
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#define readl(c) ({ unsigned int __v = __arch_getl(c); __v; })
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#define SYSTEM_CLOCK_12 12000000
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#define SYSTEM_CLOCK_13 13000000
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#define SYSTEM_CLOCK_192 19200000
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#define SYSTEM_CLOCK_96 96000000
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#if !defined(IS_DM3730) && !defined(IS_AM335X)
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#error Unrecognized BSP configured.
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#endif
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#if IS_DM3730
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#define BSP_DEVICEMEM_START 0x48000000
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#define BSP_DEVICEMEM_END 0x5F000000
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#endif
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#if IS_AM335X
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#define BSP_DEVICEMEM_START 0x44000000
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#define BSP_DEVICEMEM_END 0x57000000
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#endif
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/* per-target uart config */
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#if IS_AM335X
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#define BSP_CONSOLE_UART 1
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#define BSP_CONSOLE_UART_BASE BEAGLE_BASE_UART_1
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#define BSP_CONSOLE_UART_IRQ OMAP3_UART1_IRQ
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#define BEAGLE_BASE_UART_1 0x44E09000
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#define BEAGLE_BASE_UART_2 0x48022000
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#define BEAGLE_BASE_UART_3 0x48024000
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#endif
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/* per-target uart config */
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#if IS_DM3730
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#define BSP_CONSOLE_UART 3
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#define BSP_CONSOLE_UART_BASE BEAGLE_BASE_UART_3
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#define BSP_CONSOLE_UART_IRQ OMAP3_UART3_IRQ
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#define BEAGLE_BASE_UART_1 0x4806A000
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#define BEAGLE_BASE_UART_2 0x4806C000
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#define BEAGLE_BASE_UART_3 0x49020000
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#endif
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/* GPIO pin config */
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#if IS_AM335X
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#define BSP_GPIO_PIN_COUNT 128
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#define BSP_GPIO_PINS_PER_BANK 32
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#endif
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#if IS_DM3730
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#define BSP_GPIO_PIN_COUNT 192
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#define BSP_GPIO_PINS_PER_BANK 32
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#endif
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#if BSP_START_COPY_FDT_FROM_U_BOOT
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#define BSP_FDT_IS_SUPPORTED
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#endif
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/* i2c stuff */
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typedef struct {
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uint32_t rx_or_tx;
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uint32_t stat;
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uint32_t ctrl;
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uint32_t clk_hi;
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uint32_t clk_lo;
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uint32_t adr;
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uint32_t rxfl;
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uint32_t txfl;
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uint32_t rxb;
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uint32_t txb;
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uint32_t s_tx;
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uint32_t s_txfl;
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} beagle_i2c;
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/* sctlr */
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/* Read System Control Register */
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static inline uint32_t read_sctlr(void)
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{
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uint32_t ctl;
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asm volatile("mrc p15, 0, %[ctl], c1, c0, 0 @ Read SCTLR\n\t"
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: [ctl] "=r" (ctl));
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return ctl;
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}
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/* Write System Control Register */
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static inline void write_sctlr(uint32_t ctl)
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{
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asm volatile("mcr p15, 0, %[ctl], c1, c0, 0 @ Write SCTLR\n\t"
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: : [ctl] "r" (ctl));
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isb();
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}
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/* Read Auxiliary Control Register */
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static inline uint32_t read_actlr(void)
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{
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uint32_t ctl;
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asm volatile("mrc p15, 0, %[ctl], c1, c0, 1 @ Read ACTLR\n\t"
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: [ctl] "=r" (ctl));
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return ctl;
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}
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/* Write Auxiliary Control Register */
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static inline void write_actlr(uint32_t ctl)
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{
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asm volatile("mcr p15, 0, %[ctl], c1, c0, 1 @ Write ACTLR\n\t"
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: : [ctl] "r" (ctl));
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isb();
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}
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/* Write Translation Table Base Control Register */
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static inline void write_ttbcr(uint32_t bcr)
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{
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asm volatile("mcr p15, 0, %[bcr], c2, c0, 2 @ Write TTBCR\n\t"
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: : [bcr] "r" (bcr));
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isb();
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}
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/* Read Domain Access Control Register */
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static inline uint32_t read_dacr(void)
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{
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uint32_t dacr;
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asm volatile("mrc p15, 0, %[dacr], c3, c0, 0 @ Read DACR\n\t"
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: [dacr] "=r" (dacr));
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return dacr;
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}
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/* Write Domain Access Control Register */
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static inline void write_dacr(uint32_t dacr)
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{
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asm volatile("mcr p15, 0, %[dacr], c3, c0, 0 @ Write DACR\n\t"
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: : [dacr] "r" (dacr));
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isb();
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}
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static inline void refresh_tlb(void)
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{
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dsb();
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/* Invalidate entire unified TLB */
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asm volatile("mcr p15, 0, %[zero], c8, c7, 0 @ TLBIALL\n\t"
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: : [zero] "r" (0));
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/* Invalidate all instruction caches to PoU.
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* Also flushes branch target cache. */
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asm volatile("mcr p15, 0, %[zero], c7, c5, 0"
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: : [zero] "r" (0));
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/* Invalidate entire branch predictor array */
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asm volatile("mcr p15, 0, %[zero], c7, c5, 6"
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: : [zero] "r" (0)); /* flush BTB */
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dsb();
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isb();
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}
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/* Read Translation Table Base Register 0 */
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static inline uint32_t read_ttbr0(void)
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{
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uint32_t bar;
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asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
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: [bar] "=r" (bar));
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return bar & ARM_TTBR_ADDR_MASK;
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}
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/* Read Translation Table Base Register 0 */
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static inline uint32_t read_ttbr0_unmasked(void)
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{
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uint32_t bar;
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asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
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: [bar] "=r" (bar));
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return bar;
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}
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/* Write Translation Table Base Register 0 */
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static inline void write_ttbr0(uint32_t bar)
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{
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dsb();
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isb();
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/* In our setup TTBR contains the base address *and* the flags
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but other pieces of the kernel code expect ttbr to be the
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base address of the l1 page table. We therefore add the
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flags here and remove them in the read_ttbr0 */
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uint32_t v = (bar & ARM_TTBR_ADDR_MASK ) | ARM_TTBR_FLAGS_CACHED;
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asm volatile("mcr p15, 0, %[bar], c2, c0, 0 @ Write TTBR0\n\t"
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: : [bar] "r" (v));
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refresh_tlb();
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}
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/* Behaviour on fatal error; default: test-friendly.
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* set breakpoint to bsp_fatal_extension.
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*/
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/* Enabling BSP_PRESS_KEY_FOR_RESET prevents noninteractive testing */
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/*#define BSP_PRESS_KEY_FOR_RESET 1 */
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#define BSP_PRINT_EXCEPTION_CONTEXT 1
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/* human-readable exception info */
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#define BSP_RESET_BOARD_AT_EXIT 1
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/* causes qemu to exit, signaling end of test */
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/**
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* @brief Beagleboard specific set up of the MMU.
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*
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* Provide in the application to override.
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*/
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BSP_START_TEXT_SECTION void beagle_setup_mmu_and_cache(void);
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/* @} */
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#endif /* LIBBSP_ARM_BEAGLE_BSP_H */
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