forked from Imagelibrary/rtems
2afb22b7e1
A speciality of the RTEMS build system was the make preinstall step. It copied header files from arbitrary locations into the build tree. The header files were included via the -Bsome/build/tree/path GCC command line option. This has at least seven problems: * The make preinstall step itself needs time and disk space. * Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error. * There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult. * The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit. * An introduction of a new build system is difficult. * Include paths specified by the -B option are system headers. This may suppress warnings. * The parallel build had sporadic failures on some hosts. This patch removes the make preinstall step. All installed header files are moved to dedicated include directories in the source tree. Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc, etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g. erc32, imx, qoriq, etc. The new cpukit include directories are: * cpukit/include * cpukit/score/cpu/@RTEMS_CPU@/include * cpukit/libnetworking The new BSP include directories are: * bsps/include * bsps/@RTEMS_CPU@/include * bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include There are build tree include directories for generated files. The include directory order favours the most general header file, e.g. it is not possible to override general header files via the include path order. The "bootstrap -p" option was removed. The new "bootstrap -H" option should be used to regenerate the "headers.am" files. Update #3254.
573 lines
17 KiB
C
573 lines
17 KiB
C
/**
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* @file raspberrypi.h
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*
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* @ingroup raspberrypi_reg
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*
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* @brief Register definitions.
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*/
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/*
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* Copyright (c) 2014-2015 Andre Marques <andre.lousa.marques at gmail.com>
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* Copyright (c) 2013 Alan Cudmore.
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* Copyright (c) 2015 Yang Qiao
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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*
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* http://www.rtems.org/license/LICENSE
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*
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*/
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#ifndef LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H
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#define LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H
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#include <bspopts.h>
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#include <stdint.h>
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#include <bsp/utility.h>
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/**
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* @defgroup raspberrypi_reg Register Definitions
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*
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* @ingroup arm_raspberrypi
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*
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* @brief Register Definitions
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*
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* @{
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*/
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/**
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* @name Register Macros
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*
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* @{
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*/
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#define BCM2835_REG(x) (*(volatile uint32_t *)(x))
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#define BCM2835_BIT(n) (1 << (n))
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/** @} */
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/**
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* @name Peripheral Base Register Address
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*
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* @{
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*/
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#if (BSP_IS_RPI2 == 1)
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#define RPI_PERIPHERAL_BASE 0x3F000000
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#else
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#define RPI_PERIPHERAL_BASE 0x20000000
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#endif
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#define RPI_PERIPHERAL_SIZE 0x01000000
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/**
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* @name Internal ARM Timer Registers
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*
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* @{
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*/
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#define BCM2835_CLOCK_FREQ 250000000
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#define BCM2835_TIMER_BASE (RPI_PERIPHERAL_BASE + 0xB400)
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#define BCM2835_TIMER_LOD (BCM2835_TIMER_BASE + 0x00)
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#define BCM2835_TIMER_VAL (BCM2835_TIMER_BASE + 0x04)
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#define BCM2835_TIMER_CTL (BCM2835_TIMER_BASE + 0x08)
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#define BCM2835_TIMER_CLI (BCM2835_TIMER_BASE + 0x0C)
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#define BCM2835_TIMER_RIS (BCM2835_TIMER_BASE + 0x10)
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#define BCM2835_TIMER_MIS (BCM2835_TIMER_BASE + 0x14)
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#define BCM2835_TIMER_RLD (BCM2835_TIMER_BASE + 0x18)
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#define BCM2835_TIMER_DIV (BCM2835_TIMER_BASE + 0x1C)
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#define BCM2835_TIMER_CNT (BCM2835_TIMER_BASE + 0x20)
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#define BCM2835_TIMER_PRESCALE 0xF9
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/** @} */
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/**
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* @name Power Management and Watchdog Registers
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*
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* @{
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*/
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#define BCM2835_PM_PASSWD_MAGIC 0x5a000000
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#define BCM2835_PM_BASE (RPI_PERIPHERAL_BASE + 0x100000)
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#define BCM2835_PM_GNRIC (BCM2835_PM_BASE + 0x00)
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#define BCM2835_PM_GNRIC_POWUP 0x00000001
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#define BCM2835_PM_GNRIC_POWOK 0x00000002
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#define BCM2835_PM_GNRIC_ISPOW 0x00000004
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#define BCM2835_PM_GNRIC_MEMREP 0x00000008
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#define BCM2835_PM_GNRIC_MRDONE 0x00000010
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#define BCM2835_PM_GNRIC_ISFUNC 0x00000020
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#define BCM2835_PM_GNRIC_RSTN 0x00000fc0
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#define BCM2835_PM_GNRIC_ENAB 0x00001000
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#define BCM2835_PM_GNRIC_CFG 0x007f0000
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#define BCM2835_PM_AUDIO (BCM2835_PM_BASE + 0x04)
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#define BCM2835_PM_AUDIO_APSM 0x000fffff
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#define BCM2835_PM_AUDIO_CTRLEN 0x00100000
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#define BCM2835_PM_AUDIO_RSTN 0x00200000
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#define BCM2835_PM_STATUS (BCM2835_PM_BASE + 0x18)
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#define BCM2835_PM_RSTC (BCM2835_PM_BASE + 0x1c)
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#define BCM2835_PM_RSTC_DRCFG 0x00000003
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#define BCM2835_PM_RSTC_WRCFG 0x00000030
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#define BCM2835_PM_RSTC_WRCFG_FULL 0x00000020
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#define BCM2835_PM_RSTC_SRCFG 0x00000300
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#define BCM2835_PM_RSTC_QRCFG 0x00003000
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#define BCM2835_PM_RSTC_FRCFG 0x00030000
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#define BCM2835_PM_RSTC_HRCFG 0x00300000
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#define BCM2835_PM_RSTS (BCM2835_PM_BASE + 0x20)
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#define BCM2835_PM_RSTS_HADDRQ 0x00000001
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#define BCM2835_PM_RSTS_HADDRF 0x00000002
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#define BCM2835_PM_RSTS_HADDRH 0x00000004
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#define BCM2835_PM_RSTS_HADWRQ 0x00000010
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#define BCM2835_PM_RSTS_HADWRF 0x00000020
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#define BCM2835_PM_RSTS_HADWRH 0x00000040
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#define BCM2835_PM_RSTS_HADSRQ 0x00000100
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#define BCM2835_PM_RSTS_HADSRF 0x00000200
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#define BCM2835_PM_RSTS_HADSRH 0x00000400
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#define BCM2835_PM_RSTS_HADPOR 0x00001000
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#define BCM2835_PM_WDOG (BCM2835_PM_BASE + 0x24)
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/** @} */
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/**
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* @name GPIO Registers
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*
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* @{
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*/
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#define BCM2835_GPIO_REGS_BASE (RPI_PERIPHERAL_BASE + 0x200000)
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#define BCM2835_GPIO_GPFSEL1 (BCM2835_GPIO_REGS_BASE + 0x04)
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#define BCM2835_GPIO_GPSET0 (BCM2835_GPIO_REGS_BASE + 0x1C)
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#define BCM2835_GPIO_GPCLR0 (BCM2835_GPIO_REGS_BASE + 0x28)
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#define BCM2835_GPIO_GPLEV0 (BCM2835_GPIO_REGS_BASE + 0x34)
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#define BCM2835_GPIO_GPEDS0 (BCM2835_GPIO_REGS_BASE + 0x40)
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#define BCM2835_GPIO_GPREN0 (BCM2835_GPIO_REGS_BASE + 0x4C)
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#define BCM2835_GPIO_GPFEN0 (BCM2835_GPIO_REGS_BASE + 0x58)
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#define BCM2835_GPIO_GPHEN0 (BCM2835_GPIO_REGS_BASE + 0x64)
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#define BCM2835_GPIO_GPLEN0 (BCM2835_GPIO_REGS_BASE + 0x70)
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#define BCM2835_GPIO_GPAREN0 (BCM2835_GPIO_REGS_BASE + 0x7C)
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#define BCM2835_GPIO_GPAFEN0 (BCM2835_GPIO_REGS_BASE + 0x88)
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#define BCM2835_GPIO_GPPUD (BCM2835_GPIO_REGS_BASE + 0x94)
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#define BCM2835_GPIO_GPPUDCLK0 (BCM2835_GPIO_REGS_BASE + 0x98)
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/** @} */
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/**
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* @name AUX Registers
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*
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* @{
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*/
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#define BCM2835_AUX_BASE (RPI_PERIPHERAL_BASE + 0x215000)
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#define AUX_ENABLES (BCM2835_AUX_BASE + 0x04)
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#define AUX_MU_IO_REG (BCM2835_AUX_BASE + 0x40)
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#define AUX_MU_IER_REG (BCM2835_AUX_BASE + 0x44)
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#define AUX_MU_IIR_REG (BCM2835_AUX_BASE + 0x48)
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#define AUX_MU_LCR_REG (BCM2835_AUX_BASE + 0x4C)
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#define AUX_MU_MCR_REG (BCM2835_AUX_BASE + 0x50)
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#define AUX_MU_LSR_REG (BCM2835_AUX_BASE + 0x54)
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#define AUX_MU_MSR_REG (BCM2835_AUX_BASE + 0x58)
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#define AUX_MU_SCRATCH (BCM2835_AUX_BASE + 0x5C)
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#define AUX_MU_CNTL_REG (BCM2835_AUX_BASE + 0x60)
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#define AUX_MU_STAT_REG (BCM2835_AUX_BASE + 0x64)
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#define AUX_MU_BAUD_REG (BCM2835_AUX_BASE + 0x68)
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/** @} */
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/**
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* @name UART 0 (PL011) Registers
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*
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* @{
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*/
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#define BCM2835_UART0_BASE (RPI_PERIPHERAL_BASE + 0x201000)
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#define BCM2835_UART0_DR (BCM2835_UART0_BASE + 0x00)
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#define BCM2835_UART0_RSRECR (BCM2835_UART0_BASE + 0x04)
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#define BCM2835_UART0_FR (BCM2835_UART0_BASE + 0x18)
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#define BCM2835_UART0_ILPR (BCM2835_UART0_BASE + 0x20)
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#define BCM2835_UART0_IBRD (BCM2835_UART0_BASE + 0x24)
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#define BCM2835_UART0_FBRD (BCM2835_UART0_BASE + 0x28)
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#define BCM2835_UART0_LCRH (BCM2835_UART0_BASE + 0x2C)
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#define BCM2835_UART0_CR (BCM2835_UART0_BASE + 0x30)
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#define BCM2835_UART0_IFLS (BCM2835_UART0_BASE + 0x34)
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#define BCM2835_UART0_IMSC (BCM2835_UART0_BASE + 0x38)
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#define BCM2835_UART0_RIS (BCM2835_UART0_BASE + 0x3C)
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#define BCM2835_UART0_MIS (BCM2835_UART0_BASE + 0x40)
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#define BCM2835_UART0_ICR (BCM2835_UART0_BASE + 0x44)
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#define BCM2835_UART0_DMACR (BCM2835_UART0_BASE + 0x48)
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#define BCM2835_UART0_ITCR (BCM2835_UART0_BASE + 0x80)
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#define BCM2835_UART0_ITIP (BCM2835_UART0_BASE + 0x84)
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#define BCM2835_UART0_ITOP (BCM2835_UART0_BASE + 0x88)
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#define BCM2835_UART0_TDR (BCM2835_UART0_BASE + 0x8C)
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#define BCM2835_UART0_MIS_RX 0x10
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#define BCM2835_UART0_MIS_TX 0x20
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#define BCM2835_UART0_IMSC_RX 0x10
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#define BCM2835_UART0_IMSC_TX 0x20
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#define BCM2835_UART0_FR_RXFE 0x10
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#define BCM2835_UART0_FR_TXFF 0x20
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#define BCM2835_UART0_ICR_RX 0x10
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#define BCM2835_UART0_ICR_TX 0x20
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/** @} */
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/**
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* @name I2C (BSC) Registers
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*
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* @{
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*/
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#define BCM2835_I2C_BASE (RPI_PERIPHERAL_BASE + 0x804000)
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#define BCM2835_I2C_C (BCM2835_I2C_BASE + 0x00)
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#define BCM2835_I2C_S (BCM2835_I2C_BASE + 0x04)
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#define BCM2835_I2C_DLEN (BCM2835_I2C_BASE + 0x08)
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#define BCM2835_I2C_A (BCM2835_I2C_BASE + 0x0C)
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#define BCM2835_I2C_FIFO (BCM2835_I2C_BASE + 0x10)
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#define BCM2835_I2C_DIV (BCM2835_I2C_BASE + 0x14)
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#define BCM2835_I2C_DEL (BCM2835_I2C_BASE + 0x18)
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#define BCM2835_I2C_CLKT (BCM2835_I2C_BASE + 0x1C)
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/** @} */
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/**
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* @name SPI Registers
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*
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* @{
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*/
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#define BCM2835_SPI_BASE (RPI_PERIPHERAL_BASE + 0x204000)
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#define BCM2835_SPI_CS (BCM2835_SPI_BASE + 0x00)
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#define BCM2835_SPI_FIFO (BCM2835_SPI_BASE + 0x04)
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#define BCM2835_SPI_CLK (BCM2835_SPI_BASE + 0x08)
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#define BCM2835_SPI_DLEN (BCM2835_SPI_BASE + 0x0C)
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#define BCM2835_SPI_LTOH (BCM2835_SPI_BASE + 0x10)
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#define BCM2835_SPI_DC (BCM2835_SPI_BASE + 0x14)
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/** @} */
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/**
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* @name I2C/SPI slave BSC Registers
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*
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* @{
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*/
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#define BCM2835_I2C_SPI_BASE (RPI_PERIPHERAL_BASE + 0x214000)
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#define BCM2835_I2C_SPI_DR (BCM2835_I2C_SPI_BASE + 0x00)
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#define BCM2835_I2C_SPI_RSR (BCM2835_I2C_SPI_BASE + 0x04)
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#define BCM2835_I2C_SPI_SLV (BCM2835_I2C_SPI_BASE + 0x08)
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#define BCM2835_I2C_SPI_CR (BCM2835_I2C_SPI_BASE + 0x0C)
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#define BCM2835_I2C_SPI_FR (BCM2835_I2C_SPI_BASE + 0x10)
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#define BCM2835_I2C_SPI_IFLS (BCM2835_I2C_SPI_BASE + 0x14)
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#define BCM2835_I2C_SPI_IMSC (BCM2835_I2C_SPI_BASE + 0x18)
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#define BCM2835_I2C_SPI_RIS (BCM2835_I2C_SPI_BASE + 0x1C)
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#define BCM2835_I2C_SPI_MIS (BCM2835_I2C_SPI_BASE + 0x20)
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#define BCM2835_I2C_SPI_ICR (BCM2835_I2C_SPI_BASE + 0x24)
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#define BCM2835_I2C_SPI_DMACR (BCM2835_I2C_SPI_BASE + 0x28)
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#define BCM2835_I2C_SPI_TDR (BCM2835_I2C_SPI_BASE + 0x2C)
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#define BCM2835_I2C_SPI_GPUSTAT (BCM2835_I2C_SPI_BASE + 0x30)
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#define BCM2835_I2C_SPI_HCTRL (BCM2835_I2C_SPI_BASE + 0x34)
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/** @} */
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/**
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* @name IRQ Registers
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*
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* @{
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*/
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#define BCM2835_BASE_INTC (RPI_PERIPHERAL_BASE + 0xB200)
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#define BCM2835_IRQ_BASIC (BCM2835_BASE_INTC + 0x00)
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#define BCM2835_IRQ_PENDING1 (BCM2835_BASE_INTC + 0x04)
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#define BCM2835_IRQ_PENDING2 (BCM2835_BASE_INTC + 0x08)
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#define BCM2835_IRQ_FIQ_CTRL (BCM2835_BASE_INTC + 0x0C)
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#define BCM2835_IRQ_ENABLE1 (BCM2835_BASE_INTC + 0x10)
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#define BCM2835_IRQ_ENABLE2 (BCM2835_BASE_INTC + 0x14)
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#define BCM2835_IRQ_ENABLE_BASIC (BCM2835_BASE_INTC + 0x18)
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#define BCM2835_IRQ_DISABLE1 (BCM2835_BASE_INTC + 0x1C)
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#define BCM2835_IRQ_DISABLE2 (BCM2835_BASE_INTC + 0x20)
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#define BCM2835_IRQ_DISABLE_BASIC (BCM2835_BASE_INTC + 0x24)
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/** @} */
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/**
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* @name GPU Timer Registers
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*
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* @{
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*/
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/**
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* NOTE: The GPU uses Compare registers 0 and 2 for
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* it's own RTOS. 1 and 3 are available for use in
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* RTEMS.
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*/
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#define BCM2835_GPU_TIMER_BASE (RPI_PERIPHERAL_BASE + 0x3000)
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#define BCM2835_GPU_TIMER_CS (BCM2835_GPU_TIMER_BASE + 0x00)
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#define BCM2835_GPU_TIMER_CS_M0 0x00000001
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#define BCM2835_GPU_TIMER_CS_M1 0x00000002
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#define BCM2835_GPU_TIMER_CS_M2 0x00000004
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#define BCM2835_GPU_TIMER_CS_M3 0x00000008
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#define BCM2835_GPU_TIMER_CLO (BCM2835_GPU_TIMER_BASE + 0x04)
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#define BCM2835_GPU_TIMER_CHI (BCM2835_GPU_TIMER_BASE + 0x08)
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#define BCM2835_GPU_TIMER_C0 (BCM2835_GPU_TIMER_BASE + 0x0C)
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#define BCM2835_GPU_TIMER_C1 (BCM2835_GPU_TIMER_BASE + 0x10)
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#define BCM2835_GPU_TIMER_C2 (BCM2835_GPU_TIMER_BASE + 0x14)
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#define BCM2835_GPU_TIMER_C3 (BCM2835_GPU_TIMER_BASE + 0x18)
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/** @} */
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/**
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* @name EMMC Registers
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*
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* @{
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*/
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/**
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* NOTE: Since the SD controller follows the SDHCI standard,
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* the rtems-libbsd tree already provides the remaining registers.
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*/
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#define BCM2835_EMMC_BASE (RPI_PERIPHERAL_BASE + 0x300000)
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/** @} */
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/**
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* @name Mailbox Registers
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*
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* @{
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*/
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#define BCM2835_MBOX_BASE (RPI_PERIPHERAL_BASE+0xB880)
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#define BCM2835_MBOX_PEEK (BCM2835_MBOX_BASE+0x10)
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#define BCM2835_MBOX_READ (BCM2835_MBOX_BASE+0x00)
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#define BCM2835_MBOX_WRITE (BCM2835_MBOX_BASE+0x20)
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#define BCM2835_MBOX_STATUS (BCM2835_MBOX_BASE+0x18)
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#define BCM2835_MBOX_SENDER (BCM2835_MBOX_BASE+0x14)
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#define BCM2835_MBOX_CONFIG (BCM2835_MBOX_BASE+0x1C)
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#define BCM2835_MBOX_FULL 0x80000000
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#define BCM2835_MBOX_EMPTY 0x40000000
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/** @} */
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/**
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* @name Mailbox Channels
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*
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* @{
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*/
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/* Power Manager channel */
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#define BCM2835_MBOX_CHANNEL_PM 0
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/* Framebuffer channel */
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#define BCM2835_MBOX_CHANNEL_FB 1
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/* Virtual UART channel */
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#define BCM2835_MBOX_CHANNEL_VUART 2
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/* VCHIQ channel */
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#define BCM2835_MBOX_CHANNEL_VCHIQ 3
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/* LEDs channel */
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#define BCM2835_MBOX_CHANNEL_LED 4
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/* Button channel */
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#define BCM2835_MBOX_CHANNEL_BUTTON 5
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/* Touch screen channel */
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#define BCM2835_MBOX_CHANNEL_TOUCHS 6
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/* Property tags (ARM <-> VC) channel */
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#define BCM2835_MBOX_CHANNEL_PROP_AVC 8
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/* Property tags (VC <-> ARM) channel */
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#define BCM2835_MBOX_CHANNEL_PROP_VCA 9
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/** @} */
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/**
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* @name USB Registers
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*
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* @{
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*/
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#define BCM2835_USB_BASE (RPI_PERIPHERAL_BASE + 0x980000) /* DTC_OTG USB controller */
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/** @} */
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/**
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* @name Raspberry Pi 2 CPU Cores Local Peripherals
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|
*
|
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* @{
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|
*/
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#define BCM2836_CORE_LOCAL_PERIPH_BASE 0x40000000
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#define BCM2836_CORE_LOCAL_PERIPH_SIZE 0x00040000
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/** @} */
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|
|
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/**
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* @name Raspberry Pi 2 Mailbox Register Defines
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|
*
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|
* @{
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|
*/
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#define BCM2836_MAILBOX_0_WRITE_SET_BASE 0x40000080
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#define BCM2836_MAILBOX_1_WRITE_SET_BASE 0x40000084
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#define BCM2836_MAILBOX_2_WRITE_SET_BASE 0x40000088
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#define BCM2836_MAILBOX_3_WRITE_SET_BASE 0x4000008C
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#define BCM2836_MAILBOX_0_READ_CLEAR_BASE 0x400000C0
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#define BCM2836_MAILBOX_1_READ_CLEAR_BASE 0x400000C4
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#define BCM2836_MAILBOX_2_READ_CLEAR_BASE 0x400000C8
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#define BCM2836_MAILBOX_3_READ_CLEAR_BASE 0x400000CC
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|
|
/** @} */
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|
|
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/**
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|
* @name Raspberry Pi 2 Core Timer
|
|
*
|
|
* @{
|
|
*/
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|
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#define BCM2836_CORE_TIMER_CTRL 0x40000000
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#define BCM2836_CORE_TIMER_CTRL_APB_CLK 0x00000100
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#define BCM2836_CORE_TIMER_CTRL_INC_2 0x00000200
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#define BCM2836_CORE_TIMER_PRESCALER 0x40000008
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|
|
#define BCM2836_CORE_TIMER_LS32 0x4000001C
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|
#define BCM2836_CORE_TIMER_MS32 0x40000020
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|
|
|
/** @} */
|
|
|
|
/**
|
|
* @name Raspberry Pi 2 Local Timer
|
|
*
|
|
* @{
|
|
*/
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|
|
|
#define BCM2836_LOCAL_TIMER_CTRL 0x40000034
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|
#define BCM2836_LOCAL_TIMER_CTRL_IRQ_FLAG 0x80000000
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|
#define BCM2836_LOCAL_TIMER_CTRL_IRQ_EN 0x20000000
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|
#define BCM2836_LOCAL_TIMER_CTRL_TIMER_EN 0x10000000
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|
#define BCM2836_LOCAL_TIMER_RELOAD 0x0FFFFFFF
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|
|
|
#define BCM2836_LOCAL_TIMER_IRQ_RELOAD 0x40000038
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|
|
|
#define BCM2836_LOCAL_TIMER_IRQ_CLEAR 0x80000000
|
|
#define BCM2836_LOCAL_TIMER_RELOAD_NOW 0x40000000
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|
|
|
#define BCM2836_LOCAL_TIMER_IRQ_ROUTING 0x40000024
|
|
#define BCM2836_LOCAL_TIMER_ROU_CORE0_IRQ 0x00
|
|
#define BCM2836_LOCAL_TIMER_ROU_CORE1_IRQ 0x01
|
|
#define BCM2836_LOCAL_TIMER_ROU_CORE2_IRQ 0x02
|
|
#define BCM2836_LOCAL_TIMER_ROU_CORE3_IRQ 0x03
|
|
#define BCM2836_LOCAL_TIMER_ROU_CORE0_FIQ 0x04
|
|
#define BCM2836_LOCAL_TIMER_ROU_CORE1_FIQ 0x05
|
|
#define BCM2836_LOCAL_TIMER_ROU_CORE2_FIQ 0x06
|
|
#define BCM2836_LOCAL_TIMER_ROU_CORE3_FIQ 0x07
|
|
|
|
/** @} */
|
|
|
|
/**
|
|
* @name Raspberry Pi 2 IRQ Routing
|
|
*
|
|
* @{
|
|
*/
|
|
|
|
#define BCM2836_GPU_IRQ_ROUTING 0x4000000C
|
|
|
|
#define BCM2836_GPU_IRQ_ROU_GPU_IRQ_CORE0 0x00000000
|
|
#define BCM2836_GPU_IRQ_ROU_GPU_IRQ_CORE1 0x00000001
|
|
#define BCM2836_GPU_IRQ_ROU_GPU_IRQ_CORE2 0x00000002
|
|
#define BCM2836_GPU_IRQ_ROU_GPU_IRQ_CORE4 0x00000003
|
|
|
|
#define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE0 0x00000000
|
|
#define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE1 0x00000004
|
|
#define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE2 0x00000008
|
|
#define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE4 0x0000000C
|
|
|
|
#define BCM2836_GPU_IRQ_ROU_GPU_FIQ_CORE4 0x0000000C
|
|
|
|
|
|
/** @} */
|
|
|
|
/**
|
|
* @name Raspberry Pi 2 Interrupt Register Defines
|
|
*
|
|
* @{
|
|
*/
|
|
|
|
/* Timers interrupt control registers */
|
|
#define BCM2836_CORE0_TIMER_IRQ_CTRL_BASE 0x40000040
|
|
#define BCM2836_CORE1_TIMER_IRQ_CTRL_BASE 0x40000044
|
|
#define BCM2836_CORE2_TIMER_IRQ_CTRL_BASE 0x40000048
|
|
#define BCM2836_CORE3_TIMER_IRQ_CTRL_BASE 0x4000004C
|
|
|
|
#define BCM2836_CORE_TIMER_IRQ_CTRL(cpuidx) \
|
|
(BCM2836_CORE0_TIMER_IRQ_CTRL_BASE + 0x4 * (cpuidx))
|
|
|
|
/*
|
|
* Where to route timer interrupt to, IRQ/FIQ
|
|
* Setting both the IRQ and FIQ bit gives an FIQ
|
|
*/
|
|
#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER0_IRQ 0x01
|
|
#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER1_IRQ 0x02
|
|
#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER2_IRQ 0x04
|
|
#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER3_IRQ 0x08
|
|
#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER0_FIQ 0x10
|
|
#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER1_FIQ 0x20
|
|
#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER2_FIQ 0x40
|
|
#define BCM2836_CORE_TIMER_IRQ_CTRL_TIMER3_FIQ 0x80
|
|
|
|
/* CPU mailbox registers */
|
|
#define BCM2836_MAILBOX_IRQ_CTRL_BASE 0x40000050
|
|
#define BCM2836_MAILBOX_IRQ_CTRL(cpuidx) \
|
|
(BCM2836_MAILBOX_IRQ_CTRL_BASE + 0x4 * (cpuidx))
|
|
/*
|
|
* Where to route mailbox interrupt to, IRQ/FIQ
|
|
* Setting both the IRQ and FIQ bit gives an FIQ
|
|
*/
|
|
#define BCM2836_MAILBOX_IRQ_CTRL_MBOX0_IRQ 0x01
|
|
#define BCM2836_MAILBOX_IRQ_CTRL_MBOX1_IRQ 0x02
|
|
#define BCM2836_MAILBOX_IRQ_CTRL_MBOX2_IRQ 0x04
|
|
#define BCM2836_MAILBOX_IRQ_CTRL_MBOX3_IRQ 0x08
|
|
#define BCM2836_MAILBOX_IRQ_CTRL_MBOX0_FIQ 0x10
|
|
#define BCM2836_MAILBOX_IRQ_CTRL_MBOX1_FIQ 0x20
|
|
#define BCM2836_MAILBOX_IRQ_CTRL_MBOX2_FIQ 0x40
|
|
#define BCM2836_MAILBOX_IRQ_CTRL_MBOX3_FIQ 0x80
|
|
|
|
#define BCM2836_IRQ_SOURCE_REG_BASE 0x40000060
|
|
#define BCM2836_IRQ_SOURCE_REG(cpuidx) \
|
|
(BCM2836_IRQ_SOURCE_REG_BASE + 0x4 * (cpuidx))
|
|
|
|
#define BCM2836_FIQ_SOURCE_REG_BASE 0x40000070
|
|
#define BCM2836_FIQ_SOURCE_REG(cpuidx) \
|
|
(BCM2836_FIQ_SOURCE_REG_BASE + 0x4 * (cpuidx))
|
|
|
|
#define BCM2836_IRQ_SOURCE_TIMER0 0x00000001
|
|
#define BCM2836_IRQ_SOURCE_TIMER1 0x00000002
|
|
#define BCM2836_IRQ_SOURCE_TIMER2 0x00000004
|
|
#define BCM2836_IRQ_SOURCE_TIMER3 0x00000008
|
|
#define BCM2836_IRQ_SOURCE_MBOX0 0x00000010
|
|
#define BCM2836_IRQ_SOURCE_MBOX1 0x00000020
|
|
#define BCM2836_IRQ_SOURCE_MBOX2 0x00000040
|
|
#define BCM2836_IRQ_SOURCE_MBOX3 0x00000080
|
|
#define BCM2836_IRQ_SOURCE_GPU 0x00000100
|
|
#define BCM2836_IRQ_SOURCE_PMU 0x00000200
|
|
#define BCM2836_IRQ_SOURCE_LOCAL_TIMER 0x00000800
|
|
|
|
/** @} */
|
|
|
|
#endif /* LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H */
|