forked from Imagelibrary/rtems
159 lines
5.5 KiB
C
159 lines
5.5 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* @ingroup A9MPCoreSupport
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*
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* @brief This header file provides the interfaces of the @ref A9MPCoreSupport.
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*/
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/*
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* Copyright (c) 2013 embedded brains GmbH & Co. KG
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H
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#define LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H
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#include <bsp/utility.h>
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/**
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* @defgroup A9MPCoreSupport Cortex-A9 MPCore Support
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*
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* @ingroup RTEMSBSPsARMShared
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*
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* @brief This group contains support interfaces for the Cortex-A9 MPCore.
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*
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* @{
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*/
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typedef struct {
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uint32_t ctrl;
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#define A9MPCORE_SCU_CTRL_SCU_EN BSP_BIT32(0)
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#define A9MPCORE_SCU_CTRL_ADDR_FLT_EN BSP_BIT32(1)
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#define A9MPCORE_SCU_CTRL_RAM_PAR_EN BSP_BIT32(2)
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#define A9MPCORE_SCU_CTRL_SCU_SPEC_LINE_FILL_EN BSP_BIT32(3)
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#define A9MPCORE_SCU_CTRL_FORCE_PORT_0_EN BSP_BIT32(4)
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#define A9MPCORE_SCU_CTRL_SCU_STANDBY_EN BSP_BIT32(5)
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#define A9MPCORE_SCU_CTRL_IC_STANDBY_EN BSP_BIT32(6)
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uint32_t cfg;
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#define A9MPCORE_SCU_CFG_CPU_COUNT(val) BSP_FLD32(val, 0, 1)
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#define A9MPCORE_SCU_CFG_CPU_COUNT_GET(reg) BSP_FLD32GET(reg, 0, 1)
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#define A9MPCORE_SCU_CFG_CPU_COUNT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1)
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#define A9MPCORE_SCU_CFG_SMP_MODE(val) BSP_FLD32(val, 4, 7)
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#define A9MPCORE_SCU_CFG_SMP_MODE_GET(reg) BSP_FLD32GET(reg, 4, 7)
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#define A9MPCORE_SCU_CFG_SMP_MODE_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7)
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#define A9MPCORE_SCU_CFG_TAG_RAM_SIZE(val) BSP_FLD32(val, 8, 15)
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#define A9MPCORE_SCU_CFG_TAG_RAM_SIZE_GET(reg) BSP_FLD32GET(reg, 8, 15)
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#define A9MPCORE_SCU_CFG_TAG_RAM_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
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uint32_t pwrst;
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uint32_t invss;
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#define A9MPCORE_SCU_INVSS_CPU0(ways) BSP_FLD32(val, 0, 3)
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#define A9MPCORE_SCU_INVSS_CPU0_GET(reg) /* Write only register */
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#define A9MPCORE_SCU_INVSS_CPU0_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
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#define A9MPCORE_SCU_INVSS_CPU1(ways) BSP_FLD32(val, 4, 7)
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#define A9MPCORE_SCU_INVSS_CPU1_GET(reg) /* Write only register */
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#define A9MPCORE_SCU_INVSS_CPU1_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7)
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#define A9MPCORE_SCU_INVSS_CPU2(ways) BSP_FLD32(val, 8, 11)
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#define A9MPCORE_SCU_INVSS_CPU2_GET(reg) /* Write only register */
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#define A9MPCORE_SCU_INVSS_CPU2_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11)
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#define A9MPCORE_SCU_INVSS_CPU3(ways) BSP_FLD32(val, 12, 15)
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#define A9MPCORE_SCU_INVSS_CPU3_GET(reg) /* Write only register */
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#define A9MPCORE_SCU_INVSS_CPU3_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15)
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uint32_t reserved_09[8];
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uint32_t diagn_ctrl;
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#define A9MPCORE_SCU_DIAGN_CTRL_MIGRATORY_BIT_DISABLE BSP_BIT32(0)
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uint32_t reserved_10[3];
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uint32_t fltstart;
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uint32_t fltend;
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uint32_t reserved_48[2];
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uint32_t sac;
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uint32_t snsac;
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} a9mpcore_scu;
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typedef struct {
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} a9mpcore_gic;
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typedef struct {
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uint32_t cntrlower;
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uint32_t cntrupper;
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#define A9MPCORE_GT_CTRL_PRESCALER(val) BSP_FLD32(val, 8, 15)
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#define A9MPCORE_GT_CTRL_PRESCALER_GET(reg) BSP_FLD32GET(reg, 8, 15)
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#define A9MPCORE_GT_CTRL_PRESCALER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
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#define A9MPCORE_GT_CTRL_AUTOINC_EN BSP_BIT32(3)
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#define A9MPCORE_GT_CTRL_IRQ_EN BSP_BIT32(2)
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#define A9MPCORE_GT_CTRL_COMP_EN BSP_BIT32(1)
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#define A9MPCORE_GT_CTRL_TMR_EN BSP_BIT32(0)
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uint32_t ctrl;
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#define A9MPCORE_GT_IRQST_EFLG BSP_BIT32(0)
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uint32_t irqst;
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uint32_t cmpvallower;
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uint32_t cmpvalupper;
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uint32_t autoinc;
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} a9mpcore_gt;
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typedef struct {
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uint32_t load;
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uint32_t cntr;
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uint32_t ctrl;
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#define A9MPCORE_PT_CTRL_PRESCALER(val) BSP_FLD32(val, 8, 15)
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#define A9MPCORE_PT_CTRL_PRESCALER_GET(reg) BSP_FLD32GET(reg, 8, 15)
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#define A9MPCORE_PT_CTRL_PRESCALER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
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#define A9MPCORE_PT_CTRL_IRQ_EN BSP_BIT32(2)
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#define A9MPCORE_PT_CTRL_AUTO_RLD BSP_BIT32(1)
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#define A9MPCORE_PT_CTRL_TMR_EN BSP_BIT32(0)
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uint32_t irqst;
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#define A9MPCORE_PT_IRQST_EFLG BSP_BIT32(0)
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} a9mpcore_pt;
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typedef struct {
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uint32_t load;
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uint32_t cntr;
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uint32_t ctrl;
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uint32_t irqst;
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uint32_t rstst;
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uint32_t dis;
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} a9mpcore_pw;
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typedef struct {
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} a9mpcore_idist;
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typedef struct {
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a9mpcore_scu scu;
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uint32_t reserved_58[42];
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a9mpcore_gic gic;
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uint32_t reserved_100[64];
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a9mpcore_gt gt;
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uint32_t reserved_21c[249];
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a9mpcore_pt pt;
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uint32_t reserved_610[4];
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a9mpcore_pw pw;
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uint32_t reserved_638[626];
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a9mpcore_idist idist;
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} a9mpcore;
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/** @} */
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#endif /* LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H */
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