forked from Imagelibrary/rtems
9384ac2d65
This patch changes the license to BSD-2 for all source files where the copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research. Some files also includes copyright right statements from OAR and/or embedded Brains in addition to Gaisler. Updates #3053.
285 lines
9.8 KiB
C
285 lines
9.8 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* @brief PCI Access Methods
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*
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* Routines to access PCI memory/configuration space and other PCI related
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* functions the PCI Library provides.
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*/
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/*
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* COPYRIGHT (c) 2010 Cobham Gaisler AB.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __PCI_ACCESS_H__
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#define __PCI_ACCESS_H__
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#include <stdint.h>
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#include <libcpu/byteorder.h>
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#include <rtems/score/basedefs.h>
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#include <pci.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Identification of a PCI configuration space device (16-bit) */
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typedef uint16_t pci_dev_t;
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/* Create a PCI Configuration Space ID */
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#define PCI_DEV(bus, slot, func) (((bus)<<8) | ((slot)<<3) | (func))
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/* Get Bus of a PCI Configuration Space ID */
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#define PCI_DEV_BUS(dev) (((dev) >> 8) & 0xff)
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/* Get Slot/Device of a PCI Configuration Space ID */
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#define PCI_DEV_SLOT(dev) (((dev) >> 3) & 0x1f)
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/* Get Function of a PCI Configuration Space ID */
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#define PCI_DEV_FUNC(dev) ((dev) & 0x7)
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/* Get Device and Function of a PCI Configuration Space ID */
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#define PCI_DEV_DEVFUNC(dev) ((dev) & 0xff)
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/* Expand Device into argument lists */
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#define PCI_DEV_EXPAND(dev) PCI_DEV_BUS((dev)), PCI_DEV_SLOT((dev)), PCI_DEV_FUNC((dev))
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/* Configuration Space Read/Write Operations */
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struct pci_cfg_ops {
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/* Configuration Space Access and Setup Routines */
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int (*read8)(pci_dev_t dev, int ofs, uint8_t *data);
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int (*read16)(pci_dev_t dev, int ofs, uint16_t *data);
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int (*read32)(pci_dev_t dev, int ofs, uint32_t *data);
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int (*write8)(pci_dev_t dev, int ofs, uint8_t data);
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int (*write16)(pci_dev_t dev, int ofs, uint16_t data);
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int (*write32)(pci_dev_t dev, int ofs, uint32_t data);
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};
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/* Read a register over PCI I/O Space, and swap it if necessary (due to
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* PCI endianness)
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*/
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struct pci_io_ops {
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uint8_t (*read8)(uint8_t *adr);
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uint16_t(*read16)(uint16_t *adr);
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uint32_t (*read32)(uint32_t *adr);
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void (*write8)(uint8_t *adr, uint8_t data);
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void (*write16)(uint16_t *adr, uint16_t data);
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void (*write32)(uint32_t *adr, uint32_t data);
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};
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/* Read a register over PCI Memory Space (non-prefetchable memory), and
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* swap it if necessary (due to PCI endianness)
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*/
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struct pci_memreg_ops {
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uint8_t (*ld8)(uint8_t *adr);
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void (*st8)(uint8_t *adr, uint8_t data);
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uint16_t(*ld_le16)(uint16_t *adr);
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void (*st_le16)(uint16_t *adr, uint16_t data);
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uint16_t(*ld_be16)(uint16_t *adr);
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void (*st_be16)(uint16_t *adr, uint16_t data);
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uint32_t (*ld_le32)(uint32_t *adr);
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void (*st_le32)(uint32_t *adr, uint32_t data);
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uint32_t (*ld_be32)(uint32_t *adr);
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void (*st_be32)(uint32_t *adr, uint32_t data);
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};
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typedef uint8_t (*pci_ld8_t)(uint8_t *adr);
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typedef void (*pci_st8_t)(uint8_t *adr, uint8_t data);
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typedef uint16_t(pci_ld16_t)(uint16_t *adr);
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typedef void (*pci_st16_t)(uint16_t *adr, uint16_t data);
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typedef uint32_t (*pci_ld32_t)(uint32_t *adr);
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typedef void (*pci_st32_t)(uint32_t *adr, uint32_t data);
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struct pci_access_drv {
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/* Configuration */
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struct pci_cfg_ops cfg;
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/* I/O Access operations */
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struct pci_io_ops io;
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/* Registers over Memory Access operations. Note that these funcs
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* are only for code that need to be compatible with both Big-Endian
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* and Little-Endian PCI bus or for some other reason need function
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* pointers to access functions. Normally drivers use the inline
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* functions for Registers-over-Memory access to avoid extra function
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* call.
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*/
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struct pci_memreg_ops *memreg;
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/* Translate from PCI address to CPU address (dir=0). Translate
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* CPU address to PCI address (dir!=0). The address will can be
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* used to perform I/O access or memory access by CPU or PCI DMA
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* peripheral.
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*
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* address In/Out. CPU address or PCI address.
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* type Access type. 1=I/O, 2=MEMIO, 3=MEM
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* dir Translate direction. 0=PCI-to-CPU, 0!=CPU-to-PCI,
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*
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* Return Value
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* 0 = Success
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* -1 = Requested Address not mapped into other address space
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* i.e. not accessible
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*/
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int (*translate)(uint32_t *address, int type, int dir);
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};
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/* Access Routines valid after a PCI-Access-Driver has registered */
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extern struct pci_access_drv pci_access_ops;
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/* Register PCI Access Driver */
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extern int pci_access_drv_register(struct pci_access_drv *drv);
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/* Set/unset bits in command and status register of a PCI device */
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extern void pci_modify_cmdsts(pci_dev_t dev, uint32_t mask, uint32_t val);
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/* Enable Memory in command register */
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static inline void pci_mem_enable(pci_dev_t dev)
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{
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pci_modify_cmdsts(dev, PCIM_CMD_MEMEN, PCIM_CMD_MEMEN);
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}
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static inline void pci_mem_disable(pci_dev_t dev)
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{
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pci_modify_cmdsts(dev, PCIM_CMD_MEMEN, 0);
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}
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static inline void pci_io_enable(pci_dev_t dev)
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{
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pci_modify_cmdsts(dev, PCIM_CMD_PORTEN, PCIM_CMD_PORTEN);
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}
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static inline void pci_io_disable(pci_dev_t dev)
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{
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pci_modify_cmdsts(dev, PCIM_CMD_PORTEN, 0);
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}
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static inline void pci_master_enable(pci_dev_t dev)
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{
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pci_modify_cmdsts(dev, PCIM_CMD_BUSMASTEREN, PCIM_CMD_BUSMASTEREN);
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}
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static inline void pci_master_disable(pci_dev_t dev)
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{
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pci_modify_cmdsts(dev, PCIM_CMD_BUSMASTEREN, 0);
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}
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/* Configuration Space Access Read Routines */
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extern int pci_cfg_r8(pci_dev_t dev, int ofs, uint8_t *data);
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extern int pci_cfg_r16(pci_dev_t dev, int ofs, uint16_t *data);
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extern int pci_cfg_r32(pci_dev_t dev, int ofs, uint32_t *data);
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/* Configuration Space Access Write Routines */
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extern int pci_cfg_w8(pci_dev_t dev, int ofs, uint8_t data);
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extern int pci_cfg_w16(pci_dev_t dev, int ofs, uint16_t data);
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extern int pci_cfg_w32(pci_dev_t dev, int ofs, uint32_t data);
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/* Read a register over PCI I/O Space */
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extern uint8_t pci_io_r8(uint32_t adr);
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extern uint16_t pci_io_r16(uint32_t adr);
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extern uint32_t pci_io_r32(uint32_t adr);
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/* Write a register over PCI I/O Space */
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extern void pci_io_w8(uint32_t adr, uint8_t data);
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extern void pci_io_w16(uint32_t adr, uint16_t data);
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extern void pci_io_w32(uint32_t adr, uint32_t data);
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/* Translate PCI address into CPU accessible address */
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static inline int pci_pci2cpu(uint32_t *address, int type)
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{
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return pci_access_ops.translate(address, type, 0);
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}
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/* Translate CPU accessible address into PCI address (for DMA) */
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static inline int pci_cpu2pci(uint32_t *address, int type)
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{
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return pci_access_ops.translate(address, type, 1);
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}
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/*** Read/Write a register over PCI Memory Space ***/
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static inline uint8_t pci_ld8(volatile uint8_t *addr)
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{
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return *addr;
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}
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static inline void pci_st8(volatile uint8_t *addr, uint8_t val)
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{
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*addr = val;
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}
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/* Registers-over-Memory Space access routines. The routines are not inlined
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* so it is possible during run-time to select which function implemention
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* to use. The use of these functions are not recommended since it will have a
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* performance penalty.
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*
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* 8-bit accesses are the same for Little and Big endian PCI buses.
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*/
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uint8_t pci_mem_ld8(uint8_t *adr);
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void pci_mem_st8(uint8_t *adr, uint8_t data);
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/* Registers-over-Memory Space - Generic Big endian PCI bus definitions */
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uint16_t pci_mem_be_ld_le16(uint16_t *adr);
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uint16_t pci_mem_be_ld_be16(uint16_t *adr);
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uint32_t pci_mem_be_ld_le32(uint32_t *adr);
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uint32_t pci_mem_be_ld_be32(uint32_t *adr);
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void pci_mem_be_st_le16(uint16_t *adr, uint16_t data);
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void pci_mem_be_st_be16(uint16_t *adr, uint16_t data);
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void pci_mem_be_st_le32(uint32_t *adr, uint32_t data);
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void pci_mem_be_st_be32(uint32_t *adr, uint32_t data);
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/* Registers-over-Memory Space - Generic Little endian PCI bus definitions */
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uint16_t pci_mem_le_ld_le16(uint16_t *adr);
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uint16_t pci_mem_le_ld_be16(uint16_t *adr);
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uint32_t pci_mem_le_ld_le32(uint32_t *adr);
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uint32_t pci_mem_le_ld_be32(uint32_t *adr);
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void pci_mem_le_st_le16(uint16_t *adr, uint16_t data);
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void pci_mem_le_st_be16(uint16_t *adr, uint16_t data);
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void pci_mem_le_st_le32(uint32_t *adr, uint32_t data);
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void pci_mem_le_st_be32(uint32_t *adr, uint32_t data);
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/* Get Read/Write function for accessing a register over PCI Memory Space
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* (non-inline functions).
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*
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* Arguments
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* wr 0(Read), 1(Write)
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* size 1(Byte), 2(Word), 4(Double Word)
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* func Where function pointer will be stored
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* endian PCI_LITTLE_ENDIAN or PCI_BIG_ENDIAN
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* type 1(I/O), 3(REG over MEM), 4(CFG)
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*
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* Return
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* 0 Found function
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* others No such function defined by host driver or BSP
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*/
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extern int pci_access_func(int wr, int size, void **func, int endian, int type);
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/* Predefined functions for Host drivers or BSPs that define the
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* register-over-memory space functions operations.
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*/
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extern struct pci_memreg_ops pci_mem_le_ops; /* For Little-Endian PCI bus */
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extern struct pci_memreg_ops pci_mem_be_ops; /* For Big-Endian PCI bus */
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#ifdef __cplusplus
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}
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#endif
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#endif /* !__PCI_ACCESS_H__ */
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