forked from Imagelibrary/rtems
106 lines
4.1 KiB
C
106 lines
4.1 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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* Copyright (c) 2016-2017 Chris Johns <chrisj@rtems.org> All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Xilinx AXI IIC Interface v2.0. See PG090.pdf.
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*
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* Note, only master support is provided and no dynamic mode by design.
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*
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* The clock set up is to be handled by the IP integrator. There are too many
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* factors handling this in software.
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*/
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#ifndef XILINX_AXI_I2C_H
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#define XILINX_AXI_I2C_H
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#include <dev/i2c/i2c.h>
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/*
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* The PL integrator controls the timing. This interface allows software to
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* override those settings. It pays to check the timing with ChipScope.
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*
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* If you set the AXI bus frequency you can use the clock speed ioctl call to
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* change the speed dymanically. The ioctl call overrides the defaults passed
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* in.
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*
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* Set the valid mask to the values that are to be set.
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*/
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#define XILINX_AIX_I2C_AXI_CLOCK (1 << 0)
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#define XILINX_AIX_I2C_TSUSTA (1 << 1)
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#define XILINX_AIX_I2C_TSUSTO (1 << 2)
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#define XILINX_AIX_I2C_THDSTA (1 << 3)
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#define XILINX_AIX_I2C_TSUDAT (1 << 4)
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#define XILINX_AIX_I2C_TBUF (1 << 5)
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#define XILINX_AIX_I2C_THIGH (1 << 6)
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#define XILINX_AIX_I2C_TLOW (1 << 7)
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#define XILINX_AIX_I2C_THDDAT (1 << 8)
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#define XILINX_AIX_I2C_ALL_REGS (XILINX_AIX_I2C_TSUSTA | \
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XILINX_AIX_I2C_TSUSTO | \
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XILINX_AIX_I2C_THDSTA | \
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XILINX_AIX_I2C_TSUDAT | \
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XILINX_AIX_I2C_TBUF | \
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XILINX_AIX_I2C_THIGH | \
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XILINX_AIX_I2C_TLOW | \
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XILINX_AIX_I2C_THDDAT)
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typedef struct
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{
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uint32_t valid_mask;
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uint32_t AXI_CLOCK;
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uint32_t SCL_INERTIAL_DELAY;
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uint32_t TSUSTA;
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uint32_t TSUSTO;
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uint32_t THDSTA;
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uint32_t TSUDAT;
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uint32_t TBUF;
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uint32_t THIGH;
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uint32_t TLOW;
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uint32_t THDDAT;
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} xilinx_aix_i2c_timing;
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/*
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* Register the driver.
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*
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* The driver can multipex a number of I2C buses (in master mode only) using
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* the GPO port. The PL designer can use the output pins to select a bus. This
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* is useful if connecting a number of slave devices that have limit selectable
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* addresses.
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*
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* @param bus_path The driver's device path.
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* @param register_base AXI base address.
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* @param irq AXI FPGA interrupt.
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* @param gpio_address Bits 12:15 of a slave address it written to the GPO.
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* @param timing Override the default timing. NULL means no changes.
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*/
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int i2c_bus_register_xilinx_aix_i2c(const char* bus_path,
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uintptr_t register_base,
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rtems_vector_number irq,
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bool ten_gpio,
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const xilinx_aix_i2c_timing* timing);
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#endif
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