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4 Commits
5.3 ... 5

Author SHA1 Message Date
Jan Sommer
616545350f cpukit/termios: Fix ordering of baud rate table
rtems_termios_set_best_baud expects a sorted baud rate table.

Fixes #5220
2025-02-20 22:08:51 +00:00
Jan Sommer
13cbd83444 grlib/occan: Fix baud rate calculation
Fixes #5219
2025-02-20 11:24:30 +01:00
Amar Takhar
ef6e6e3087 gitlab: Add link to CI
This runs only the commit message and merge request checker.

Required so we can have 'all pipelines must pass' enabled due to a bug in
Gitlab
2025-02-12 22:22:35 -05:00
Reinking, Janosch
7b40317e76 bsps/shared: NS16550 driver updates the line control register during operation
Fixes: #5179
2025-01-23 15:30:28 +01:00
5 changed files with 13 additions and 6 deletions

4
.gitlab/gitlab-ci.yml Normal file
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@@ -0,0 +1,4 @@
include:
- project: 'administration/integration'
file:
- 'ci/config/rtems.yml'

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@@ -590,7 +590,7 @@ int ns16550_set_attributes(
* turn into the LSB and MSB divisor latch registers.
*/
(*setReg)(pNS16550, NS16550_LINE_CONTROL, SP_LINE_DLAB);
(*setReg)(pNS16550, NS16550_LINE_CONTROL, SP_LINE_DLAB | ucLineControl);
(*setReg)(pNS16550, NS16550_TRANSMIT_BUFFER, ulBaudDivisor&0xff);
(*setReg)(pNS16550, NS16550_INTERRUPT_ENABLE, (ulBaudDivisor>>8)&0xff);

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@@ -62,7 +62,8 @@ int grlib_canbtrs_calc_timing(
tseg++) {
/* calculate scaler */
tmp = ((br->divfactor + tseg) * baud);
sc = (core_hz * 2)/ tmp - core_hz / tmp;
/* Core frequency is always divided by 2 before scaler */
sc = core_hz / (2 * tmp);
if (sc <= 0 || sc > br->max_scaler)
continue;
if (br->has_bpr &&
@@ -71,7 +72,7 @@ int grlib_canbtrs_calc_timing(
((sc > 256 * 4) && (sc <= 256 * 8) && (sc & 0x7))))
continue;
error = baud - core_hz / (sc * (br->divfactor + tseg));
error = baud - core_hz / (2 * sc * (br->divfactor + tseg));
#ifdef GRLIB_CANBTRS_DEBUG
printf(" baud=%d, tseg=%d, sc=%d, error=%d\n",
baud, tseg, sc, error);

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@@ -1000,7 +1000,9 @@ static void convert_timing_to_btrs(
{
btrs->btr0 = (t->rsj << OCCAN_BUSTIM_SJW_BIT) |
(t->scaler & OCCAN_BUSTIM_BRP);
btrs->btr1 = (0<<7) | (t->ps2 << OCCAN_BUSTIM_TSEG2_BIT) | t->ps1;
/* Core adds +1 to the register values, so compensate here by decrementing */
btrs->btr1 = (0<<7) | ((t->ps2-1) << OCCAN_BUSTIM_TSEG2_BIT) | (t->ps1-1);
}
static int occan_set_speedregs(occan_priv *priv, occan_speed_regs *timing)

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@@ -34,11 +34,11 @@ const rtems_assoc_t rtems_termios_baud_table [] = {
{ "B1800", 1800, B1800 },
{ "B2400", 2400, B2400 },
{ "B4800", 4800, B4800 },
{ "B7200", 7200, B7200 },
{ "B9600", 9600, B9600 },
{ "B14400", 14400, B14400 },
{ "B19200", 19200, B19200 },
{ "B38400", 38400, B38400 },
{ "B7200", 7200, B7200 },
{ "B14400", 14400, B14400 },
{ "B28800", 28800, B28800 },
{ "B57600", 57600, B57600 },
{ "B76800", 76800, B76800 },