This commit was manufactured by cvs2svn to create tag 'rtems-4-9-2'.

Sprout from rtems-4-9-branch 2009-03-12 17:03:39 UTC Joel Sherrill <joel.sherrill@OARcorp.com> 'Upgrade to 4.9.2' Cherrypick from rtems-4-9-branch 2009-09-15 05:32:51 UTC cvs2git <rtems-devel@rtems.org> 'This commit was manufactured by cvs2svn to create branch 'rtems-4-9-branch'.': c/src/lib/libbsp/arm/gba/console/defaultfont.h c/src/lib/libbsp/arm/smdk2410/include/.cvsignore c/src/lib/libbsp/bare/preinstall.am c/src/lib/libbsp/m68k/genmcf548x/include/.cvsignore c/src/lib/libbsp/m68k/mcf52235/include/.cvsignore c/src/lib/libbsp/m68k/mcf5329/include/.cvsignore c/src/lib/libbsp/mips/csb350/start/regs.h c/src/lib/libbsp/mips/genmongoosev/start/regs.h c/src/lib/libbsp/mips/hurricane/liblnk/regs.h c/src/lib/libbsp/mips/jmr3904/start/regs.h c/src/lib/libbsp/mips/rbtx4925/liblnk/regs.h c/src/lib/libbsp/mips/rbtx4938/liblnk/regs.h c/src/lib/libbsp/powerpc/mvme3100/include/.cvsignore c/src/lib/libbsp/powerpc/virtex/include/.cvsignore
2009-09-15 05:32:54 +00:00
241 changed files with 3640 additions and 29117 deletions
--- a/2
+++ b/2
@@ -4,4 +4,4 @@
 #  $Id$
 #

-RTEMS Version 4.9.3
+RTEMS Version 4.9.2
--- a/aclocal/version.m4
+++ b/aclocal/version.m4
@@ -1,4 +1,4 @@
 AC_DEFUN([RTEMS_VERSIONING],
-m4_define([_RTEMS_VERSION],[4.9.3]))
+m4_define([_RTEMS_VERSION],[4.9.2]))

 m4_define([RTEMS_API],[4.9])
--- a/c/src/aclocal/version.m4
+++ b/c/src/aclocal/version.m4
@@ -1,4 +1,4 @@
 AC_DEFUN([RTEMS_VERSIONING],
-m4_define([_RTEMS_VERSION],[4.9.3]))
+m4_define([_RTEMS_VERSION],[4.9.2]))

 m4_define([RTEMS_API],[4.9])
--- a/c/src/lib/libbsp/i386/ChangeLog
+++ b/c/src/lib/libbsp/i386/ChangeLog
@@ -1,8 +1,3 @@
-2009-05-18	Joel Sherrill <joel.sherrill@OARcorp.com>
-
-	* shared/irq/irq.c, shared/irq/irq.h, shared/irq/irq_asm.S: Add shared
-	interrupt support to i386.
-
 2009-03-12	Joel Sherrill <joel.sherrill@OARcorp.com>

 	PR 1385/cpukit
--- a/c/src/lib/libbsp/i386/pc386/ChangeLog
+++ b/c/src/lib/libbsp/i386/pc386/ChangeLog
@@ -1,10 +1,3 @@
-2009-09-15	Till Straumann <strauman@slac.stanford.edu>
-
-	PR 1344/bsps:
-	* clock/ckinit.c: Fix more bugs (applied PR1344/attachment 702):
-	TSC handler was used when 8254 was requested and vice versa.
-	Also, nanosecond handler was never installed to RTEMS clock.
-
 2008-12-08	Ralf Corsépius <ralf.corsepius@rtems.org>

 	* bsp_specs: Backport from CVS-HEAD.
--- a/c/src/lib/libbsp/i386/pc386/clock/ckinit.c
+++ b/c/src/lib/libbsp/i386/pc386/clock/ckinit.c
@@ -285,27 +285,19 @@ void Clock_driver_support_initialize_hardware(void)
    /* printk( "Use 8254\n" ); */
    Clock_driver_support_at_tick = Clock_driver_support_at_tick_empty;
    Clock_driver_nanoseconds_since_last_tick = 
-      bsp_clock_nanoseconds_since_last_tick_i8254;
+      bsp_clock_nanoseconds_since_last_tick_tsc;
+
  } else {
    /* printk( "Use TSC\n" ); */
    Clock_driver_support_at_tick = Clock_driver_support_at_tick_tsc;
    Clock_driver_nanoseconds_since_last_tick = 
-      bsp_clock_nanoseconds_since_last_tick_tsc;
+      bsp_clock_nanoseconds_since_last_tick_i8254;
  }

-  /* Shell installs nanosecond handler before calling
-   * Clock_driver_support_initialize_hardware() :-(
-   * so we do it again now that we're ready.
-   */
-  rtems_clock_set_nanoseconds_extension(
-    Clock_driver_nanoseconds_since_last_tick
-  );
-
  if (!BSP_install_rtems_irq_handler (&clockIrqData)) {
    printk("Unable to initialize system clock\n");
    rtems_fatal_error_occurred(1);
  }
-
 }

 #define Clock_driver_support_shutdown_hardware() \
--- a/c/src/lib/libbsp/i386/shared/irq/irq.c
+++ b/c/src/lib/libbsp/i386/shared/irq/irq.c
@@ -2,7 +2,7 @@
 *
 *  This file contains the implementation of the function described in irq.h
 *
- *  Copyright (C) 1998 valette@crf.canon.fr
+ *  CopyRight (C) 1998 valette@crf.canon.fr
 *
 *  The license and distribution terms for this file may be
 *  found in found in the file LICENSE in this distribution or at
@@ -195,63 +195,7 @@ static int isValidInterrupt(int irq)
 }

 /*
- * ------------------- RTEMS Shared Irq Handler Mngt Routines ------------
- */
-int BSP_install_rtems_shared_irq_handler  (const rtems_irq_connect_data* irq)
-{
-  rtems_interrupt_level   level;
-  rtems_irq_connect_data* vchain;
-
-  if (!isValidInterrupt(irq->name)) {
-    printk("Invalid interrupt vector %d\n",irq->name);
-    return 0;
-  }
-
-  rtems_interrupt_disable(level);
-
-  if ( (int)rtems_hdl_tbl[irq->name].next_handler  == -1 ) {
-    rtems_interrupt_enable(level);
-    printk(
-      "IRQ vector %d already connected to an unshared handler\n",
-      irq->name
-    );
-    return 0;
-  }
-
-   vchain = (rtems_irq_connect_data*)malloc(sizeof(rtems_irq_connect_data));
-
-  /* save off topmost handler */
-  vchain[0]= rtems_hdl_tbl[irq->name];
-
-  /*
-   * store the data provided by user
-   */
-  rtems_hdl_tbl[irq->name] = *irq;
-
-  /* link chain to new topmost handler */
-  rtems_hdl_tbl[irq->name].next_handler = (void *)vchain;
-
-  /*
-   * enable_irq_at_pic is supposed to ignore
-   * requests to disable interrupts outside
-   * of the range handled by the PIC
-   */
-  BSP_irq_enable_at_i8259s (irq->name);
-
-  /*
-   * Enable interrupt on device
-   */
-  if (irq->on)
-    irq->on(irq);
-
-  rtems_interrupt_enable(level);
-
-  return 1;
-}
-
-
-/*
- * --------------- RTEMS Single Irq Handler Mngt Routines ---------------
+ * ------------------------ RTEMS Single Irq Handler Mngt Routines ----------------
 */

 int BSP_install_rtems_irq_handler  (const rtems_irq_connect_data* irq)
@@ -278,8 +222,6 @@ int BSP_install_rtems_irq_handler  (const rtems_irq_connect_data* irq)
     * store the data provided by user
     */
    rtems_hdl_tbl[irq->name] = *irq;
-    rtems_hdl_tbl[irq->name].next_handler = (void *)-1;
-
    /*
     * Enable interrupt at PIC level
     */
@@ -287,7 +229,7 @@ int BSP_install_rtems_irq_handler  (const rtems_irq_connect_data* irq)
    /*
     * Enable interrupt on device
     */
-    if (irq->on)
+	if (irq->on)
    	irq->on(irq);

    rtems_interrupt_enable(level);
@@ -310,86 +252,43 @@ int BSP_get_current_rtems_irq_handler	(rtems_irq_connect_data* irq)

 int BSP_remove_rtems_irq_handler  (const rtems_irq_connect_data* irq)
 {
-  rtems_interrupt_level       level;
-  rtems_irq_connect_data *pchain= NULL, *vchain = NULL;
+    rtems_interrupt_level       level;

-  if (!isValidInterrupt(irq->name)) {
-    return 0;
-  }
-
-  /*
-   * Check if default handler is actually connected. If not issue an error.
-   * You must first get the current handler via i386_get_current_idt_entry
-   * and then disconnect it using i386_delete_idt_entry.
-   * RATIONALE : to always have the same transition by forcing the user
-   * to get the previous handler before accepting to disconnect.
-   */
-  rtems_interrupt_disable(level);
-  if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) {
-    rtems_interrupt_enable(level);
-    return 0;
-  }
-
-  if ( (int)rtems_hdl_tbl[irq->name].next_handler != -1 ) {
-    int found = 0;
-
-    for( (pchain= NULL, vchain = &rtems_hdl_tbl[irq->name]);
-         (vchain->hdl != default_rtems_entry.hdl);
-         (pchain= vchain,
-          vchain = (rtems_irq_connect_data*)vchain->next_handler) ) {
-      if ( vchain->hdl == irq->hdl ) {
-        found =  -1;
-        break;
-      }
-    }
-
-    if ( !found ) {
-      rtems_interrupt_enable(level);
+    if (!isValidInterrupt(irq->name)) {
      return 0;
    }
-  } else {
+    /*
+     * Check if default handler is actually connected. If not issue an error.
+     * You must first get the current handler via i386_get_current_idt_entry
+     * and then disconnect it using i386_delete_idt_entry.
+     * RATIONALE : to always have the same transition by forcing the user
+     * to get the previous handler before accepting to disconnect.
+     */
+    rtems_interrupt_disable(level);
    if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) {
      rtems_interrupt_enable(level);
      return 0;
    }
-  }

-  /*
-   * disable interrupt at PIC level
-   */
-  BSP_irq_disable_at_i8259s (irq->name);
+    /*
+     * disable interrupt at PIC level
+     */
+    BSP_irq_disable_at_i8259s (irq->name);

-  /*
-   * Disable interrupt on device
-   */
-  if (irq->off)
-    irq->off(irq);
+    /*
+     * Disable interrupt on device
+     */
+	if (irq->off)
+    	irq->off(irq);

-  /*
-   * restore the default irq value
-   */
-  if( !vchain ) {
-     /* single handler vector... */
-     rtems_hdl_tbl[irq->name] = default_rtems_entry;
-  } else {
-    if ( pchain ) {
-       /* non-first handler being removed */
-       pchain->next_handler = vchain->next_handler;
-    } else {
-       /* first handler isn't malloc'ed, so just overwrite it.  Since
-        * the contents of vchain are being struct copied, vchain itself
-        * goes away
-        */
-       vchain = vchain->next_handler;
-       rtems_hdl_tbl[irq->name]= *vchain;
-    }
-    free(vchain);
-  }
+    /*
+     * restore the default irq value
+     */
+    rtems_hdl_tbl[irq->name] = default_rtems_entry;

+    rtems_interrupt_enable(level);

-  rtems_interrupt_enable(level);
-
-  return 1;
+    return 1;
 }

 /*
@@ -399,7 +298,6 @@ int BSP_remove_rtems_irq_handler  (const rtems_irq_connect_data* irq)
 int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
 {
    int                    i;
-    rtems_irq_connect_data*       vchain;
    rtems_interrupt_level  level;

    /*
@@ -416,16 +314,17 @@ int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
    compute_i8259_masks_from_prio ();

    for (i=0; i < internal_config->irqNb; i++) {
-      BSP_irq_disable_at_i8259s (i);
-      for( vchain = &rtems_hdl_tbl[i];
-           ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); 
-           vchain = (rtems_irq_connect_data*)vchain->next_handler ) {
+      if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
 	BSP_irq_enable_at_i8259s (i);
-        if (vchain->on)
-          vchain->on(vchain);
+	if (rtems_hdl_tbl[i].on)
+		rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
+      }
+      else {
+	if (rtems_hdl_tbl[i].off)
+		rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);
+	BSP_irq_disable_at_i8259s (i);
      }
    }
-
    /*
     * must enable slave pic anyway
     */
@@ -464,23 +363,3 @@ void processIrq(unsigned index)
  rtems_hdl_tbl[index].hdl(rtems_hdl_tbl[index].handle);
 }

-static inline void
-bsp_irq_dispatch_list(
-  rtems_irq_connect_data *tbl,
-  unsigned                irq,
-  rtems_irq_hdl                sentinel
-)
-{
-  rtems_irq_connect_data* vchain;
-  for( vchain = &tbl[irq];
-       ((int)vchain != -1 && vchain->hdl != sentinel);
-       vchain = (rtems_irq_connect_data*)vchain->next_handler ) {
-          vchain->hdl(vchain->handle);
-  }
-}
-
-
-void C_dispatch_isr(int irq)
-{
-  bsp_irq_dispatch_list(rtems_hdl_tbl, irq, default_rtems_entry.hdl);
-}
--- a/c/src/lib/libbsp/i386/shared/irq/irq.h
+++ b/c/src/lib/libbsp/i386/shared/irq/irq.h
@@ -31,7 +31,6 @@ extern "C" {

 #include <bsp/irq_asm.h>
 #include <rtems.h>
-#define BSP_SHARED_HANDLER_SUPPORT      1
 #include <rtems/irq.h>

 /*-------------------------------------------------------------------------+
@@ -47,7 +46,7 @@ extern "C" {
     * Interrupt offset in comparison to BSP_ASM_IRQ_VECTOR_BASE
     * NB : 1) Interrupt vector number in IDT = offset + BSP_ASM_IRQ_VECTOR_BASE
     * 	    2) The same name should be defined on all architecture
-     *	       so that handler connection can be unchanged.
+     *	       so that handler connexion can be unchanged.
     */
 #define BSP_PERIODIC_TIMER      0
 #define BSP_KEYBOARD          	1
--- a/c/src/lib/libbsp/i386/shared/irq/irq_asm.S
+++ b/c/src/lib/libbsp/i386/shared/irq/irq_asm.S
@@ -107,7 +107,11 @@ nested:
 	 */

        pushl     ecx                       /* push vector number */
-	call	  C_dispatch_isr
+        lea       (ecx,ecx,2), eax
+        mov       SYM (rtems_hdl_tbl), edx
+        shl       $0x3,eax
+        pushl     0x8(edx,eax,1)            /* push hdl argument */
+        call      *0x4(edx,eax,1)           /* call hdl */
        addl      $4, esp

 	/*
--- a/c/src/lib/libbsp/m68k/uC5282/ChangeLog
+++ b/c/src/lib/libbsp/m68k/uC5282/ChangeLog
@@ -1,27 +1,3 @@
-2009-09-09	Till Straumann <strauman@slac.stanford.edu>
-
-	* startup/bspstart.c: Added dummy implementation of firmware
-	syscalls for use with QEMU. Dummy handler is installed if no
-	pre-existing firmware handler is found.
-
-2009-07-30  Eric Norum <norume@aps.anl.gov>
-
-	* include/bsp.h, network/network.c, startup/bspstart.c:  Try enabling
-    the data cache.
-
-2009-07-28  Eric Norum <norume@aps.anl.gov>
-
-   PR 1420/bsps
-   * startup/bspstart.c: Turn on buffered writes to DRAM. As Device Errata
-      SECF124 notes this may cause double writes, but that's not really a big
-      problem and benchmarking tests have shown that buffered writes do gain
-      some performance.
-
-2009-06-02	Eric Norum <norume@aps.anl.gov>
-
-	PR 1420/bsps
-	* startup/bspstart.c: Turn off buffered writes.
-
 2009-03-02	Till Straumann <strauman@slac.stanford.edu>

 	PR 1375/bsps
--- a/c/src/lib/libbsp/m68k/uC5282/include/bsp.h
+++ b/c/src/lib/libbsp/m68k/uC5282/include/bsp.h
@@ -31,7 +31,7 @@ extern "C" {
 * Uncomment to use instruction/data cache
 * Leave commented to use instruction-only cache
 */
-#define RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
+/* #define RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE */

 /***************************************************************************/
 /**  Hardware data structure headers                                      **/
--- a/c/src/lib/libbsp/m68k/uC5282/network/network.c
+++ b/c/src/lib/libbsp/m68k/uC5282/network/network.c
@@ -492,9 +492,13 @@ fec_rxDaemon (void *arg)
 #ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
            /*
             * Invalidate the cache.  The cache is so small that it's
-             * reasonable to simply invalidate the whole thing.
+             * more efficient to just invalidate the whole thing unless
+             * the packet is very small.
             */
-            rtems_cache_invalidate_entire_data();
+            if (len < 128)
+                rtems_cache_invalidate_multiple_data_lines(m->m_data, len);
+            else
+                rtems_cache_invalidate_entire_data();
 #endif
            m->m_len = m->m_pkthdr.len = len - sizeof(struct ether_header);
            eh = mtod(m, struct ether_header *);
--- a/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c
+++ b/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c
@@ -57,20 +57,6 @@
 * should be followed immediately by a NOP instruction.  This avoids the cache
 * corruption problem.
 * DATECODES AFFECTED: All
- *
- *
- * Buffered writes must be disabled as described in "MCF5282 Chip Errata",
- * MCF5282DE, Rev. 6, 5/2009:
- *   SECF124: Buffered Write May Be Executed Twice 
- *   Errata type: Silicon 
- *   Affected component: Cache 
- *   Description: If buffered writes are enabled using the CACR or ACR
- *                registers, the imprecise write transaction generated
- *                by a buffered write may be executed twice. 
- *   Workaround: Do not enable buffered writes in the CACR or ACR registers: 
- *               CACR[8] = DBWE (default buffered write enable) must be 0 
- *               ACRn[5] = BUFW (buffered write enable) must be 0 
- *   Fix plan: Currently, there are no plans to fix this. 
 */
 #define m68k_set_cacr_nop(_cacr) asm volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr))
 #define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr))
@@ -81,7 +67,7 @@
 * Read/write copy of cache registers
 *   Split instruction/data or instruction-only
 *   Allow CPUSHL to invalidate a cache line
- *   Disable buffered writes
+ *   Enable buffered writes
 *   No burst transfers on non-cacheable accesses
 *   Default cache mode is *disabled* (cache only ACRx areas)
 */
@@ -89,6 +75,7 @@ uint32_t mcf5282_cacr_mode = MCF5XXX_CACR_CENB |
 #ifndef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
                             MCF5XXX_CACR_DISD |
 #endif
+                             MCF5XXX_CACR_DBWE |
                             MCF5XXX_CACR_DCM;
 uint32_t mcf5282_acr0_mode = 0;
 uint32_t mcf5282_acr1_mode = 0;
@@ -112,7 +99,7 @@ void _CPU_cache_enable_instruction(void)

    rtems_interrupt_disable(level);
    mcf5282_cacr_mode &= ~MCF5XXX_CACR_DIDI;
-    m68k_set_cacr_nop(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
+    m68k_set_cacr(mcf5282_cacr_mode);
    rtems_interrupt_enable(level);
 }

@@ -146,8 +133,8 @@ void _CPU_cache_enable_data(void)
    rtems_interrupt_level level;

    rtems_interrupt_disable(level);
-    mcf5282_cacr_mode &= ~MCF5XXX_CACR_DISD;
-    m68k_set_cacr_nop(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
+    mcf5282_cacr_mode &= ~MCF5XXX_CACR_CENB;
+    m68k_set_cacr(mcf5282_cacr_mode);
    rtems_interrupt_enable(level);
 #endif
 }
@@ -158,7 +145,8 @@ void _CPU_cache_disable_data(void)
    rtems_interrupt_level level;

    rtems_interrupt_disable(level);
-    mcf5282_cacr_mode |= MCF5XXX_CACR_DISD;
+    rtems_interrupt_disable(level);
+    mcf5282_cacr_mode |= MCF5XXX_CACR_CENB;
    m68k_set_cacr(mcf5282_cacr_mode);
    rtems_interrupt_enable(level);
 #endif
@@ -188,8 +176,6 @@ void _CPU_cache_invalidate_1_data_line(const void *addr)
 void bsp_libc_init( void *, uint32_t, int );
 void bsp_pretasking_hook(void);         /* m68k version */

-extern void bsp_fake_syscall();
-
 /*
 * The Arcturus boot ROM prints exception information improperly
 * so use this default exception handler instead.  This one also
@@ -262,13 +248,6 @@ void bsp_start( void )
        if (i != (32+2)) /* Catch all but bootrom system calls */
            *((void (**)(int))(i * 4)) = handler;

-	/*
-	 * Qemu has no trap handler; install our fake syscall
-	 * implementation if there is no existing handler.
-	 */
-	if ( 0 == *((void (**)(int))((32+2) * 4)) )
-		*((void (**)(int))((32+2) * 4)) = bsp_fake_syscall;
-
  /*
   *  Need to "allocate" the memory for the RTEMS Workspace and
   *  tell the RTEMS configuration where it is.  This memory is
@@ -286,16 +265,12 @@ void bsp_start( void )

  /*
   * Cache SDRAM
-   * Enable buffered writes
-   * As Device Errata SECF124 notes this may cause double writes,
-   * but that's not really a big problem and benchmarking tests have
-   * shown that buffered writes do gain some performance.
   */
  mcf5282_acr0_mode = MCF5XXX_ACR_AB((uint32_t)_RamBase)     |
                      MCF5XXX_ACR_AM((uint32_t)_RamSize-1)   |
                      MCF5XXX_ACR_EN                         |
-                      MCF5XXX_ACR_SM_IGNORE                  |
-                      MCF5XXX_ACR_BWE;
+                      MCF5XXX_ACR_BWE                        |
+                      MCF5XXX_ACR_SM_IGNORE;
  m68k_set_acr0(mcf5282_acr0_mode);

  /*
@@ -428,37 +403,6 @@ syscall_2(int, program, bsp_mnode_t *, chain, int, flags)
 syscall_3(int, flash_erase_range, volatile unsigned short *, flashptr, int, start, int, end);
 syscall_3(int, flash_write_range, volatile unsigned short *, flashptr, bsp_mnode_t *, chain, int, offset);

-/* Provide a dummy-implementation of these syscalls
- * for qemu (which lacks the firmware).
- */
-
-#define __STR(x)    #x
-#define __STRSTR(x) __STR(x)
-#define ERRVAL      __STRSTR(EACCES)
-
-/* reset-control register */
-#define RCR "__IPSBAR + 0x110000"
-
-asm(
-    "bsp_fake_syscall:         \n"
-    "   cmpl  #0,  %d0         \n" /* sysreset    */
-    "   bne   1f               \n"
-    "   moveb #0x80, %d0       \n"
-    "   moveb %d0, "RCR"       \n" /* reset-controller */
-        /* should never get here - but we'd return -EACCESS if we do */
-    "1:                        \n"
-    "   cmpl  #12, %d0         \n" /* gethwaddr   */
-    "   beq   2f               \n"
-    "   cmpl  #14, %d0         \n" /* getbenv     */
-    "   beq   2f               \n"
-    "   movel #-"ERRVAL", %d0  \n" /* return -EACCESS */
-    "   rte                    \n"
-    "2:                        \n"
-    "   movel #0,  %d0         \n" /* return NULL */
-    "   rte                    \n"
-);
-
-
 /*
 * 'Extended BSP' routines
 * Should move to cpukit/score/cpu/m68k/cpu.c someday.
--- a/c/src/lib/libbsp/powerpc/ep1a/ChangeLog
+++ b/c/src/lib/libbsp/powerpc/ep1a/ChangeLog
@@ -1,16 +1,3 @@
-2009-10-16	Jennifer Averett <jennifer@OARcorp.com>
-
-	* Makefile.am, configure.ac, preinstall.am, console/alloc360.c,
-	console/config.c, console/console.c, console/m68360.h,
-	console/mc68360_scc.c, console/rsPMCQ1.c, console/rsPMCQ1.h,
-	include/bsp.h, irq/irq_init.c, irq/openpic_xxx_irq.c, start/start.S,
-	startup/bspstart.c, startup/linkcmds, vme/VMEConfig.h: 
-        Updated and tested against RTEMS 4.9. Updated README file to latest
-        source status. Modified to use the shared irq source code. Turned off
-	debugging, cleaned up warnings, removed unused code. Tested with two
-	PMCQ1 serial cards. Tested MC68360 serial ports and VME using
-	external tests.
-	* README, irq/irq.h, vme/vmeconfig.c: New files.
 2008-12-08	Ralf Corsépius <ralf.corsepius@rtems.org>

 	* bsp_specs: Backport from CVS-HEAD.
--- a/c/src/lib/libbsp/powerpc/ep1a/Makefile.am
+++ b/c/src/lib/libbsp/powerpc/ep1a/Makefile.am
@@ -22,38 +22,37 @@ include_bspdir = $(includedir)/bsp
 dist_project_lib_DATA += startup/linkcmds

 startup_SOURCES = startup/bspstart.c ../../shared/bootcard.c \
-    ../../shared/bspclean.c ../../shared/bsplibc.c \
-    ../../shared/sbrk.c \
-    ../../shared/gnatinstallhandler.c \
-    ../../powerpc/shared/showbats.c  \
-    ../../shared/bsppost.c ../../shared/bsppredriverhook.c 
-
+    ../../shared/bsppost.c ../../shared/bsppredriverhook.c \
+    ../../shared/bsplibc.c ../../powerpc/shared/startup/sbrk.c \
+    ../../shared/bspclean.c ../../shared/gnatinstallhandler.c \
+    ../../powerpc/shared/startup/pgtbl_setup.c \
+    ../../powerpc/shared/startup/pgtbl_activate.c \
+    ../../powerpc/shared/showbats.c

 pclock_SOURCES = ../../powerpc/shared/clock/p_clock.c
+
+include_bsp_HEADERS = ../../powerpc/shared/console/uart.h \
+    ../../powerpc/shared/motorola/motorola.h \
+    ../../powerpc/shared/residual/residual.h \
+    ../../powerpc/shared/residual/pnp.h \
+    ../../powerpc/shared/console/consoleIo.h console/rsPMCQ1.h
 console_SOURCES = console/console.c console/ns16550cfg.c \
    console/mc68360_scc.c console/rsPMCQ1.c console/alloc360.c \
    console/init68360.c

-include_bsp_HEADERS = ../../powerpc/shared/pci/pci.h \
-    ../../powerpc/shared/motorola/motorola.h \
-     ../../powerpc/shared/residual/residual.h \
-    ../../powerpc/shared/residual/pnp.h \
-    ../../powerpc/shared/console/consoleIo.h console/rsPMCQ1.h
+include_bsp_HEADERS += ../../powerpc/shared/openpic/openpic.h
+openpic_SOURCES = ../../powerpc/shared/openpic/openpic.h \
+    ../../powerpc/shared/openpic/openpic.c

+include_bsp_HEADERS += ../../powerpc/shared/pci/pci.h
 pci_SOURCES = pci/no_host_bridge.c ../../powerpc/shared/pci/pci.c \
-        ../../powerpc/shared/pci/pcifinddevice.c
+    ../../powerpc/shared/pci/pcifinddevice.c

-include_bsp_HEADERS += irq/irq.h \
+include_bsp_HEADERS += ../../powerpc/shared/irq/irq.h \
 	../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h \
 	../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h \
 	../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h
-
-irq_SOURCES =  irq/irq.h  irq/irq_init.c irq/openpic_xxx_irq.c \
-    ../../powerpc/shared/irq/i8259.c 
-    
-include_bsp_HEADERS += ../../powerpc/shared/openpic/openpic.h
-
-openpic_SOURCES = ../../powerpc/shared/openpic/openpic.c
+irq_SOURCES = irq/irq_init.c irq/openpic_xxx_irq.c ../../powerpc/shared/irq/i8259.c 

 include_bsp_HEADERS += ../../shared/vmeUniverse/vmeUniverse.h \
    vme/VMEConfig.h \
@@ -65,7 +64,7 @@ include_bsp_HEADERS += ../../shared/vmeUniverse/vmeUniverse.h \

 vme_SOURCES = ../../shared/vmeUniverse/vmeUniverse.c \
    ../../shared/vmeUniverse/bspVmeDmaList.c \
-    vme/vmeconfig.c \
+    ../shared/vme/vmeconfig.c \
    ../shared/vme/vme_universe.c \
    ../../shared/vmeUniverse/vme_am_defs.h

@@ -79,12 +78,9 @@ rtems_crti.$(OBJEXT): ../../powerpc/shared/start/rtems_crti.S
 	$(CPPASCOMPILE) -o $@ -c $<
 project_lib_DATA += rtems_crti.$(OBJEXT)

-EXTRA_DIST += README
-
 noinst_LIBRARIES = libbsp.a
-libbsp_a_SOURCES =  $(pclock_SOURCES) $(console_SOURCES) $(irq_SOURCES) \
-    $(pci_SOURCES) $(vectors_SOURCES) $(startup_SOURCES) \
-    $(openpic_SOURCES) $(vme_SOURCES) 
+libbsp_a_SOURCES = $(startup_SOURCES) $(pclock_SOURCES) $(console_SOURCES) \
+    $(openpic_SOURCES) $(pci_SOURCES) $(irq_SOURCES) $(vme_SOURCES)

 libbsp_a_LIBADD = \
    ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
--- a/c/src/lib/libbsp/powerpc/ep1a/README
+++ b/c/src/lib/libbsp/powerpc/ep1a/README
@@ -1,46 +0,0 @@
-#
-#  $Id$
-#
-
-BSP NAME:           ep1a
-BOARD:              RADSTONE EP1A
-BUS:                N/A
-CPU FAMILY:         ppc
-CPU:                PowerPC 8245
-COPROCESSORS:       N/A
-MODE:               32 bit mode
-
-DEBUG MONITOR:      see note.
-
-PERIPHERALS
-===========
-TIMERS:             PPC internal Timebase register
-  RESOLUTION:         
-SERIAL PORTS:       1 onboard QUIC, optional 2 mezannes with QUIC chips
-REAL-TIME CLOCK:    xxx
-DMA:                none
-VIDEO:              none
-SCSI:               none
-NETWORKING:         none
-
-DRIVER INFORMATION
-==================
-CLOCK DRIVER:       PPC internal
-IOSUPP DRIVER:      N/A
-SHMSUPP:            N/A
-TIMER DRIVER:       PPC internal
-TTY DRIVER:         PPC internal
-
-STDIO
-=====
-PORT:               Console port 0
-ELECTRICAL:         na
-BAUD:               9600
-BITS PER CHARACTER: 8
-PARITY:             n
-STOP BITS:          1
-
-Notes
-=====
-This bsp has been tested with an custom ep1a, which had two 
-PMCQ1 Daughter cards attached.
--- a/c/src/lib/libbsp/powerpc/ep1a/configure.ac
+++ b/c/src/lib/libbsp/powerpc/ep1a/configure.ac
@@ -15,21 +15,6 @@ RTEMS_PROG_CC_FOR_TARGET([-ansi -fasm])
 RTEMS_CANONICALIZE_TOOLS
 RTEMS_PROG_CCAS

-RTEMS_BSPOPTS_SET([CONSOLE_USE_INTERRUPTS],[*],[1])
-RTEMS_BSPOPTS_HELP([CONSOLE_USE_INTERRUPTS],
-[whether using console interrupts])
-
-RTEMS_BSPOPTS_SET([INITIALIZE_COM_PORTS],[*],[0])
-RTEMS_BSPOPTS_HELP([INITIALIZE_COM_PORTS],
-[FIXME: Missing explanation])
-
-RTEMS_BSPOPTS_SET([PPC_USE_SPRG],[*],[0])
-RTEMS_BSPOPTS_HELP([PPC_USE_SPRG],
-[If defined, then the PowerPC specific code in RTEMS will use some
-of the special purpose registers to slightly optimize interrupt
-response time.  The use of these registers can conflict with
-other tools like debuggers.])
-
 RTEMS_BSPOPTS_SET([PPC_USE_DATA_CACHE],[*],[0])
 RTEMS_BSPOPTS_HELP([PPC_USE_DATA_CACHE],
 [If defined, then the PowerPC specific code in RTEMS will use
@@ -39,10 +24,14 @@ RTEMS_BSPOPTS_HELP([PPC_USE_DATA_CACHE],
 of PowerPC 603e revisions and emulator versions.
 The BSP actually contains the call that enables this.])

-RTEMS_BSPOPTS_SET([PPC_VECTOR_FILE_BASE],[*],[0x0100])
-RTEMS_BSPOPTS_HELP([PPC_VECTOR_FILE_BASE],
-[This defines the base address of the exception table.
- NOTE: Vectors are actually at 0xFFF00000 but file starts at offset.])
+RTEMS_BSPOPTS_SET([INSTRUCTION_CACHE_ENABLE],[*],[0])
+RTEMS_BSPOPTS_HELP([INSTRUCTION_CACHE_ENABLE],
+[If defined, the instruction cache will be enabled after address translation
+ is turned on.])
+
+RTEMS_BSPOPTS_SET([CONSOLE_USE_INTERRUPTS],[*],[0])
+RTEMS_BSPOPTS_HELP([CONSOLE_USE_INTERRUPTS],
+[whether using console interrupts])

 RTEMS_CHECK_NETWORKING
 AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
--- a/c/src/lib/libbsp/powerpc/ep1a/console/alloc360.c
+++ b/c/src/lib/libbsp/powerpc/ep1a/console/alloc360.c
@@ -34,40 +34,23 @@ void M360SetupMemory( M68360_t ptr ){

 #if DEBUG_PRINT
 printk("m360->mcr:0x%08x  Q1_360_SIM_MCR:0x%08x\n", 
-       (uint32_t)&(m360->mcr), ((uint32_t)m360+Q1_360_SIM_MCR));
+       (unsigned int)&(m360->mcr), ((unsigned int)m360+Q1_360_SIM_MCR));
 #endif
-  ptr->bdregions[0].base = (uint8_t *)&m360->dpram1[0];
+  ptr->bdregions[0].base = (char *)&m360->dpram1[0];
  ptr->bdregions[0].size = sizeof m360->dpram1;
  ptr->bdregions[0].used = 0;
-#if DEBUG_PRINT
-printk("%d) base 0x%x size %d used %d\n", 0,
-       (uint32_t)ptr->bdregions[0].base, ptr->bdregions[0].size, ptr->bdregions[0].used );
-#endif

-  ptr->bdregions[1].base = (uint8_t *)&m360->dpram3[0];
+  ptr->bdregions[1].base = (char *)&m360->dpram3[0];
  ptr->bdregions[1].size = sizeof m360->dpram3;
  ptr->bdregions[1].used = 0;
-#if DEBUG_PRINT
-printk("%d) base 0x%x size %d used %d\n", 1,
-       (uint32_t)ptr->bdregions[1].base, ptr->bdregions[1].size, ptr->bdregions[1].used );
-#endif

-  ptr->bdregions[2].base = (uint8_t *)&m360->dpram0[0];
+  ptr->bdregions[2].base = (char *)&m360->dpram0[0];
  ptr->bdregions[2].size = sizeof m360->dpram0;
  ptr->bdregions[2].used = 0;
-#if DEBUG_PRINT
-printk("%d) base 0x%x size %d used %d\n", 2,
-       (uint32_t)ptr->bdregions[2].base, ptr->bdregions[2].size, ptr->bdregions[2].used );
-#endif

-  ptr->bdregions[3].base = (uint8_t *)&m360->dpram2[0];
+  ptr->bdregions[3].base = (char *)&m360->dpram2[0];
  ptr->bdregions[3].size = sizeof m360->dpram2;
  ptr->bdregions[3].used = 0;
-#if DEBUG_PRINT
-printk("%d) base 0x%x size %d used %d\n", 3,
-       (uint32_t)ptr->bdregions[3].base, ptr->bdregions[3].size, ptr->bdregions[3].used );
-#endif
-
 }


@@ -77,11 +60,11 @@ printk("%d) base 0x%x size %d used %d\n", 3,
 void *
 M360AllocateBufferDescriptors (M68360_t ptr, int count)
 {
-  uint32_t     i;
+  unsigned int i;
  ISR_Level    level;
  void         *bdp  = NULL;
-  uint32_t      want  = count * sizeof(m360BufferDescriptor_t);
-  uint32_t      have;
+  unsigned int want  = count * sizeof(m360BufferDescriptor_t);
+  int          have;

  /*
   * Running with interrupts disabled is usually considered bad
@@ -98,27 +81,15 @@ M360AllocateBufferDescriptors (M68360_t ptr, int count)
     * less dual-port RAM.
     */
    if (ptr->bdregions[i].used == 0) {
-      volatile uint8_t *cp = ptr->bdregions[i].base;
-      uint8_t data;
-
+      volatile unsigned char *cp = ptr->bdregions[i].base;
      *cp = 0xAA;
-      data = *cp;
-      if (data != 0xAA) {
+      if (*cp != 0xAA) {
        ptr->bdregions[i].used = ptr->bdregions[i].size;
-#if DEBUG_PRINT
-printk("%d) base 0x%x used %d expected 0xAA read 0x%x\n",i, 
-       (uint32_t)ptr->bdregions[i].base, ptr->bdregions[0].used, data );
-#endif
        continue;
      }
      *cp = 0x55;
-      data = *cp;
-      if (data != 0x55) {
+      if (*cp != 0x55) {
        ptr->bdregions[i].used = ptr->bdregions[i].size;
-#if DEBUG_PRINT
-printk("%d) base 0x%x used %d expected 0x55 read 0x%x\n",i, 
-       (uint32_t)ptr->bdregions[i].base, ptr->bdregions[0].used, data );
-#endif
        continue;
      }
      *cp = 0x0;
--- a/c/src/lib/libbsp/powerpc/ep1a/console/config.c
+++ b/c/src/lib/libbsp/powerpc/ep1a/console/config.c
@@ -1,7 +1,7 @@
 /*
 *  This file contains the TTY driver table for the EP1A
 * 
- *  COPYRIGHT (c) 1989-2009.
+ *  COPYRIGHT (c) 1989-1999.
 *  On-Line Applications Research Corporation (OAR).
 *
 *  The license and distribution terms for this file may be
@@ -21,12 +21,7 @@
 *  or interrupt driven IO.
 */

-#if 1 
 #define NS16550_FUNCTIONS &ns16550_fns_polled
-#else
-#define NS16550_FUNCTIONS &ns16550_fns
-#endif
-
 #define MC68360_SCC_FUNCTIONS &mc68360_scc_fns

 /*
@@ -127,7 +122,6 @@ console_tbl	Console_Port_Tbl[] = {
                7372800,                        /* ulClock */
                0                               /* ulIntVector */
        },
-
        /*
         * Up to 12 serial ports are provided by MC68360 SCC ports.
         *     EP1A may have one MC68360 providing 4 ports (A,B,C,D).
@@ -437,8 +431,3 @@ static bool config_68360_scc_base_probe_12( int minor ) {
  return config_68360_scc_base_probe( minor, 0, 15, 4);
 }

-
-void Force_mc8360_interrupt( int d ) {
-  mc68360_sccInterruptHandler( M68360_chips->next );
-}
-
--- a/c/src/lib/libbsp/powerpc/ep1a/console/console.c
+++ b/c/src/lib/libbsp/powerpc/ep1a/console/console.c
@@ -1,4 +1,4 @@
-/*
+/*XXX
 *  This file contains the TTY driver for the ep1a 
 *
 *  This driver uses the termios pseudo driver.
@@ -212,11 +212,6 @@ rtems_device_driver console_initialize(
    Console_Port_Tbl[minor].pDeviceFns->deviceInitialize(
      Console_Port_Minor);

-  /*
-   * NOTE:  We must probe ALL possible devices, which initializes
-   *        the address information in the config.c tables.
-   */
-
  for(minor++;minor<Console_Port_Count;minor++)
  {
    /*
@@ -246,6 +241,83 @@ rtems_device_driver console_initialize(

  return RTEMS_SUCCESSFUL;
 }
+#if 0
+/* PAGE
+ *
+ *  DEBUG_puts
+ *
+ *  This should be safe in the event of an error.  It attempts to ensure
+ *  that no TX empty interrupts occur while it is doing polled IO.  Then
+ *  it restores the state of that external interrupt.
+ *
+ *  Input parameters:
+ *    string  - pointer to debug output string
+ *
+ *  Output parameters:  NONE
+ *
+ *  Return values:      NONE
+ */
+
+void DEBUG_puts(
+	char *string
+)
+{
+	char *s;
+	unsigned32	Irql;
+
+	rtems_interrupt_disable(Irql);
+
+	for ( s = string ; *s ; s++ ) 
+	{
+		Console_Port_Tbl[Console_Port_Minor].pDeviceFns->
+			deviceWritePolled(Console_Port_Minor, *s);
+	}
+
+	rtems_interrupt_enable(Irql);
+}
+
+/* PAGE
+ *
+ *  DEBUG_puth
+ *
+ *  This should be safe in the event of an error.  It attempts to ensure
+ *  that no TX empty interrupts occur while it is doing polled IO.  Then
+ *  it restores the state of that external interrupt.
+ *
+ *  Input parameters:
+ *    ulHexNum - value to display
+ *
+ *  Output parameters:  NONE
+ *
+ *  Return values:      NONE
+ */
+void
+DEBUG_puth(
+    unsigned32 ulHexNum
+    )
+{
+	unsigned long i,d;
+	unsigned32 Irql;
+
+	rtems_interrupt_disable(Irql);
+	
+	Console_Port_Tbl[Console_Port_Minor].pDeviceFns->
+		deviceWritePolled(Console_Port_Minor, '0');
+	Console_Port_Tbl[Console_Port_Minor].pDeviceFns->
+		deviceWritePolled(Console_Port_Minor, 'x');
+
+	for(i=32;i;)
+	{
+		i-=4;
+		d=(ulHexNum>>i)&0xf;
+		Console_Port_Tbl[Console_Port_Minor].pDeviceFns->
+			deviceWritePolled(Console_Port_Minor,
+					  (d<=9) ? d+'0' : d+'a'-0xa);
+	}
+
+	rtems_interrupt_enable(Irql);
+}
+#endif

 /* const char arg to be compatible with BSP_output_char decl. */
 void
--- a/c/src/lib/libbsp/powerpc/ep1a/console/m68360.h
+++ b/c/src/lib/libbsp/powerpc/ep1a/console/m68360.h
@@ -16,7 +16,7 @@
 *      eric@skatter.usask.ca                      
 *                                            
 *
- *  COPYRIGHT (c) 1989-2009.
+ *  COPYRIGHT (c) 1989-1999.
 *  On-Line Applications Research Corporation (OAR).
 *
 *  The license and distribution terms for this file may be
@@ -935,9 +935,9 @@ typedef struct m360_ {
 } m360_t;

 struct bdregions_t {
-  uint8_t     *base;
-  uint32_t    size;
-  uint32_t    used;
+  char            *base;
+  unsigned int    size;
+  unsigned int    used;
 };

 #define M68360_RX_BUF_SIZE        1
@@ -977,8 +977,6 @@ void *M360AllocateBufferDescriptors (M68360_t ptr, int count);
 void M360ExecuteRISC( volatile m360_t *m360, uint16_t command);
 int mc68360_scc_create_chip( PPMCQ1BoardData BoardData, uint8_t int_vector );

-void mc68360_sccInterruptHandler( void *ptr);
-
 #if 0
 extern volatile m360_t *m360;
 #endif
--- a/c/src/lib/libbsp/powerpc/ep1a/console/mc68360_scc.c
+++ b/c/src/lib/libbsp/powerpc/ep1a/console/mc68360_scc.c
@@ -1,7 +1,7 @@
 /*  This file contains the termios TTY driver for the
 *  Motorola MC68360 SCC ports.
 *
- *  COPYRIGHT (c) 1989-2009.
+ *  COPYRIGHT (c) 1989-2008.
 *  On-Line Applications Research Corporation (OAR).
 *
 *  The license and distribution terms for this file may be
@@ -25,7 +25,7 @@
 #include <rtems/bspIo.h>
 #include <string.h>

-#if 0 
+#if 0
 #define DEBUG_360
 #endif

@@ -77,10 +77,10 @@ void scc_write8(
  uint8_t           value
 )
 {
-  *address = value;
 #ifdef DEBUG_360
  printk( "WR8 %s 0x%08x 0x%02x\n", name, address, value );
 #endif
+  *address = value;
 }


@@ -108,10 +108,10 @@ void scc_write16(
  uint16_t           value
 )
 {
-  *address = value;
 #ifdef DEBUG_360
  printk( "WR16 %s 0x%08x 0x%04x\n", name, address, value );
 #endif
+  *address = value;
 }


@@ -139,11 +139,10 @@ void scc_write32(
  uint32_t           value
 )
 {
-  *address = value;
-  Processor_Synchronize();
 #ifdef DEBUG_360
  printk( "WR32 %s 0x%08x 0x%08x\n", name, address, value );
 #endif
+  *address = value;
 }

 void mc68360_sccShow_Regs(int minor){
@@ -156,9 +155,9 @@ void mc68360_sccShow_Regs(int minor){
 }

 #define TX_BUFFER_ADDRESS( _ptr ) \
-  ((uint8_t *)ptr->txBuf - (uint8_t *)ptr->chip->board_data->baseaddr)
+  ((char *)ptr->txBuf - (char *)ptr->chip->board_data->baseaddr)
 #define RX_BUFFER_ADDRESS( _ptr ) \
-  ((uint8_t *)ptr->rxBuf - (uint8_t *)ptr->chip->board_data->baseaddr)
+  ((char *)ptr->rxBuf - (char *)ptr->chip->board_data->baseaddr)


 /**************************************************************************
@@ -240,9 +239,8 @@ mc68360_sccBRGC(int baud, int m360_clock_rate)
 *    none                                                                *
 *                                                                        *
 **************************************************************************/
-void mc68360_sccInterruptHandler( void *ptr)
+void mc68360_sccInterruptHandler( M68360_t chip )
 {
-  M68360_t           chip   = ptr;
  volatile m360_t    *m360;
  int                port;
  uint16_t           status;
@@ -252,8 +250,8 @@ void mc68360_sccInterruptHandler( void *ptr)
  int                clear_isr;


-#ifdef DEBUG_360 
-  printk("mc68360_sccInterruptHandler with 0x%x \n", ptr);
+#ifdef DEBUG_360
+  printk("mc68360_sccInterruptHandler\n");
 #endif
  for (port=0; port<4; port++) {

@@ -277,8 +275,8 @@ void mc68360_sccInterruptHandler( void *ptr)
        while ((status & M360_BD_EMPTY) == 0)
        {
           length= scc_read16("sccRxBd->length",&chip->port[port].sccRxBd->length);
-           if (length > 1)
-             EP1A_READ_LENGTH_GREATER_THAN_1 = length;
+if (length > 1)
+  EP1A_READ_LENGTH_GREATER_THAN_1 = length;

           for (i=0;i<length;i++) {
             data= chip->port[port].rxBuf[i];
@@ -304,19 +302,21 @@ void mc68360_sccInterruptHandler( void *ptr)
        if ((status & M360_BD_EMPTY) == 0)
        {
           scc_write16("sccTxBd->status",&chip->port[port].sccTxBd->status,0);
+#if 1
           rtems_termios_dequeue_characters(
             Console_Port_Data[chip->port[port].minor].termios_data, 
-             chip->port[port].sccTxBd->length
-           );
+             chip->port[port].sccTxBd->length);
+#else
+           mc68360_scc_write_support_int(chip->port[port].minor,"*****", 5); 
+#endif
        }
      }

      /*
       * Clear SCC interrupt-in-service bit.
       */
-      if ( clear_isr ) {
+      if ( clear_isr )
        scc_write32( "cisr", &m360->cisr, (0x80000000 >> chip->port[port].channel) );
-      }
  }
 }

@@ -339,9 +339,10 @@ int mc68360_scc_open(
  uint32_t               data;

 #ifdef DEBUG_360
-  printk("mc68360_scc_open %s (%d)\n", Console_Port_Tbl[minor].sDeviceName, minor);
+  printk("mc68360_scc_open %d\n", minor);
 #endif

+
  ptr   = Console_Port_Tbl[minor].pDeviceParams;
  m360  = ptr->chip->m360;

@@ -367,8 +368,8 @@ int mc68360_scc_open(

 uint32_t mc68360_scc_calculate_pbdat( M68360_t chip )
 {
-  int                    i;
-  uint32_t               pbdat_data = 0x03;
+  uint32_t               i;
+  uint32_t               pbdat_data;
  int                    minor;
  uint32_t               type422data[4] = {
    0x00440,  0x00880,  0x10100,  0x20200
@@ -377,15 +378,13 @@ uint32_t mc68360_scc_calculate_pbdat( M68360_t chip )
  pbdat_data = 0x3;
  for (i=0; i<4; i++) {
    minor = chip->port[i].minor;
-    if mc68360_scc_Is_422( minor ){
+    if mc68360_scc_Is_422( minor ) 
      pbdat_data |= type422data[i];
-    }
  }

  return pbdat_data;
 }

-
 /*
 *  mc68360_scc_initialize_interrupts
 *
@@ -401,7 +400,7 @@ void mc68360_scc_initialize_interrupts(int minor)
  uint32_t               buffers_start;
  uint32_t               tmp_u32;

-#ifdef DEBUG_360 
+#ifdef DEBUG_360
  printk("mc68360_scc_initialize_interrupts: minor %d\n", minor );
  printk("Console_Port_Tbl[minor].pDeviceParams 0x%08x\n",
    Console_Port_Tbl[minor].pDeviceParams );
@@ -410,7 +409,7 @@ void mc68360_scc_initialize_interrupts(int minor)
  ptr   = Console_Port_Tbl[minor].pDeviceParams;
  m360  = ptr->chip->m360;
  
-#ifdef DEBUG_360 
+#ifdef DEBUG_360
  printk("m360 0x%08x baseaddr 0x%08x\n",
     m360, ptr->chip->board_data->baseaddr);
 #endif
@@ -465,7 +464,6 @@ void mc68360_scc_initialize_interrupts(int minor)
  /*
   * XXX
   */
-
  scc_write16( "papar", &m360->papar, 0xffff );
  scc_write16( "padir", &m360->padir, 0x5500 ); /* From Memo    */
  scc_write16( "paodr", &m360->paodr, 0x0000 );
@@ -666,11 +664,6 @@ int mc68360_scc_write_support_int(
  rtems_interrupt_level  Irql;
  M68360_serial_ports_t  ptr;

-#ifdef DEBUG_360
-  printk("mc68360_scc_write_support_int: char 0x%x length %d\n",
-       (unsigned int)*buf, len );
-#endif
-
 #if 1
  mc68360_length_array[ mc68360_length_count ] = len;
  mc68360_length_count++;
@@ -688,13 +681,18 @@ int mc68360_scc_write_support_int(
  if ( !len )
    return 0;

+  /*
+   *
+   */
+#ifdef DEBUG_360
+  printk("mc68360_scc_write_support_int: char 0x%x length %d\n",
+       (unsigned int)*buf, len );
+#endif
  /*
   *  We must copy the data from the global memory space to MC68360 space
   */
+
  rtems_interrupt_disable(Irql);
-#ifdef DEBUG_360
-  printk("mc68360_scc_write_support_int: disable irq 0x%x\n", Irql );
-#endif

  scc_write16( "sccTxBd->status", &ptr->sccTxBd->status, 0 );
  memcpy((void *) ptr->txBuf, buf, len);
@@ -704,9 +702,6 @@ int mc68360_scc_write_support_int(
  scc_write16( "sccTxBd->status", &ptr->sccTxBd->status, 
               (M360_BD_READY | M360_BD_WRAP | M360_BD_INTERRUPT) );

-#ifdef DEBUG_360
-  printk("mc68360_scc_write_support_int: enable irq 0x%x\n", Irql );
-#endif
  rtems_interrupt_enable(Irql);

  return len;
@@ -902,14 +897,12 @@ int mc68360_scc_create_chip( PPMCQ1BoardData BoardData, uint8_t int_vector )
   * XXX - Note Does this need to be moved up to if a QUICC is fitted
   *       section?
   */
-
-  if ((chip = calloc( 1, sizeof(struct _m68360_per_chip))) == NULL)
+  if ((chip = malloc(sizeof(struct _m68360_per_chip))) == NULL)
  {
    printk("Error Unable to allocate memory for _m68360_per_chip\n");
    return RTEMS_IO_ERROR;
-  } else {
-    printk("Allocate memory for _m68360_per_chip at 0x%x\n", chip );
  }
+
  chip->next                    = M68360_chips;
  chip->m360                    = (void *)BoardData->baseaddr;
  chip->m360_interrupt          = int_vector;
@@ -952,6 +945,7 @@ int mc68360_scc_create_chip( PPMCQ1BoardData BoardData, uint8_t int_vector )
    /*
     * Allocate buffer descriptors.
     */
+
    chip->port[i-1].sccRxBd = M360AllocateBufferDescriptors(chip, 1);
    chip->port[i-1].sccTxBd = M360AllocateBufferDescriptors(chip, 1);
  }
@@ -963,6 +957,7 @@ int mc68360_scc_create_chip( PPMCQ1BoardData BoardData, uint8_t int_vector )
    &mc68360_sccInterruptHandler,
    chip 
  );
+
  return RTEMS_SUCCESSFUL;
 }

--- a/c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.c
+++ b/c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.c
@@ -27,7 +27,7 @@ These functions are responsible for scanning for PMCQ1's and setting up
 the Motorola MC68360's if present.

 USAGE
-call rsPMCQ1Init() to perform basic initialisation of the PMCQ1's.
+call rsPMCQ1Init() to perform ba  sic initialisation of the PMCQ1's.
 */

 /* includes */
@@ -41,8 +41,8 @@ call rsPMCQ1Init() to perform basic initialisation of the PMCQ1's.
 #include "m68360.h"

 /* defines */
-#if 0 
-#define DEBUG_360     TRUE
+#if 1
+#define DEBUG_360
 #endif

 /* Local data */
@@ -82,61 +82,27 @@ static unsigned char rsPMCQ1eeprom[] =

 void MsDelay(void)
 {
-  printk("..");
+  printk(".");
 }

 void write8( int addr, int data ){
-  out_8((volatile void *)addr, (unsigned char)data);
-  Processor_Synchronize();
+  out_8((void *)addr, (unsigned char)data);
 }

 void write16( int addr, int data ) {
-  out_be16((volatile void *)addr, (short)data );
-  Processor_Synchronize();
+  out_be16((void *)addr, (short)data );
 }

 void write32( int addr, int data ) {
-  out_be32((volatile unsigned int *)addr, data );
-  Processor_Synchronize();
+  out_be32((unsigned int *)addr, data );
 }

 int read32( int addr){
-  int value = in_be32((volatile unsigned int *)addr);
-  Processor_Synchronize();
-  return value;
-}
-
-void rsPMCQ1_scc_On(const struct __rtems_irq_connect_data__ *ptr) 
-{
-
-}
-
-void rsPMCQ1_scc_Off(const struct __rtems_irq_connect_data__ *ptr) 
-{
-
-}
-
-int rsPMCQ1_scc_except_always_enabled(const struct __rtems_irq_connect_data__ *ptr)
-{
-  return TRUE;
+  return in_be32((unsigned int *)addr);
 }


-void rsPMCQ1ShowIntrStatus(void )
-{
-  unsigned long   status;
-  unsigned long   mask;
-  PPMCQ1BoardData boardData;
-
-  for (boardData = pmcq1BoardData; boardData; boardData = boardData->pNext)
-  {
-
-    status = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS );
-    mask   = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_MASK );
-    printk("rsPMCQ1ShowIntrStatus: interrupt status 0x%x) 0x%x with mask: 0x%x\n", boardData->quiccInt, status, mask);
-  }
-}
-
+void rsPMCQ1_scc_nullFunc(void) {}
  
 /*******************************************************************************
 * rsPMCQ1Int - handle a PMCQ1 interrupt
@@ -150,57 +116,48 @@ void rsPMCQ1ShowIntrStatus(void )
 void rsPMCQ1Int( void *ptr )
 {
  unsigned long   status;
-  static unsigned long   status1;
+  unsigned long   status1;
  unsigned long   mask;
  uint32_t        data;
  PPMCQ1BoardData boardData = ptr;
-  volatile unsigned long *hrdwr;
-  unsigned long           value;

  status = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS );
  mask   = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_MASK );

-
-  if (((mask & PMCQ1_INT_MASK_QUICC) == 0) && ((status & PMCQ1_INT_STATUS_QUICC) != 0 ))
+  if (((mask & PMCQ1_INT_MASK_QUICC) == 0) && (status & PMCQ1_INT_STATUS_QUICC))
  {
    /* If there is a handler call it otherwise mask the interrupt */
    if (boardData->quiccInt) {
      boardData->quiccInt(boardData->quiccArg);
    } else {
-      printk("No handler - Masking interrupt\n");
-      hrdwr = (volatile unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK);
-      value = (*hrdwr) | PMCQ1_INT_MASK_QUICC;
-      *hrdwr = value;
+      *(volatile unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_QUICC;
    }
  }

  if (((mask & PMCQ1_INT_MASK_MA) == 0) && (status & PMCQ1_INT_STATUS_MA))
  {
-
    /* If there is a handler call it otherwise mask the interrupt */
    if (boardData->maInt) {
      boardData->maInt(boardData->maArg);
+
      data = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS );
-      data = data & (~PMCQ1_INT_STATUS_MA);
+      data &= (~PMCQ1_INT_STATUS_MA);
      PMCQ1_Write_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS, data );
-    } else { 
-      printk("No handler - Masking interrupt\n");
-      hrdwr = (volatile unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK);
-      value = (*hrdwr) | PMCQ1_INT_MASK_MA;
-      *hrdwr = value;
+
+    } else {
+     *(volatile unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_MA;
    }
  }

  RTEMS_COMPILER_MEMORY_BARRIER();

  /* Clear Interrupt on QSPAN */
-  hrdwr = (volatile unsigned long *)(boardData->bridgeaddr + 0x600);
-  *hrdwr = 0x00001000;
+  *(volatile unsigned long *)(boardData->bridgeaddr + 0x600) = 0x00001000;

  /* read back the status register to ensure that the pci write has completed */
-  status1 = *hrdwr;
-
+  status1 = *(volatile unsigned long *)(boardData->bridgeaddr + 0x600);
  RTEMS_COMPILER_MEMORY_BARRIER();
+
 }


@@ -218,8 +175,8 @@ unsigned int rsPMCQ1MaIntConnect (
    unsigned long	busNo,	/* Pci Bus number of PMCQ1 */
    unsigned long	slotNo,	/* Pci Slot number of PMCQ1 */
    unsigned long	funcNo,	/* Pci Function number of PMCQ1 */
-    PMCQ1_FUNCTION_PTR	routine,/* interrupt routine */
-    void * 	        arg	/* argument to pass to interrupt routine */
+    FUNCION_PTR	routine,/* interrupt routine */
+    int		arg	/* argument to pass to interrupt routine */
 )
 {
  PPMCQ1BoardData boardData;
@@ -274,7 +231,7 @@ unsigned int rsPMCQ1MaIntDisconnect(
        (boardData->funcNo == funcNo))
    {
      boardData->maInt = NULL;
-      *(volatile unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_MA;
+      *(unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_MA;
      status = RTEMS_SUCCESSFUL;
      break;
    }
@@ -294,11 +251,11 @@ unsigned int rsPMCQ1MaIntDisconnect(
 */

 unsigned int rsPMCQ1QuiccIntConnect(
-  unsigned long         busNo,	 /* Pci Bus number of PMCQ1 */ 
-  unsigned long         slotNo,  /* Pci Slot number of PMCQ1 */
-  unsigned long         funcNo,  /* Pci Function number of PMCQ1 */
-  PMCQ1_FUNCTION_PTR    routine, /* interrupt routine */
-  void *                arg      /* argument to pass to interrupt routine */
+    unsigned long	busNo,	/* Pci Bus number of PMCQ1 */
+    unsigned long	slotNo,	/* Pci Slot number of PMCQ1 */
+    unsigned long	funcNo,	/* Pci Function number of PMCQ1 */
+    FUNCION_PTR	routine,/* interrupt routine */
+    int		arg	/* argument to pass to interrupt routine */
 )
 {
  PPMCQ1BoardData boardData;
@@ -343,7 +300,7 @@ unsigned int rsPMCQ1QuiccIntDisconnect(
        (boardData->funcNo == funcNo))
    {
      boardData->quiccInt = NULL;
-      *(volatile unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_QUICC;
+      *(unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_QUICC;
      status = RTEMS_SUCCESSFUL;
      break;
    }
@@ -366,22 +323,25 @@ unsigned int rsPMCQ1Init(void)
 {
  int busNo;
  int slotNo;
-  uint32_t baseaddr = 0;
-  uint32_t bridgeaddr = 0;
+  unsigned int baseaddr = 0;
+  unsigned int bridgeaddr = 0;
  unsigned long pbti0_ctl;
  int i;
  unsigned char int_vector;
  int fun;
-  uint32_t temp;
+  int temp;
  PPMCQ1BoardData       boardData;
-  rtems_irq_connect_data *IrqData = NULL;
+  rtems_irq_connect_data IrqData = {0,
+                                    rsPMCQ1Int,
+                                    rsPMCQ1_scc_nullFunc,
+                                    rsPMCQ1_scc_nullFunc,
+                                    rsPMCQ1_scc_nullFunc,
+                                    NULL};

  if (rsPMCQ1Initialized)
  {
-    printk("rsPMCQ1Init: Already Initialized\n");
    return RTEMS_SUCCESSFUL;
-  } 
-
+  }
  for (i=0;;i++){
    if ( pci_find_device(PCI_VEN_ID_RADSTONE, PCI_DEV_ID_PMCQ1, i, &busNo, &slotNo, &fun) != 0 )
      break;
@@ -389,17 +349,17 @@ unsigned int rsPMCQ1Init(void)
    pci_read_config_dword(busNo, slotNo, 0, PCI_BASE_ADDRESS_2, &baseaddr);
    pci_read_config_dword(busNo, slotNo, 0, PCI_BASE_ADDRESS_0, &bridgeaddr);
 #ifdef DEBUG_360
-  printk("rsPMCQ1Init: PMCQ1 baseaddr 0x%08x bridgeaddr 0x%08x\n", baseaddr, bridgeaddr );
+  printk("PMCQ1 baseaddr 0x%08x bridgeaddr 0x%08x\n", baseaddr, bridgeaddr );
 #endif

    /* Set function code to normal mode and enable window */
-    pbti0_ctl = (*(unsigned long *)(bridgeaddr + 0x100)) & 0xff0fffff;
+    pbti0_ctl = *(unsigned long *)(bridgeaddr + 0x100) & 0xff0fffff;
    eieio();
-    *(volatile unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00500080;
+    *(unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00500080;
    eieio();

    /* Assert QBUS reset */
-    *(volatile unsigned long *)(bridgeaddr + 0x800) |= 0x00000080;
+    *(unsigned long *)(bridgeaddr + 0x800) |= 0x00000080;
    eieio();

    /*
@@ -408,7 +368,7 @@ unsigned int rsPMCQ1Init(void)
    MsDelay();

    /* Take QBUS out of reset */
-    *(volatile unsigned long *)(bridgeaddr + 0x800) &= ~0x00000080;
+    *(unsigned long *)(bridgeaddr + 0x800) &= ~0x00000080;
    eieio();

    MsDelay();
@@ -417,19 +377,19 @@ unsigned int rsPMCQ1Init(void)
    if (PMCQ1_Read_EPLD(baseaddr, PMCQ1_BUILD_OPTION) & PMCQ1_QUICC_FITTED)
    {
 #ifdef DEBUG_360 
-  printk("rsPMCQ1Init: Found QUICC busNo %d slotNo %d\n", busNo, slotNo);
+  printk(" Found QUICC busNo %d slotNo %d\n", busNo, slotNo);
 #endif

      /* Initialise MBAR (must use function code of 7) */
-      *(volatile unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00700080;
+      *(unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00700080;
      eieio();

      /* place internal 8K SRAM and registers at address 0x0 */
-      *(volatile unsigned long *)(baseaddr + Q1_360_MBAR) = 0x1;
+      *(unsigned long *)(baseaddr + Q1_360_MBAR) = 0x1;
      eieio();

      /* Set function code to normal mode */
-      *(volatile unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00500080;
+      *(unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00500080;
      eieio();

      /* Disable the SWT and perform basic initialisation */
@@ -465,15 +425,15 @@ unsigned int rsPMCQ1Init(void)
     */
    pci_read_config_dword(busNo, slotNo, 0, PCI_BASE_ADDRESS_3, &temp);
    if (temp) {
-      *(volatile unsigned long *)(bridgeaddr + 0x110) |= 0x00500880;
+      *(unsigned long *)(bridgeaddr + 0x110) |= 0x00500880;
    }

    /*
     * Create descriptor structure for this card
     */
-    if ((boardData = calloc(1, sizeof(struct _PMCQ1BoardData))) == NULL)
+    if ((boardData = malloc(sizeof(struct _PMCQ1BoardData))) == NULL)
    {
-      printk("rsPMCQ1Init: Error Unable to allocate memory for _PMCQ1BoardData\n");
+      printk("Error Unable to allocate memory for _PMCQ1BoardData\n");
      return(RTEMS_IO_ERROR);
    }

@@ -486,7 +446,6 @@ unsigned int rsPMCQ1Init(void)
    boardData->quiccInt = NULL;
    boardData->maInt = NULL;
    pmcq1BoardData = boardData;
-
    mc68360_scc_create_chip( boardData, int_vector );

    /*
@@ -494,22 +453,11 @@ unsigned int rsPMCQ1Init(void)
     */
    pci_read_config_byte(busNo, slotNo, 0, 0x3c, &int_vector);
 #ifdef DEBUG_360
-    printk("rsPMCQ1Init: PMCQ1 int_vector %d\n", int_vector);
+    printk("PMCQ1 int_vector %d\n", int_vector);
 #endif
-
-    if ((IrqData = calloc( 1, sizeof(rtems_irq_connect_data) )) == NULL )
-    {
-      printk("rsPMCQ1Init: Error Unable to allocate memory for rtems_irq_connect_data\n");
-      return(RTEMS_IO_ERROR);
-    }
-    IrqData->name   = ((unsigned int)BSP_PCI_IRQ0 + int_vector);
-    IrqData->hdl    = rsPMCQ1Int;
-    IrqData->handle = boardData;
-    IrqData->on     = rsPMCQ1_scc_On;
-    IrqData->off    = rsPMCQ1_scc_Off;
-    IrqData->isOn   = rsPMCQ1_scc_except_always_enabled;
-
-    if (!BSP_install_rtems_shared_irq_handler (IrqData)) {
+    IrqData.name  = ((unsigned int)BSP_PCI_IRQ0 + int_vector);
+    IrqData.handle = boardData;
+    if (!BSP_install_rtems_shared_irq_handler (&IrqData)) {
        printk("Error installing interrupt handler!\n");
        rtems_fatal_error_occurred(1);
    }
@@ -517,10 +465,11 @@ unsigned int rsPMCQ1Init(void)
    /*
     * Enable PMCQ1 Interrupts from QSPAN-II
     */
-    *(volatile unsigned long *)(bridgeaddr + 0x600) = 0x00001000;
+        
+    *(unsigned long *)(bridgeaddr + 0x600) = 0x00001000;
    eieio();
-    Processor_Synchronize();
-    *(volatile unsigned long *)(bridgeaddr + 0x604) |= 0x00001000;
+    *(unsigned long *)(bridgeaddr + 0x604) |= 0x00001000;
+
    eieio();
  }

@@ -563,9 +512,9 @@ unsigned int rsPMCQ1Commission( unsigned long busNo, unsigned long slotNo )
     * A real PMCQ1 also has the sub vendor ID set up.
     */
    if ((busNo == 0) && (slotNo == 1)) {
-      *(volatile unsigned long *)rsPMCQ1eeprom = 0;
+      *(unsigned long *)rsPMCQ1eeprom = 0;
    } else {
-      *(volatile unsigned long *)rsPMCQ1eeprom = PCI_ID(PCI_VEN_ID_RADSTONE, PCI_DEV_ID_PMCQ1);
+      *(unsigned long *)rsPMCQ1eeprom = PCI_ID(PCI_VEN_ID_RADSTONE, PCI_DEV_ID_PMCQ1);
    }

    for (i = 0; i < 23; i++) {
@@ -609,27 +558,20 @@ unsigned int rsPMCQ1Commission( unsigned long busNo, unsigned long slotNo )

 uint32_t PMCQ1_Read_EPLD( uint32_t base, uint32_t reg )
 {
-  uint32_t           data;
-  volatile uint32_t *ptr;
+  uint32_t data;

-  Processor_Synchronize();
-  ptr =  (volatile uint32_t *)(base + reg);
-  data =  *ptr ;
+  data = ( *((unsigned long *) (base + reg)) );
 #ifdef DEBUG_360
-  printk("EPLD Read 0x%x: 0x%08x\n", ptr, data );
+  printk("EPLD Read 0x%x: 0x%08x\n", reg + base, data );
 #endif
  return data;
 }

 void PMCQ1_Write_EPLD( uint32_t base, uint32_t reg, uint32_t data )
 {
-  volatile uint32_t *ptr;
-
-  ptr = (volatile uint32_t *) (base + reg);
-  *ptr = data;
-  Processor_Synchronize();
+  *((unsigned long *) (base + reg)) = data;
 #ifdef DEBUG_360
-  printk("EPLD Write 0x%x: 0x%08x\n", ptr, data );
+  printk("EPLD Write 0x%x: 0x%08x\n", reg+base, data );
 #endif
 }

--- a/c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.h
+++ b/c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.h
@@ -30,8 +30,8 @@
   01a,20Dec00,jpb         created
 */

-#ifndef __RSPMCQ1_H
-#define __RSPMCQ1_H
+#ifndef __INCPMCQ1H
+#define __INCPMCQ1H

 /*
 * PMCQ1 definitions
@@ -95,6 +95,10 @@
 #define PMCQ1_MINIACE_MEM       0x00100000
 #define PMCQ1_RAM               0x00200000

+/*
+#define PMCQ1_Read_EPLD( _base, _reg ) ( *((unsigned long *) ((unsigned32)_base + _reg)) )
+#define PMCQ1_Write_EPLD( _base, _reg, _data ) *((unsigned long *) ((unsigned32)_base + _reg)) = _data
+*/
 uint32_t PMCQ1_Read_EPLD( uint32_t base, uint32_t reg );
 void     PMCQ1_Write_EPLD( uint32_t base, uint32_t reg, uint32_t data );

@@ -104,7 +108,7 @@ void     PMCQ1_Write_EPLD( uint32_t base, uint32_t reg, uint32_t data );

 #define QSPAN2_INT_STATUS	0x00000600

-typedef void (*PMCQ1_FUNCTION_PTR) (void *);
+typedef void (*FUNCION_PTR) (int);

 #define PCI_ID(v, d) ((d << 16) | v)

@@ -121,16 +125,16 @@ typedef void (*PMCQ1_FUNCTION_PTR) (void *);

 typedef struct _PMCQ1BoardData 
 {
-    struct _PMCQ1BoardData              *pNext;     
-    unsigned long                       busNo;
-    unsigned long                       slotNo;
-    unsigned long                       funcNo;
-    unsigned long                       baseaddr;
-    unsigned long                       bridgeaddr;
-    PMCQ1_FUNCTION_PTR                  quiccInt;
-    void *                              quiccArg;
-    PMCQ1_FUNCTION_PTR                  maInt;
-    void *                              maArg;
+    struct _PMCQ1BoardData   		*pNext;     
+    unsigned long			busNo;
+    unsigned long			slotNo;
+    unsigned long			funcNo;
+    unsigned long			baseaddr;
+    unsigned long			bridgeaddr;
+    FUNCION_PTR				quiccInt;
+    int					quiccArg;
+    FUNCION_PTR				maInt;
+    int					maArg;
 } PMCQ1BoardData, *PPMCQ1BoardData;

 extern PPMCQ1BoardData  pmcq1BoardData;
@@ -142,18 +146,16 @@ extern unsigned int rsPMCQ1QuiccIntConnect(
  unsigned long         busNo, 
  unsigned long         slotNo, 
  unsigned long         funcNo, 
-  PMCQ1_FUNCTION_PTR    routine, 
-  void *                arg
+  FUNCION_PTR           routine, 
+  int                   arg
 );
 unsigned int rsPMCQ1Init();
 unsigned int rsPMCQ1MaIntConnect (
    unsigned long       busNo,  /* Pci Bus number of PMCQ1 */
    unsigned long       slotNo, /* Pci Slot number of PMCQ1 */
    unsigned long       funcNo, /* Pci Function number of PMCQ1 */
-    PMCQ1_FUNCTION_PTR  routine,/* interrupt routine */
-    void *              arg     /* argument to pass to interrupt routine */
+    FUNCION_PTR         routine,/* interrupt routine */
+    int                 arg     /* argument to pass to interrupt routine */
 );

-void rsPMCQ1ShowIntrStatus(void );
-
-#endif				/* __RSPMCQ1_H */
+#endif				/* __INCPMCQ1H */
--- a/c/src/lib/libbsp/powerpc/ep1a/include/bsp.h
+++ b/c/src/lib/libbsp/powerpc/ep1a/include/bsp.h
@@ -1,6 +1,6 @@
 /*
 *
- *  COPYRIGHT (c) 1989-2009.
+ *  COPYRIGHT (c) 1989-1999.
 *  On-Line Applications Research Corporation (OAR).
 *
 *  The license and distribution terms for this file may be
@@ -13,9 +13,6 @@
 #ifndef _BSP_H
 #define _BSP_H

-
-#define BSP_ZERO_WORKSPACE_AUTOMATICALLY TRUE
-
 #include <bspopts.h>

 #include <rtems.h>
--- a/c/src/lib/libbsp/powerpc/ep1a/irq/irq.h
+++ b/c/src/lib/libbsp/powerpc/ep1a/irq/irq.h
@@ -1,110 +0,0 @@
-/* 
- *
- *  This include file describe the data structure and the functions implemented
- *  by RTEMS to write interrupt handlers.
- *
- *  Copyright (C) 1999 valette@crf.canon.fr
- *
- *  This code is heavilly inspired by the public specification of STREAM V2
- *  that can be found at :
- *
- *      <http://www.chorus.com/Documentation/index.html> by following
- *  the STREAM API Specification Document link.
- *
- *  The license and distribution terms for this file may be
- *  found in found in the file LICENSE in this distribution or at
- *  http://www.rtems.com/license/LICENSE.
- *
- *  $Id$
- */
-
-#ifndef BSP_POWERPC_IRQ_H
-#define BSP_POWERPC_IRQ_H
-
-#define BSP_SHARED_HANDLER_SUPPORT      1
-#include <rtems/irq.h>
-
-/* PIC's command and mask registers */
-#define PIC_MASTER_COMMAND_IO_PORT 0x20 /* Master PIC command register */
-#define PIC_SLAVE_COMMAND_IO_PORT  0xa0 /* Slave PIC command register */
-#define PIC_MASTER_IMR_IO_PORT     0x21 /* Master PIC Interrupt Mask Register */
-#define PIC_SLAVE_IMR_IO_PORT      0xa1 /* Slave PIC Interrupt Mask Register */
-
-/* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */
-#define PIC_EOSI        0x60  /* End of Specific Interrupt (EOSI) */
-#define SLAVE_PIC_EOSI  0x62 /* End of Specific Interrupt (EOSI) for cascade */
-#define PIC_EOI         0x20  /* Generic End of Interrupt (EOI) */
-
-#ifndef ASM
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * rtems_irq_number Definitions
- */
-
-/*
- * ISA IRQ handler related definitions
- */
-#define BSP_ISA_IRQ_NUMBER         (16)
-#define BSP_ISA_IRQ_LOWEST_OFFSET  (0)
-#define BSP_ISA_IRQ_MAX_OFFSET \
-        (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1)
-/*
- * PCI IRQ handlers related definitions
- * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE
- */
-#define BSP_PCI_IRQ_NUMBER        (26)
-#define BSP_PCI_IRQ_LOWEST_OFFSET (BSP_ISA_IRQ_NUMBER)
-#define BSP_PCI_IRQ_MAX_OFFSET    \
-        (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1)
-
-/*
- * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt
- * handler might be connected
- */
-#define BSP_PROCESSOR_IRQ_NUMBER        (1)
-#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1)
-#define BSP_PROCESSOR_IRQ_MAX_OFFSET \
-        (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
-/*
- * Misc vectors for OPENPIC irqs (IPI, timers)
- */
-#define BSP_MISC_IRQ_NUMBER        (8)
-#define BSP_MISC_IRQ_LOWEST_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1)
-#define BSP_MISC_IRQ_MAX_OFFSET \
-        (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1)
-/*
- * Summary
- */
-#define BSP_IRQ_NUMBER      (BSP_MISC_IRQ_MAX_OFFSET + 1)
-#define BSP_LOWEST_OFFSET   (BSP_ISA_IRQ_LOWEST_OFFSET)
-#define BSP_MAX_OFFSET      (BSP_MISC_IRQ_MAX_OFFSET)
-
-
-/*
- * Some PCI IRQ symbolic name definition
- */
-#define BSP_PCI_IRQ0      (BSP_PCI_IRQ_LOWEST_OFFSET)
-
-/*
- * Some Processor execption handled as RTEMS IRQ symbolic name definition
- */
-#define BSP_DECREMENTER   (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
-
-/*
- * Type definition for RTEMS managed interrupts
- */
-typedef unsigned short rtems_i8259_masks;
-extern  volatile rtems_i8259_masks i8259s_cache;
-
-/* Stuff in irq_supp.h should eventually go into <rtems/irq.h> */
-#include <bsp/irq_supp.h>
-
-#ifdef __cplusplus
-};
-#endif
-
-#endif
-#endif
--- a/c/src/lib/libbsp/powerpc/ep1a/irq/irq_init.c
+++ b/c/src/lib/libbsp/powerpc/ep1a/irq/irq_init.c
@@ -5,13 +5,13 @@
 *
 *  CopyRight (C) 1999 valette@crf.canon.fr
 *
- *  Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com>
- *  to make it valid for MVME2300 Motorola boards.
+ * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com>
+ * to make it valid for MVME2300 Motorola boards.
 *
- *  Till Straumann <strauman@slac.stanford.edu>, 12/20/2001:
- *  Use the new interface to openpic_init
+ * Till Straumann <strauman@slac.stanford.edu>, 12/20/2001:
+ * Use the new interface to openpic_init
 *
- *  COPYRIGHT (c) 1989-2009.
+ *  COPYRIGHT (c) 1989-1999.
 *  On-Line Applications Research Corporation (OAR).
 *
 *  The license and distribution terms for this file may be
@@ -32,91 +32,74 @@
 #include <bsp/motorola.h>
 #include <rtems/bspIo.h>

-#if 0 
-#define TRACE_IRQ_INIT 1   /* XXX */
-#endif
+/*
+#define SHOW_ISA_PCI_BRIDGE_SETTINGS
+*/
+#define TRACE_IRQ_INIT

-typedef struct {
-  unsigned char bus;	/* few chance the PCI/ISA bridge is not on first bus but ... */
-  unsigned char device;
-  unsigned char function;
-} pci_isa_bridge_device;
+/*
+ * default on/off function
+ */
+static void nop_func(void){}
+/*
+ * default isOn function
+ */
+static int not_connected(void) {return 0;}
+/*
+ * default possible isOn function
+ */
+static int connected(void) {return 1;}

-pci_isa_bridge_device* via_82c586 = 0;
-#if 0
-static pci_isa_bridge_device bridge;
-#endif
-
-
-
-extern unsigned int external_exception_vector_prolog_code_size[];
-extern void external_exception_vector_prolog_code();
-extern unsigned int decrementer_exception_vector_prolog_code_size[];
-extern void decrementer_exception_vector_prolog_code();
-
-
-static void IRQ_Default_rtems_irq_hdl( rtems_irq_hdl_param ptr ) { printk("IRQ_Default_rtems_irq_hdl\n"); }
-static void IRQ_Default_rtems_irq_enable (const struct __rtems_irq_connect_data__ *ptr)   {}
-static void IRQ_Default_rtems_irq_disable(const struct __rtems_irq_connect_data__ *ptr)   {}
-static int  IRQ_Default_rtems_irq_is_enabled(const struct __rtems_irq_connect_data__ *ptr){ return 1; }
 static rtems_irq_connect_data     	rtemsIrq[BSP_IRQ_NUMBER];
 static rtems_irq_global_settings     	initial_config;
 static rtems_irq_connect_data     	defaultIrq = {
-/*name,	 hdl				handle	on				off				isOn */
-  0,	 IRQ_Default_rtems_irq_hdl,	NULL,	IRQ_Default_rtems_irq_enable,	IRQ_Default_rtems_irq_disable,	IRQ_Default_rtems_irq_is_enabled
+  /* vectorIdex,	 hdl		, handle	, on		, off		, isOn */
+  0, 			 nop_func	, NULL		, nop_func	, nop_func	, not_connected
 };
-
-
-/*
- *  If the BSP_IRQ_NUMBER changes the following if will force the tables to be corrected.
- */
-#if ( (BSP_ISA_IRQ_NUMBER == 16)      && \
-      (BSP_PCI_IRQ_NUMBER == 26)      && \
-      (BSP_PROCESSOR_IRQ_NUMBER == 1) && \
-      (BSP_MISC_IRQ_NUMBER == 8) )
-
-
 static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={
  /*
-   * ISA interrupts.
+   * actual rpiorities for interrupt :
+   *	0   means that only current interrupt is masked
+   *	255 means all other interrupts are masked
   */
-  0, 0,
-  (OPENPIC_NUM_PRI-1),
+  /*
+   * ISA interrupts.
+   * The second entry has a priority of 255 because
+   * it is the slave pic entry and is should always remain
+   * unmasked.
+   */
+  0,0,
+  255,
  0, 0, 0, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
-
  /*
   * PCI Interrupts
   */
-  8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 
-  8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 
-
+  8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, /* for raven prio 0 means unactive... */
  /*
   * Processor exceptions handled as interrupts
   */
-  8,
- 
-  8, 8, 8, 8, 8, 8, 8, 8
+  0
 };

-static unsigned char mpc8245_openpic_initpolarities[] = {
+static unsigned char mcp750_openpic_initpolarities[] = {
    1,  /*  0 8259 cascade */
-    0,	/*  1 */
-    0,  /*  2 */
-    0,  /*  3 */
-    0,  /*  4 */
-    0,  /*  5 */
-    0,  /*  6 */
-    0,  /*  7 */
-    0,  /*  8 */
-    0,  /*  9 */
-    0,  /* 10 */
-    0,  /* 11 */
-    0,  /* 12 */
-    0,  /* 13 */
-    0,  /* 14 */
-    0,  /* 15 */
-    0,  /* 16 */
-    0,  /* 17 */
+    0,	/*  1 all the rest of them */
+    0,  /*  2 all the rest of them */
+    0,  /*  3 all the rest of them */
+    0,  /*  4 all the rest of them */
+    0,  /*  5 all the rest of them */
+    0,  /*  6 all the rest of them */
+    0,  /*  7 all the rest of them */
+    0,  /*  8 all the rest of them */
+    0,  /*  9 all the rest of them */
+    0,  /* 10 all the rest of them */
+    0,  /* 11 all the rest of them */
+    0,  /* 12 all the rest of them */
+    0,  /* 13 all the rest of them */
+    0,  /* 14 all the rest of them */
+    0,  /* 15 all the rest of them */
+    0,  /* 16 all the rest of them */
+    0,  /* 17 all the rest of them */
    1,  /* 18 all the rest of them */
    1,  /* 19 all the rest of them */
    1,  /* 20 all the rest of them */
@@ -125,78 +108,25 @@ static unsigned char mpc8245_openpic_initpolarities[] = {
    1,  /* 23 all the rest of them */
    1,  /* 24 all the rest of them */
    1,  /* 25 all the rest of them */
-    1,  /* 26 all the rest of them */
-    1,	/* 27 all the rest of them */
-    1,  /* 28 all the rest of them */
-    1,  /* 29 all the rest of them */
-    1,  /* 30 all the rest of them */
-    1,  /* 31 all the rest of them */
-    1,  /* 32 all the rest of them */
-    1,  /* 33 all the rest of them */
-    1,  /* 34 all the rest of them */
-    1,  /* 35 all the rest of them */
-    1,  /* 36 all the rest of them */
-    1,  /* 37 all the rest of them */
-    1,  /* 38 all the rest of them */
-    1,  /* 39 all the rest of them */
-    1,  /* 40 all the rest of them */
-    1,  /* 41 all the rest of them */
-    1,  /* 42 all the rest of them */
-    1,  /* 43 all the rest of them */
-    1,  /* 44 all the rest of them */
-    1,  /* 45 all the rest of them */
-    1,  /* 46 all the rest of them */
-    1,  /* 47 all the rest of them */
-    1,  /* 48 all the rest of them */
-    1,  /* 49 all the rest of them */
-    1,  /* 50 all the rest of them */
-    1,  /* 51 all the rest of them */
-
 };

-static unsigned char mpc8245_openpic_initsenses[] = {
-    1,	/* 0  */
-    0,	/* 1  */
-    1,	/* 2  */
-    1,	/* 3  */
-    1,	/* 4  */
-    1,	/* 5  */
-    1,	/* 6  */
-    1,	/* 7  */
-    1,	/* 8  */
-    1,	/* 9  */
-    1,	/*10  */
-    1,	/*11  */
-    1,	/*12  */
-    1,	/*13  */
-    1,	/*14  */
-    1,	/*15  */
-    1,
-    1, 
-    1,
-    1,
-    1,
-    1,
-    1,
-    1,
-    1,
-    1,
-    1,
-    1,
-    1,
-    1,
-    1,
-    1,
-    1,
-    1,
-    1,
-    1,
-    1,
-    1,
-    1,
-    1,
-    1,
-    1,
+static unsigned char mcp750_openpic_initsenses[] = {
+    1,	/* 0 MCP750_INT_PCB(8259) */
+    0,	/* 1 MCP750_INT_FALCON_ECC_ERR */
+    1,	/* 2 MCP750_INT_PCI_ETHERNET */
+    1,	/* 3 MCP750_INT_PCI_PMC */
+    1,	/* 4 MCP750_INT_PCI_WATCHDOG_TIMER1 */
+    1,	/* 5 MCP750_INT_PCI_PRST_SIGNAL */
+    1,	/* 6 MCP750_INT_PCI_FALL_SIGNAL */
+    1,	/* 7 MCP750_INT_PCI_DEG_SIGNAL */
+    1,	/* 8 MCP750_INT_PCI_BUS1_INTA */
+    1,	/* 9 MCP750_INT_PCI_BUS1_INTB */
+    1,	/*10 MCP750_INT_PCI_BUS1_INTC */
+    1,	/*11 MCP750_INT_PCI_BUS1_INTD */
+    1,	/*12 MCP750_INT_PCI_BUS2_INTA */
+    1,	/*13 MCP750_INT_PCI_BUS2_INTB */
+    1,	/*14 MCP750_INT_PCI_BUS2_INTC */
+    1,	/*15 MCP750_INT_PCI_BUS2_INTD */
    1,
    1, 
    1,
@@ -208,7 +138,6 @@ static unsigned char mpc8245_openpic_initsenses[] = {
    1,
    1
 };
-#endif

  /*
   * This code assumes the exceptions management setup has already
@@ -218,41 +147,24 @@ static unsigned char mpc8245_openpic_initsenses[] = {
   */
 void BSP_rtems_irq_mng_init(unsigned cpuId)
 {
-  int                           i;
+  int i;

  /*
   * First initialize the Interrupt management hardware
   */
 #ifdef TRACE_IRQ_INIT  
-  uint32_t                      msr;
-
-  _CPU_MSR_GET( msr );
-  printk("BSP_rtems_irq_mng_init: Initialize openpic compliant device with MSR %x \n", msr);
-  printk(" BSP_ISA_IRQ_NUMBER %d\n",BSP_ISA_IRQ_NUMBER );
-  printk(" BSP_ISA_IRQ_LOWEST_OFFSET %d\n",BSP_ISA_IRQ_LOWEST_OFFSET );
-  printk(" BSP_ISA_IRQ_MAX_OFFSET %d\n", BSP_ISA_IRQ_MAX_OFFSET);
-  printk(" BSP_PCI_IRQ_NUMBER %d\n",BSP_PCI_IRQ_NUMBER );
-  printk(" BSP_PCI_IRQ_LOWEST_OFFSET %d\n",BSP_PCI_IRQ_LOWEST_OFFSET );
-  printk(" BSP_PCI_IRQ_MAX_OFFSET %d\n",BSP_PCI_IRQ_MAX_OFFSET );
-  printk(" BSP_PROCESSOR_IRQ_NUMBER %d\n",BSP_PROCESSOR_IRQ_NUMBER );
-  printk(" BSP_PROCESSOR_IRQ_LOWEST_OFFSET %d\n",BSP_PROCESSOR_IRQ_LOWEST_OFFSET );
-  printk(" BSP_PROCESSOR_IRQ_MAX_OFFSET %d\n", BSP_PROCESSOR_IRQ_MAX_OFFSET);
-  printk(" BSP_MISC_IRQ_NUMBER %d\n", BSP_MISC_IRQ_NUMBER);
-  printk(" BSP_MISC_IRQ_LOWEST_OFFSET %d\n", BSP_MISC_IRQ_LOWEST_OFFSET);
-  printk(" BSP_MISC_IRQ_MAX_OFFSET %d\n",BSP_MISC_IRQ_MAX_OFFSET );
-  printk(" BSP_IRQ_NUMBER %d\n",BSP_IRQ_NUMBER );
-  printk(" BSP_LOWEST_OFFSET %d\n",BSP_LOWEST_OFFSET );
-  printk(" BSP_MAX_OFFSET %d\n",BSP_MAX_OFFSET );
-#endif
-       
+  printk("Going to initialize openpic compliant device\n");
+#endif       
  /* FIXME (t.s.): we should probably setup the EOI delay by
   * passing a non-zero 'epic_freq' argument (frequency of the
   * EPIC serial interface) but I don't know the value on this
   * board (8245 SDRAM freq, IIRC)...
-   *
-   * When tested this appears to work correctly.
   */
-  openpic_init(1, mpc8245_openpic_initpolarities, mpc8245_openpic_initsenses, 0, 0, 0);
+  openpic_init(1, mcp750_openpic_initpolarities, mcp750_openpic_initsenses, 0, 16, 0 /* epic_freq */);
+
+#ifdef TRACE_IRQ_INIT  
+  printk("Going to initialize the PCI/ISA bridge IRQ related setting (VIA 82C586)\n");
+#endif

  /*
   * Initialize Rtems management interrupt table
@@ -263,11 +175,7 @@ void BSP_rtems_irq_mng_init(unsigned cpuId)
    for (i = 0; i < BSP_IRQ_NUMBER; i++) {
      rtemsIrq[i]      = defaultIrq;
      rtemsIrq[i].name = i;
-#ifdef BSP_SHARED_HANDLER_SUPPORT
-      rtemsIrq[i].next_handler = NULL;
-#endif
    }
-
    /*
     * Init initial Interrupt management config
     */
@@ -277,20 +185,14 @@ void BSP_rtems_irq_mng_init(unsigned cpuId)
    initial_config.irqBase	= BSP_LOWEST_OFFSET;
    initial_config.irqPrioTbl	= irqPrioTable;

-
-#ifdef TRACE_IRQ_INIT  
-    _CPU_MSR_GET( msr );
-    printk("BSP_rtems_irq_mng_init: Set initial configuration with MSR %x\n", msr);
-#endif
+printk("Call BSP_rtems_irq_mngt_set\n");
    if (!BSP_rtems_irq_mngt_set(&initial_config)) {
      /*
       * put something here that will show the failure...
       */
      BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n");
-    }  else {
-      printk(" Initialized RTEMS Interrupt Manager\n");
    }
-
+  
 #ifdef TRACE_IRQ_INIT  
    printk("RTEMS IRQ management is now operationnal\n");
 #endif
--- a/c/src/lib/libbsp/powerpc/ep1a/irq/openpic_xxx_irq.c
+++ b/c/src/lib/libbsp/powerpc/ep1a/irq/openpic_xxx_irq.c
@@ -23,7 +23,7 @@
 #include <bsp/vectors.h>
 #include <stdlib.h>

-#include <rtems/bspIo.h> 
+#include <rtems/bspIo.h> /* for printk */
 #define RAVEN_INTR_ACK_REG 0xfeff0030

 #ifdef BSP_PCI_ISA_BRIDGE_IRQ
@@ -41,31 +41,28 @@ rtems_i8259_masks 	irq_mask_or_tbl[BSP_IRQ_NUMBER];
 /*
 * default handler connected on each irq after bsp initialization
 */
-static rtems_irq_connect_data	   default_rtems_entry;
-static rtems_irq_connect_data*	   rtems_hdl_tbl;
+static rtems_irq_connect_data	default_rtems_entry;

+static rtems_irq_connect_data*		rtems_hdl_tbl;
+
+#ifdef BSP_PCI_ISA_BRIDGE_IRQ
 /*
 * Check if IRQ is an ISA IRQ
 */
 static inline int is_isa_irq(const rtems_irq_number irqLine)
 {
-  if  ( BSP_ISA_IRQ_NUMBER == 0 )
-    return FALSE;
-
-  return (((int) irqLine <= BSP_ISA_IRQ_MAX_OFFSET) &&
+  return (((int) irqLine <= BSP_ISA_IRQ_MAX_OFFSET) &
 	  ((int) irqLine >= BSP_ISA_IRQ_LOWEST_OFFSET)
 	 );
 }
+#endif

 /*
 * Check if IRQ is an OPENPIC IRQ
 */
 static inline int is_pci_irq(const rtems_irq_number irqLine)
 {
-  if ( BSP_PCI_IRQ_NUMBER == 0 )
-    return FALSE;
-
-  return (((int) irqLine <= BSP_PCI_IRQ_MAX_OFFSET) &&
+  return (((int) irqLine <= BSP_PCI_IRQ_MAX_OFFSET) &
 	  ((int) irqLine >= BSP_PCI_IRQ_LOWEST_OFFSET)
 	 );
 }
@@ -101,34 +98,46 @@ static void compute_i8259_masks_from_prio (rtems_irq_global_settings* config)
 }
 #endif

-void BSP_enable_irq_at_pic(const rtems_irq_number name)
+void
+BSP_enable_irq_at_pic(const rtems_irq_number name)
 {
-  if (is_isa_irq(name)) {
-    printk("BSP_enable_irq_at_pic: called with isa irq\n");
-  }
-  if (is_pci_irq(name)) {
-    /*
-     * enable interrupt at OPENPIC level.
-     */
-    openpic_enable_irq ( ((int)name - BSP_PCI_IRQ_LOWEST_OFFSET) + 16 );  
-  }
+#ifdef BSP_PCI_ISA_BRIDGE_IRQ
+    if (is_isa_irq(name)) {
+      /*
+       * Enable interrupt at PIC level
+       */
+printk("ERROR BSP_irq_enable_at_i8259s Being Called for %d\n", (int)name);
+      BSP_irq_enable_at_i8259s ((int) name);
+    }
+#endif
+    
+    if (is_pci_irq(name)) {
+      /*
+       * Enable interrupt at OPENPIC level
+       */
+printk(" openpic_enable_irq %d\n", (int)name );
+       openpic_enable_irq ((int) name);
+    }
 }

-int BSP_disable_irq_at_pic(const rtems_irq_number name)
+int
+BSP_disable_irq_at_pic(const rtems_irq_number name)
 {
+#ifdef BSP_PCI_ISA_BRIDGE_IRQ
    if (is_isa_irq(name)) {
      /*
       * disable interrupt at PIC level
       */
-      printk("BSP_disable_irq_at_pic: called with isa irq\n");
+      return BSP_irq_disable_at_i8259s ((int) name);
    }
+#endif
    if (is_pci_irq(name)) {
      /*
       * disable interrupt at OPENPIC level
       */
-      return openpic_disable_irq (((int) name - BSP_PCI_IRQ_LOWEST_OFFSET) + 16  );
+      return openpic_disable_irq ((int) name );
    }
-    return -1;
+	return -1;
 }

 /*
@@ -137,23 +146,23 @@ int BSP_disable_irq_at_pic(const rtems_irq_number name)
 int BSP_setup_the_pic(rtems_irq_global_settings* config)
 {
    int i;
-
   /*
    * Store various code accelerators
    */
    default_rtems_entry	= config->defaultEntry;
-    rtems_hdl_tbl 	= config->irqHdlTbl;
-    
+    rtems_hdl_tbl 		= config->irqHdlTbl;
+
    /*
     * set up internal tables used by rtems interrupt prologue
     */
+#if 0
 #ifdef BSP_PCI_ISA_BRIDGE_IRQ
    /*
     * start with ISA IRQ
     */
    compute_i8259_masks_from_prio (config);

-    for (i=BSP_ISA_IRQ_LOWEST_OFFSET; (i < (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER)); i++) {
+    for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) {
      if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
         BSP_irq_enable_at_i8259s (i);
      }
@@ -168,6 +177,7 @@ int BSP_setup_the_pic(rtems_irq_global_settings* config)
 		 */
 		BSP_irq_enable_at_i8259s (2);
 	}
+#endif
 #endif

    /*
@@ -180,26 +190,27 @@ int BSP_setup_the_pic(rtems_irq_global_settings* config)
      openpic_set_source_priority(i - BSP_PCI_IRQ_LOWEST_OFFSET,
 				  config->irqPrioTbl[i]);
      if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
-         openpic_enable_irq ((int) i - BSP_PCI_IRQ_LOWEST_OFFSET);
+         openpic_enable_irq ((int) i );
      }
      else {
-         openpic_disable_irq ((int) i - BSP_PCI_IRQ_LOWEST_OFFSET);
+         openpic_disable_irq ((int) i );
      }
    }

 #ifdef BSP_PCI_ISA_BRIDGE_IRQ
 	if ( BSP_ISA_IRQ_NUMBER > 0 ) {
-          /*
-           * Must enable PCI/ISA bridge IRQ
-           */
-          openpic_enable_irq (0);
+    	/*
+	     * Must enable PCI/ISA bridge IRQ
+	     */
+    	openpic_enable_irq (0);
 	}
 #endif
-    
+
    return 1;
 }

 int _BSP_vme_bridge_irq = -1;
+
 unsigned BSP_spuriousIntr = 0;

 /*
@@ -213,24 +224,29 @@ int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum)
  register unsigned oldMask = 0;	      /* old isa pic masks */
  register unsigned newMask;                  /* new isa pic masks */
 #endif
+
  if (excNum == ASM_DEC_VECTOR) {
-    bsp_irq_dispatch_list_base(rtems_hdl_tbl, BSP_DECREMENTER, default_rtems_entry.hdl);
+/* printk("ASM_DEC_VECTOR\n"); */
+  	bsp_irq_dispatch_list(rtems_hdl_tbl, BSP_DECREMENTER, default_rtems_entry.hdl);
+
    return 0;

  }
  irq = openpic_irq(0);
  if (irq == OPENPIC_VEC_SPURIOUS) {
-    printk("OPENPIC_VEC_SPURIOUS interrupt %d\n", OPENPIC_VEC_SPURIOUS );
-    ++BSP_spuriousIntr;
+/* printk("OPENPIC_VEC_SPURIOUS interrupt %d\n", OPENPIC_VEC_SPURIOUS ); */
+     ++BSP_spuriousIntr;
    return 0;
  }

  /* some BSPs might want to use a different numbering... */
-  irq = irq - OPENPIC_VEC_SOURCE ;
+  irq = irq - OPENPIC_VEC_SOURCE + BSP_PCI_IRQ_LOWEST_OFFSET;
+/* printk("OpenPic Irq: %d\n", irq); */

 #ifdef BSP_PCI_ISA_BRIDGE_IRQ
  isaIntr = (irq == BSP_PCI_ISA_BRIDGE_IRQ);
  if (isaIntr)  {
+/* printk("BSP_PCI_ISA_BRIDGE_IRQ\n"); */
    /*
     * Acknowledge and read 8259 vector
     */
@@ -248,28 +264,30 @@ int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum)
  }
 #endif

+
  /* dispatch handlers */
-  bsp_irq_dispatch_list_base(rtems_hdl_tbl, irq, default_rtems_entry.hdl);
+/* printk("dispatch\n"); */
+irq -=16;
+  bsp_irq_dispatch_list(rtems_hdl_tbl, irq, default_rtems_entry.hdl);
+/* printk("Back from dispatch\n"); */

 #ifdef BSP_PCI_ISA_BRIDGE_IRQ
-  if (isaIntr)  {
+  if (isaIntr)  {\
    i8259s_cache = oldMask;
    outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff);
    outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
  }
  else
 #endif
-
  {
 #ifdef BSP_PCI_VME_DRIVER_DOES_EOI
-    /* leave it to the VME bridge driver to do EOI, so
+	/* leave it to the VME bridge driver to do EOI, so
     * it can re-enable the openpic while handling
     * VME interrupts (-> VME priorities in software)
-     */
-    if (_BSP_vme_bridge_irq != irq)
+	 */
+	if (_BSP_vme_bridge_irq != irq)
 #endif
-      openpic_eoi(0);
+    		openpic_eoi(0);
  }
  return 0;
-
 }
--- a/c/src/lib/libbsp/powerpc/ep1a/preinstall.am
+++ b/c/src/lib/libbsp/powerpc/ep1a/preinstall.am
@@ -57,9 +57,9 @@ $(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds
 PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds

-$(PROJECT_INCLUDE)/bsp/pci.h: ../../powerpc/shared/pci/pci.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/pci.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/pci.h
+$(PROJECT_INCLUDE)/bsp/uart.h: ../../powerpc/shared/console/uart.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/uart.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/uart.h

 $(PROJECT_INCLUDE)/bsp/motorola.h: ../../powerpc/shared/motorola/motorola.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/motorola.h
@@ -81,7 +81,15 @@ $(PROJECT_INCLUDE)/bsp/rsPMCQ1.h: console/rsPMCQ1.h $(PROJECT_INCLUDE)/bsp/$(dir
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/rsPMCQ1.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/rsPMCQ1.h

-$(PROJECT_INCLUDE)/bsp/irq.h: irq/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+$(PROJECT_INCLUDE)/bsp/openpic.h: ../../powerpc/shared/openpic/openpic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/openpic.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/openpic.h
+
+$(PROJECT_INCLUDE)/bsp/pci.h: ../../powerpc/shared/pci/pci.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/pci.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/pci.h
+
+$(PROJECT_INCLUDE)/bsp/irq.h: ../../powerpc/shared/irq/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h

@@ -97,10 +105,6 @@ $(PROJECT_INCLUDE)/bsp/irq_supp.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bsps
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq_supp.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq_supp.h

-$(PROJECT_INCLUDE)/bsp/openpic.h: ../../powerpc/shared/openpic/openpic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/openpic.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/openpic.h
-
 $(PROJECT_INCLUDE)/bsp/vmeUniverse.h: ../../shared/vmeUniverse/vmeUniverse.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vmeUniverse.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vmeUniverse.h
--- a/c/src/lib/libbsp/powerpc/ep1a/start/start.S
+++ b/c/src/lib/libbsp/powerpc/ep1a/start/start.S
@@ -114,10 +114,6 @@ __rtems_entry_point:
 	lis	sp,__stack@h
 	ori	sp,sp,__stack@l

-        lis	r13,_SDA_BASE_@ha
-	la	r13,_SDA_BASE_@l(r13)  		/* Read-write small data */
-
-
 	/* set up initial stack frame */
 	addi	sp,sp,-4		/* make sure we don't overwrite debug mem */
 	lis	r0,0
--- a/c/src/lib/libbsp/powerpc/ep1a/startup/bspstart.c
+++ b/c/src/lib/libbsp/powerpc/ep1a/startup/bspstart.c
@@ -4,7 +4,7 @@
 *  The generic CPU dependent initialization has been performed
 *  before this routine is invoked.
 *
- *  COPYRIGHT (c) 1989-2009.
+ *  COPYRIGHT (c) 1989-2007.
 *  On-Line Applications Research Corporation (OAR).
 *
 *  The license and distribution terms for this file may be
@@ -14,7 +14,7 @@
 *  $Id$
 */

-#define SHOW_MORE_INIT_SETTINGS
+#warning The interrupt disable mask is now stored in SPRG0, please verify that this is compatible to this BSP (see also bootcard.c).

 #include <string.h>

@@ -33,7 +33,6 @@
 #include <libcpu/cpuIdent.h>
 #include <bsp/vectors.h>
 #include <rtems/powerpc/powerpc.h>
-#include <bsp/ppc_exc_bspsupp.h>

 extern unsigned long __rtems_end[];
 extern void L1_caches_enables(void);
@@ -94,13 +93,6 @@ uint32_t VME_Slot1 = FALSE;
 extern int   RAM_END;  
 unsigned int BSP_mem_size = (unsigned int)&RAM_END;

-/*
- * Where the heap starts; is used by bsp_pretasking_hook;
- */
-unsigned int BSP_heap_start;
-uint32_t BSP_intrStackStart;
-uint32_t BSP_intrStackSize;
-
 /*
 * PCI Bus Frequency
 */
@@ -113,15 +105,13 @@ unsigned int BSP_processor_frequency;

 /*
 * Time base divisior (how many tick for 1 second).
- * Calibrated by outputing a 20 ms pulse.
 */
-unsigned int BSP_time_base_divisor = 1320;  
+unsigned int BSP_time_base_divisor = 1000;  /* XXX - Just a guess */

 /*
 * system init stack 
 */
-#define INIT_STACK_SIZE 0x2000
-#define INTR_STACK_SIZE rtems_configuration_get_interrupt_stack_size()
+#define INIT_STACK_SIZE 0x1000

 void BSP_panic(char *s)
 {
@@ -180,38 +170,6 @@ void BSP_FLASH_set_page(
 
 void bsp_libc_init( void *, uint32_t, int );

-
-void ShowMemoryLayout(){
-  extern unsigned long __bss_start[], __SBSS_START__[], __SBSS_END__[];
-  extern unsigned long __SBSS2_START__[], __SBSS2_END__[];
-  extern unsigned long __bss_start[];
-  extern unsigned long __bss_end[];
-  extern unsigned long __stack[];
-  extern unsigned long __stackLow[];
-  extern uint32_t end;
-  /* extern uint32_t BSP_intrStackStart; */
-  /* extern uint32_t BSP_intrStackSize; */
-  /* Configuration.work_space_start     */
-  /* rtems_configuration_get_work_space_size() */
-  printk(" bss start: 0x%x\n", __bss_start);
-  printk(" bss end: 0x%x\n",  __bss_end);
-  printk(" rtems end: 0x%x\n",  __rtems_end);
-  printk(" stack    : 0x%x\n",  __stack);
-  printk(" stack Low: 0x%x\n",  __stackLow);
-  printk(" end      : 0x%x\n",  &end);
-  printk(" Intr Stack: 0x%x\n", BSP_intrStackStart);
-  printk(" Intr Stack Size: 0x%x\n", BSP_intrStackSize);
-  printk(" Heap start: %x\n", BSP_heap_start);
-
-  printk(" workspace start: 0x%x\n", Configuration.work_space_start);
-  printk(" workspace size: 0x%x\n", rtems_configuration_get_work_space_size() );
-
-}
-
-
-
-
-
 /*
 *  Function:   bsp_pretasking_hook
 *  Created:    95/03/10
@@ -228,30 +186,28 @@ void ShowMemoryLayout(){
 
 void bsp_pretasking_hook(void)
 {
-  uint32_t        heap_start = BSP_heap_start;    
+  uint32_t        heap_start;    
  uint32_t        heap_size;
  uint32_t        heap_sbrk_spared;
+
  extern uint32_t _bsp_sbrk_init(uint32_t, uint32_t*);
-  extern uint32_t end;
+  
+  heap_start = ((uint32_t) __rtems_end) +
+    INIT_STACK_SIZE + rtems_configuration_get_interrupt_stack_size();
+  if (heap_start & (CPU_ALIGNMENT-1))
+    heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1);

-  heap_start = (BSP_heap_start + CPU_ALIGNMENT - 1) & ~(CPU_ALIGNMENT-1);
-  heap_size = (uint32_t) &RAM_END;
-  heap_size = heap_size - heap_start - Configuration.work_space_size;
-  heap_size &= 0xfffffff0;  /* keep it as a multiple of 16 bytes */
+  heap_size = (BSP_mem_size - heap_start) - rtems_configuration_get_work_space_size();

-#if 0  /*XXXXXXX */
-    heap_size = Configuration.work_space_start - (void *)&end;
-    heap_size &= 0xfffffff0;  /* keep it as a multiple of 16 bytes */
-#endif
+  heap_sbrk_spared=_bsp_sbrk_init(heap_start, &heap_size);

 #ifdef SHOW_MORE_INIT_SETTINGS
-  printk(" HEAP start 0x%x  size %x \n", 
-    heap_start, heap_size, 0 );
+  printk(" HEAP start %x  size %x (%x bytes spared for sbrk)\n", 
+    heap_start, heap_size, heap_sbrk_spared);
 #endif    

-  bsp_libc_init((void *)heap_start, heap_size, 0);
+  bsp_libc_init((void *) 0, heap_size, heap_sbrk_spared);
  rsPMCQ1Init();
-  ShowMemoryLayout();
 }

 void zero_bss()
@@ -276,8 +232,21 @@ void save_boot_params(RESIDUAL* r3, void *r4, void* r5, char *additional_boot_op
 unsigned int EUMBBAR;

 unsigned int get_eumbbar() {
-  out_le32( (uint32_t*)0xfec00000, 0x80000078 );
-  return in_le32( (uint32_t*)0xfee00000 );
+  register int a, e;
+
+  asm volatile( "lis %0,0xfec0; ori  %0,%0,0x0000": "=r" (a) );
+  asm volatile("sync");
+                                                                
+  asm volatile("lis %0,0x8000; ori %0,%0,0x0078": "=r"(e) ); 
+  asm volatile("stwbrx  %0,0x0,%1": "=r"(e): "r"(a));  
+  asm volatile("sync");
+
+  asm volatile("lis %0,0xfee0; ori %0,%0,0x0000": "=r" (a) ); 
+  asm volatile("sync");
+                                                         
+  asm volatile("lwbrx %0,0x0,%1": "=r" (e): "r" (a));
+  asm volatile("isync");
+  return e;
 }

 void Read_ep1a_config_registers( ppc_cpu_id_t myCpu ) {
@@ -348,7 +317,6 @@ void Read_ep1a_config_registers( ppc_cpu_id_t myCpu ) {
      BSP_bus_frequency       =  33000000;
      break;
  }
-  printk("Processor Frequency %d  Bus Frequency: %d\n", BSP_processor_frequency, BSP_bus_frequency );
 }

 /*
@@ -360,6 +328,8 @@ void Read_ep1a_config_registers( ppc_cpu_id_t myCpu ) {
 void bsp_start( void )
 {
  unsigned char *stack;
+  uint32_t intrStackStart;
+  uint32_t intrStackSize;
  unsigned char *work_space_start;
  ppc_cpu_id_t myCpu;
  ppc_cpu_revision_t myCpuRevision;
@@ -376,22 +346,15 @@ void bsp_start( void )
  EUMBBAR = get_eumbbar(); 
  printk("EUMBBAR 0x%08x\n", EUMBBAR );

-  /*
-   * Init MMU block address translation to enable hardware
-   * access
-   */
-  setdbat(1, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE);
-  setdbat(2, 0x80000000, 0x80000000, 0x10000000, IO_PAGE);
-  setdbat(3, 0x90000000, 0x90000000, 0x10000000, IO_PAGE);
-ShowBATS();
-
  /* 
   * Note this sets BSP_processor_frequency based upon register settings.
   * It must be done prior to setting up hooks.
   */
  Read_ep1a_config_registers( myCpu );
+
  bsp_clicks_per_usec = BSP_processor_frequency/(BSP_time_base_divisor * 1000);

+ShowBATS();
 #if 0   /* XXX - Add back in cache enable when we get this up and running!! */
  /*
   * enables L1 Cache. Note that the L1_caches_enables() codes checks for
@@ -400,35 +363,41 @@ ShowBATS();
  L1_caches_enables();
 #endif

+  /*
+   * the initial stack  has aready been set to this value in start.S
+   * so there is no need to set it in r1 again... It is just for info
+   * so that It can be printed without accessing R1.
+   */
+  stack = ((unsigned char*) __rtems_end) + INIT_STACK_SIZE - PPC_MINIMUM_STACK_FRAME_SIZE;
+
+ /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */
+  *((uint32_t *)stack) = 0;
+
  /*
   * Initialize the interrupt related settings.
   */
-  BSP_intrStackStart = (uint32_t) __rtems_end + INIT_STACK_SIZE;
-  BSP_intrStackSize = rtems_configuration_get_interrupt_stack_size();
-  BSP_heap_start = BSP_intrStackStart + BSP_intrStackSize;
-  printk("Interrupt Stack Start: 0x%x Size: 0x%x  Heap Start: 0x%x\n",
-    BSP_intrStackStart, BSP_intrStackSize, BSP_heap_start
-  );
-
-  /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */
-  *((uint32_t *)BSP_intrStackStart) = 0;
+  intrStackStart = (uint32_t) __rtems_end + INIT_STACK_SIZE;
+  intrStackSize = rtems_configuration_get_interrupt_stack_size();

  /*
   * Initialize default raw exception hanlders.
   */
-
-#ifdef SHOW_MORE_INIT_SETTINGS
-  printk("bsp_start: Initialize Exceptions\n");
-#endif  
-  ppc_exc_cache_wb_check = 0; 
  ppc_exc_initialize(
    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
-    BSP_intrStackStart,
-    BSP_intrStackSize
+    intrStackStart,
+    intrStackSize
  );

+  /*
+   * Init MMU block address translation to enable hardware
+   * access
+   */
+  setdbat(1, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE);
+  setdbat(3, 0x90000000, 0x90000000, 0x10000000, IO_PAGE);
+
+
 #ifdef SHOW_MORE_INIT_SETTINGS
-  printk("bsp_start: Going to start PCI buses scanning and initialization\n");
+  printk("Going to start PCI buses scanning and initialization\n");
 #endif  
  pci_initialize();

@@ -436,7 +405,7 @@ ShowBATS();
  printk("Number of PCI buses found is : %d\n", pci_bus_count());
 #endif
 #ifdef TEST_RAW_EXCEPTION_CODE  
-  printk("bsp_start: Testing exception handling Part 1\n");
+  printk("Testing exception handling Part 1\n");

  /*
   * Cause a software exception
@@ -446,45 +415,28 @@ ShowBATS();
  /*
   * Check we can still catch exceptions and returned coorectly.
   */
-  printk("bsp_start: Testing exception handling Part 2\n");
+  printk("Testing exception handling Part 2\n");
  __asm__ __volatile ("sc");
 #endif  

 #ifdef SHOW_MORE_INIT_SETTINGS
-  printk("bsp_start: rtems_configuration_get_work_space_size() = %x\n", 
+  printk("rtems_configuration_get_work_space_size() = %x\n", 
     rtems_configuration_get_work_space_size());
 #endif  
  work_space_start = 
-    (unsigned char *)&RAM_END - rtems_configuration_get_work_space_size();
+    (unsigned char *)BSP_mem_size - rtems_configuration_get_work_space_size();
+
  if ( work_space_start <= ((unsigned char *)__rtems_end) + 
        INIT_STACK_SIZE + rtems_configuration_get_interrupt_stack_size()) {
    printk( "bspstart: Not enough RAM!!!\n" );
    bsp_cleanup();
  }
+
  Configuration.work_space_start = work_space_start;
-#ifdef SHOW_MORE_INIT_SETTINGS
-  printk("bsp_start: workspace_start = 0x%x\n", 
-     work_space_start);
-#endif  
-
-  #if ( PPC_USE_DATA_CACHE )
-    #if DEBUG
-      printk("bsp_start: cache_enable\n");
-    #endif
-    instruction_cache_enable ();
-    data_cache_enable ();
-    #if DEBUG
-      printk("bsp_start: END PPC_USE_DATA_CACHE\n");
-    #endif
-  #endif
-

  /*
   * Initalize RTEMS IRQ system
   */
-#ifdef  SHOW_MORE_INIT_SETTINGS
-    printk("bspstart: Call BSP_rtems_irq_mng_init\n");
-#endif
  BSP_rtems_irq_mng_init(0);
  
  /* Activate the page table mappings only after
@@ -493,7 +445,7 @@ ShowBATS();
   */           
  if (pt) {
 #ifdef  SHOW_MORE_INIT_SETTINGS
-    printk("bspstart: Page table setup finished; will activate it NOW...\n");
+    printk("Page table setup finished; will activate it NOW...\n");
 #endif
    BSP_pgtbl_activate(pt);
  }
@@ -503,7 +455,7 @@ ShowBATS();
   * and IRQ subsystems...
   */
 #ifdef SHOW_MORE_INIT_SETTINGS
-  printk("bspstart: Going to initialize VME bridge\n");
+  printk("Going to initialize VME bridge\n");
 #endif
  /* VME initialization is in a separate file so apps which don't use
   * VME or want a different configuration may link against a customized
--- a/c/src/lib/libbsp/powerpc/ep1a/startup/linkcmds
+++ b/c/src/lib/libbsp/powerpc/ep1a/startup/linkcmds
@@ -152,9 +152,7 @@ SECTIONS
   *(COMMON)
   PROVIDE (__bss_end = .);
  }
-  . =  ALIGN(0x100);
-  PROVIDE (__stackLow = .);
-  . += 0x8000;
+  . =  ALIGN(8) + 0x8000;
  PROVIDE (__stack = .);
  _end = . ;
  __rtems_end = . ;
--- a/c/src/lib/libbsp/powerpc/ep1a/vme/VMEConfig.h
+++ b/c/src/lib/libbsp/powerpc/ep1a/vme/VMEConfig.h
@@ -77,8 +77,7 @@
 * at _VME_DRAM_OFFSET
 */
 #undef  _VME_DRAM_OFFSET
-/* #define _VME_DRAM_OFFSET                0xc0000000   */
-
+#define _VME_DRAM_OFFSET                0xc0000000  
 #define _VME_DRAM_32_OFFSET1		0x20000000
 #define _VME_DRAM_32_OFFSET2            0x20b00000
 #define _VME_DRAM_24_OFFSET1            0x00000000
--- a/c/src/lib/libbsp/powerpc/ep1a/vme/vmeconfig.c
+++ b/c/src/lib/libbsp/powerpc/ep1a/vme/vmeconfig.c
@@ -1,144 +0,0 @@
-/* $Id$ */
-
-/* Default VME bridge configuration - note that this file
- * is independent of the bridge driver/chip
- */
-
-/* 
- * Authorship
- * ----------
- * This software was created by
- *     Till Straumann <strauman@slac.stanford.edu>, 3/2002,
- * 	   Stanford Linear Accelerator Center, Stanford University.
- * 
- * Acknowledgement of sponsorship
- * ------------------------------
- * This software was produced by
- *     the Stanford Linear Accelerator Center, Stanford University,
- * 	   under Contract DE-AC03-76SFO0515 with the Department of Energy.
- * 
- * Government disclaimer of liability
- * ----------------------------------
- * Neither the United States nor the United States Department of Energy,
- * nor any of their employees, makes any warranty, express or implied, or
- * assumes any legal liability or responsibility for the accuracy,
- * completeness, or usefulness of any data, apparatus, product, or process
- * disclosed, or represents that its use would not infringe privately owned
- * rights.
- * 
- * Stanford disclaimer of liability
- * --------------------------------
- * Stanford University makes no representations or warranties, express or
- * implied, nor assumes any liability for the use of this software.
- * 
- * Stanford disclaimer of copyright
- * --------------------------------
- * Stanford University, owner of the copyright, hereby disclaims its
- * copyright and all other rights in this software.  Hence, anyone may
- * freely use it for any purpose without restriction.  
- * 
- * Maintenance of notices
- * ----------------------
- * In the interest of clarity regarding the origin and status of this
- * SLAC software, this and all the preceding Stanford University notices
- * are to remain affixed to any copy or derivative of this software made
- * or distributed by the recipient and are to be affixed to any copy of
- * software made or distributed by the recipient that contains a copy or
- * derivative of this software.
- * 
- * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
- */ 
-
-#include <bsp.h>
-#include <bsp/VME.h>
-#include <bsp/VMEConfig.h>
-#ifdef BSP_VME_BAT_IDX
-#include <libcpu/bat.h>
-#endif
-#include <rtems/bspIo.h>
-
-extern int BSP_VMEInit(void);
-extern int BSP_VMEIrqMgrInstall(void);
-
-/* Use a weak alias for the VME configuration.
- * This permits individual applications to override
- * this routine.
- * They may even create an 'empty'
- *
- *    void BSP_vme_config(void) {}
- *
- * which will avoid linking in the Universe driver
- * at all :-).
- */
-
-void BSP_vme_config(void) 
-     __attribute__ (( weak, alias("__BSP_EP1A_vme_config") ));
-
-void __BSP_EP1A_vme_config(void)
-{
-  if ( BSP_VMEInit() ) {
-	printk("Skipping VME initialization...\n");
-	return;
-  }
-
-#ifdef BSP_VME_BAT_IDX
-  printk("BSP_VME_BAT_IDX\n");
-  /* setup a PCI area to map the VME bus */
-  setdbat(BSP_VME_BAT_IDX,
-		  PCI_MEM_BASE + _VME_A32_WIN0_ON_PCI,
-		  PCI_MEM_BASE + _VME_A32_WIN0_ON_PCI,
-		  0x10000000,
-		  IO_PAGE);
-#endif
-
-  /* map VME address ranges */
-  BSP_VMEOutboundPortCfg(
-	0,
-	VME_AM_EXT_SUP_DATA,
-	_VME_A32_WIN0_ON_VME,
-	_VME_A32_WIN0_ON_PCI,
-	0x0f000000);
-  BSP_VMEOutboundPortCfg(
-	1,
-	VME_AM_STD_SUP_DATA,
-	0x00000000,
-	_VME_A24_ON_PCI,
-	0x00ff0000);
-  BSP_VMEOutboundPortCfg(
-	2,
-	VME_AM_SUP_SHORT_IO,
-	0x00000000,
-	_VME_A16_ON_PCI,
-	0x00010000);
-
-#ifdef _VME_CSR_ON_PCI
-  /* Map VME64 CSR */
-  printk("_VME_CSR_ON_PCI\n");
-  BSP_VMEOutboundPortCfg(
-		  7,
-		  VME_AM_CSR,
-		  0,
-		  _VME_CSR_ON_PCI,
-		  0x01000000);
-#endif
-
-
-#ifdef _VME_DRAM_OFFSET
-  printk("_VME_DRAM_OFFSET");
-  /* map our memory to VME giving the driver a hint that it's ordinary memory
-   * so they can enable decoupled cycles which should give better performance...
-   */
-  BSP_VMEInboundPortCfg(
-	0,
-	VME_AM_EXT_SUP_DATA | VME_AM_IS_MEMORY,
-	_VME_DRAM_OFFSET,
-	PCI_DRAM_OFFSET,
-	BSP_mem_size);
-#endif
-
-  /* stdio is not yet initialized; the driver will revert to printk */
-  BSP_VMEOutboundPortsShow(0);
-  BSP_VMEInboundPortsShow(0);
-
-  BSP_VMEIrqMgrInstall();
-}
--- a/c/src/lib/libbsp/powerpc/gen83xx/ChangeLog
+++ b/c/src/lib/libbsp/powerpc/gen83xx/ChangeLog
@@ -1,8 +1,3 @@
-2009-03-18	Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
-
-	* start/start.S, include/hwreg_vals.h, startup/cpuinit.c:
-	correct some init values for HSC_CM01 boards
-
 2008-12-08	Ralf Corsépius <ralf.corsepius@rtems.org>

 	* bsp_specs: Backport from CVS-HEAD.
--- a/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h
+++ b/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h
@@ -207,26 +207,26 @@
 #define LBLAWBAR0_VAL  bsp_rom_start
 #define LBLAWAR0_VAL   0x80000018
 #define LBLAWBAR1_VAL  (FPGA_CONFIG_START)
-#define LBLAWAR1_VAL   0x80000018
+#define LBLAWAR1_VAL   0x80000015
 #define DDRLAWBAR0_VAL bsp_ram_start
 #define DDRLAWAR0_VAL  0x8000001B
 /*
 * Local Bus (Memory) Controller
 * FIXME: decode bit settings 
 */
-#define BR0_VAL (0xFE000000 | 0x01001)
+#define BR0_VAL 0xFE001001
 #define OR0_VAL 0xFE000E54
 // fpga config access range (UPM_A) (32 kByte)
 #define BR2_VAL (FPGA_CONFIG_START | 0x01881)
-#define OR2_VAL 0xFFFF9100
+#define OR2_VAL 0xFFF80100

 // fpga register access range (UPM_B) (8 MByte)
 #define BR3_VAL (FPGA_REGISTER_START | 0x018A1)
-#define OR3_VAL 0xFF801100
+#define OR3_VAL 0xFF800100

-// fpga fifo access range (UPM_C) (8 MByte)
-#define BR4_VAL (FPGA_FIFO_START | 0x018C1)
-#define OR4_VAL 0xFF801100
+// fpga fifo access range (UPM_B) (8 MByte)
+#define BR4_VAL (FPGA_FIFO_START | 0x018A1)
+#define OR4_VAL 0xFF800100

 /*
 * SDRAM registers
--- a/c/src/lib/libbsp/powerpc/gen83xx/start/start.S
+++ b/c/src/lib/libbsp/powerpc/gen83xx/start/start.S
@@ -199,18 +199,7 @@ start_code_in_rom:
 #ifdef OR3_VAL
 	SET_IMM_REGW r31,r30,OR3_OFF,OR3_VAL
 #endif
-#ifdef BR4_VAL
-	SET_IMM_REGW r31,r30,BR4_OFF,BR4_VAL
-#endif
-#ifdef OR4_VAL
-	SET_IMM_REGW r31,r30,OR4_OFF,OR4_VAL
-#endif
-#ifdef BR5_VAL
-	SET_IMM_REGW r31,r30,BR5_OFF,BR5_VAL
-#endif
-#ifdef OR5_VAL
-	SET_IMM_REGW r31,r30,OR5_OFF,OR5_VAL
-#endif
+	
 	/*
 	 * ROM startup: init SDRAM access window
 	 */
--- a/c/src/lib/libbsp/powerpc/gen83xx/startup/cpuinit.c
+++ b/c/src/lib/libbsp/powerpc/gen83xx/startup/cpuinit.c
@@ -235,7 +235,7 @@ void cpu_init( void)
      (uint32_t) bsp_rom_start,
      (uint32_t) bsp_rom_size,
    #endif /* HAS_UBOOT */
-    true,
+    false,
    false,
    false,
    false,
--- a/c/src/lib/libbsp/powerpc/mvme3100/ChangeLog
+++ b/c/src/lib/libbsp/powerpc/mvme3100/ChangeLog
@@ -1,34 +1,3 @@
-2009-10-20	Till Straumann <strauman@slac.stanford.edu>
-
-	* network/tsec.c: Bugfix. Broadcast address was declared
-	uint8_t instead of uint8_t [8].
-
-2009-10-13	Till Straumann <strauman@slac.stanford.edu>
-
-	PR 1451/bsps
-	* network/tsec.c: Fix mbuf leak when watchdog expires. The
-	re-initialization algorithm failed to release mbuf chains
-	held in the TX ring.
-	Also, during initialization the initial link status is determined
-	and IFF_OACTIVE set if no active link was detected.
-
-2009-08-17	Till Straumann <strauman@slac.stanford.edu>
-
-	* network/tsec.c, network/if_tsec_pub.h:
-	Fixed bugs in multicast support; added reference-count
-	for hash-table entries which allows for the implementation
-	of a 'deletion' routine.
-	NOTE: mcast support largely untested.
-
-2009-06-05	Till Straumann <strauman@slac.stanford.edu>
-
-	* irq/irq_init.c: silenced compiler warning.
-
-2009-06-05	Till Straumann <strauman@slac.stanford.edu>
-
-	* network/tsec.c, network/if_tsec_pub.h:
-	implemented multicast support.
-
 2009-03-05	Till Straumann <strauman@slac.stanford.edu>

 	* startup/bspstart.c: removed legacy code (inherited
--- a/c/src/lib/libbsp/powerpc/mvme3100/irq/irq_init.c
+++ b/c/src/lib/libbsp/powerpc/mvme3100/irq/irq_init.c
@@ -28,7 +28,7 @@
 #include <libcpu/raw_exception.h>
 #include <rtems/bspIo.h>

-static void nop_func(void *arg)
+static void nop_func(void)
 {
 	printk("Unhandled IRQ\n");
 }
--- a/c/src/lib/libbsp/powerpc/mvme3100/network/if_tsec_pub.h
+++ b/c/src/lib/libbsp/powerpc/mvme3100/network/if_tsec_pub.h
@@ -173,60 +173,10 @@ BSP_tsec_reset_stats(struct tsec_private *mp);
 * 'promisc'	whether to set promiscuous flag.
 * 'enaddr'		pointer to six bytes with MAC address. Read
 *				from the device if NULL.
- * NOTE:        multicast filter is cleared by this routine.
 */
 void
 BSP_tsec_init_hw(struct tsec_private *mp, int promisc, unsigned char *enaddr);

-/*
- * Clear multicast hash filter. No multicast frames are accepted
- * after executing this routine (unless the hardware was initialized
- * in 'promiscuous' mode).
- *
- * Reset reference count for all hash-table entries
- * to zero (see BSP_tsec_mcast_filter_accept_del()).
- */
-void
-BSP_tsec_mcast_filter_clear(struct tsec_private *mp);
-
-/*
- * Program multicast filter to accept all multicast frames.
- *
- * Increment reference count for all hash-table entries
- * by one (see BSP_tsec_mcast_filter_accept_del()).
- */
-void
-BSP_tsec_mcast_filter_accept_all(struct tsec_private *mp);
-
-/*
- * Add a MAC address to the multicast filter and increment
- * the reference count for the matching hash-table entry
- * (see BSP_tsec_mcast_filter_accept_del()).
- * 
- * Existing entries are not changed but note that
- * the filter is imperfect, i.e., multiple MAC addresses
- * may alias to a single filter entry. Hence software
- * filtering must still be performed.
- *
- */
-void
-BSP_tsec_mcast_filter_accept_add(struct tsec_private *mp, unsigned char *enaddr);
-
-/*
- * Remove a MAC address from the (imperfec) multicast
- * filter.
- * Note that the driver maintains an internal reference
- * counter for each multicast hash. The hash-table
- * entry is only cleared when the reference count
- * reaches zero ('del' has been called the same
- * amount of times as 'add' for an address (or
- * any alias) that matches a given table entry.
- * BSP_tsec_mcast_filter_clear() resets all reference
- * counters to zero.
- */
-void
-BSP_tsec_mcast_filter_accept_del(struct tsec_private *mp, unsigned char *enaddr);
-
 /*
 * Dump statistics to FILE 'f'. If NULL, stdout is used.
 */
--- a/c/src/lib/libbsp/powerpc/mvme3100/network/tsec.c
+++ b/c/src/lib/libbsp/powerpc/mvme3100/network/tsec.c
@@ -50,7 +50,6 @@
 #include <libcpu/byteorder.h>
 #include <inttypes.h>
 #include <stdio.h>
-#include <errno.h>
 #include <assert.h>
 #include <bsp.h>

@@ -114,9 +113,6 @@ phy_irq_pending(struct tsec_private *mp);
 static uint32_t
 phy_ack_irq(struct tsec_private *mp);

-static void
-tsec_update_mcast(struct ifnet *ifp);
-
 #if defined(PARANOIA) || defined(DEBUG)
 void tsec_dump_tring(struct tsec_private *mp);
 void tsec_dump_rring(struct tsec_private *mp);
@@ -640,8 +636,6 @@ static inline void bd_wrbuf(TSEC_BD *bd, uint32_t addr)

 /* Driver 'private' data */

-#define NUM_MC_HASHES		256
-
 struct tsec_private {
 	FEC_Enet_Base	base;            /* Controller base address                  */
 	FEC_Enet_Base	phy_base;        /* Phy base address (not necessarily identical
@@ -686,7 +680,6 @@ struct tsec_private {
 		unsigned	odrops;
 		unsigned	repack;
 	}               stats;
-	uint16_t		mc_refcnt[NUM_MC_HASHES];
 };

 #define NEXT_TXI(mp, i)	(((i)+1) < (mp)->tx_ring_size ? (i)+1 : 0 )
@@ -1219,7 +1212,7 @@ int i;
 static int
 mac_set_duplex(struct tsec_private *mp)
 {
-int media = IFM_MAKEWORD(0, 0, 0, 0);
+int media = 0;

 	if ( 0 == BSP_tsec_media_ioctl(mp, SIOCGIFMEDIA, &media)) {
 		if ( IFM_LINK_OK & media ) {
@@ -1346,10 +1339,9 @@ rtems_interrupt_level l;

 	for ( i=0; i<8*4; i+=4 ) {
 		fec_wr( b, TSEC_IADDR0 + i, 0 );
+		fec_wr( b, TSEC_GADDR0 + i, 0 );
 	}

-	BSP_tsec_mcast_filter_clear(mp);
-
 	BSP_tsec_reset_stats(mp);

 	fec_wr( b, TSEC_ATTR, (TSEC_ATTR_RDSEN | TSEC_ATTR_RBDSEN) );
@@ -1404,80 +1396,6 @@ rtems_interrupt_level l;
 	rtems_interrupt_enable( l );
 }

-static uint8_t
-hash_prog(struct tsec_private *mp, uint32_t tble, const uint8_t *enaddr, int accept)
-{
-uint8_t  s;
-uint32_t reg, bit;
-
-	s = ether_crc32_le(enaddr, ETHER_ADDR_LEN);
-
-	/* bit-reverse */
-    s = ((s&0x0f) << 4) | ((s&0xf0) >> 4);
-    s = ((s&0x33) << 2) | ((s&0xcc) >> 2);
-    s = ((s&0x55) << 1) | ((s&0xaa) >> 1);
-
-	reg = tble + ((s >> (5-2)) & ~3);
-	bit = 1 << (31 - (s & 31));
-
-	if ( accept ) {
-		if ( 0 == mp->mc_refcnt[s]++ )
-			fec_set( mp->base, reg, bit );
-	} else {
-		if ( mp->mc_refcnt[s] > 0 && 0 == --mp->mc_refcnt[s] )
-			fec_clr( mp->base, reg, bit );
-	}
-}
-
-void
-BSP_tsec_mcast_filter_clear(struct tsec_private *mp)
-{
-int i;
-	for ( i=0; i<8*4; i+=4 ) {
-		fec_wr( mp->base, TSEC_GADDR0 + i, 0 );
-	}
-	for ( i=0; i<NUM_MC_HASHES; i++ )
-		mp->mc_refcnt[i] = 0;
-}
-
-void
-BSP_tsec_mcast_filter_accept_all(struct tsec_private *mp)
-{
-int i;
-	for ( i=0; i<8*4; i+=4 ) {
-		fec_wr( mp->base, TSEC_GADDR0 + i, 0xffffffff );
-	}
-	for ( i=0; i<NUM_MC_HASHES; i++ )
-		mp->mc_refcnt[i]++;
-}
-
-static void
-mcast_filter_prog(struct tsec_private *mp, uint8_t *enaddr, int accept)
-{
-static const uint8_t bcst[6]={0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-	if ( ! (enaddr[0] & 0x01) ) {
-		/* not a multicast address; ignore */
-		return;
-	}
-	if ( 0 == memcmp( enaddr, bcst, sizeof(bcst) ) ) {
-		/* broadcast; ignore */
-		return;
-	}
-	hash_prog(mp, TSEC_GADDR0, enaddr, accept);
-}
-
-void
-BSP_tsec_mcast_filter_accept_add(struct tsec_private *mp, uint8_t *enaddr)
-{
-	mcast_filter_prog(mp, enaddr, 1 /* accept */);
-}
-
-void
-BSP_tsec_mcast_filter_accept_del(struct tsec_private *mp, uint8_t *enaddr)
-{
-	mcast_filter_prog(mp, enaddr, 0 /* delete */);
-}
-
 void
 BSP_tsec_dump_stats(struct tsec_private *mp, FILE *f)
 {
@@ -2329,17 +2247,15 @@ unsigned long	l,o;
 static void consume_rx_mbuf(void *buf, void *arg, int len)
 {
 struct ifnet *ifp = arg;
-struct mbuf    *m = buf;
-
 	if ( len <= 0 ) {
 		ifp->if_iqdrops++;
 		if ( len < 0 ) {
 			ifp->if_ierrors++;
 		}
-		if ( m )
-			m_freem(m);
+		/* caller recycles mbuf */
 	} else {
 		struct ether_header *eh;
+		struct mbuf			*m = buf;

 			eh			= (struct ether_header *)(mtod(m, unsigned long) + ETH_RX_OFFSET);
 			m->m_len	= m->m_pkthdr.len = len - sizeof(struct ether_header) - ETH_RX_OFFSET - ETH_CRC_LEN;
@@ -2393,21 +2309,7 @@ tsec_init(void *arg)
 {
 struct tsec_softc	*sc  = arg;
 struct ifnet		*ifp = &sc->arpcom.ac_if;
-int                 media;
-
 	BSP_tsec_init_hw(&sc->pvt, ifp->if_flags & IFF_PROMISC, sc->arpcom.ac_enaddr);
-
-	/* Determine initial link status and block sender if there is no link */
-	media = IFM_MAKEWORD(0, 0, 0, 0);
-	if ( 0 == BSP_tsec_media_ioctl(&sc->pvt, SIOCGIFMEDIA, &media) ) {
-		if ( (IFM_LINK_OK & media) ) {
-			ifp->if_flags &= ~IFF_OACTIVE;
-		} else {
-			ifp->if_flags |=  IFF_OACTIVE;
-		}
-	}
-
-	tsec_update_mcast(ifp);
 	ifp->if_flags |= IFF_RUNNING;
 	sc->arpcom.ac_if.if_timer = 0;
 }
@@ -2446,31 +2348,6 @@ struct tsec_softc	*sc = ifp->if_softc;
 	tsec_start(ifp);
 }

-static void
-tsec_update_mcast(struct ifnet *ifp)
-{
-struct tsec_softc *sc = ifp->if_softc;
-struct ether_multi     *enm;
-struct ether_multistep step;
-
-	if ( IFF_ALLMULTI & ifp->if_flags ) {
-		BSP_tsec_mcast_filter_accept_all( &sc->pvt );
-	} else {
-		BSP_tsec_mcast_filter_clear( &sc->pvt );
-
-		ETHER_FIRST_MULTI(step, (struct arpcom *)ifp, enm);
-
-		while ( enm ) {
-			if ( memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) )
-				assert( !"Should never get here; IFF_ALLMULTI should be set!" );
-
-			BSP_tsec_mcast_filter_accept_add(&sc->pvt, enm->enm_addrlo);
-
-			ETHER_NEXT_MULTI(step, enm);
-		}
-	}
-}
-
 /* bsdnet driver ioctl entry */
 static int
 tsec_ioctl(struct ifnet *ifp, ioctl_command_t cmd, caddr_t data)
@@ -2518,19 +2395,15 @@ int					f;
 			error = BSP_tsec_media_ioctl(&sc->pvt, cmd, &ifr->ifr_media);
 		break;
 
- 		case SIOCADDMULTI:
- 		case SIOCDELMULTI:
-			error = (cmd == SIOCADDMULTI)
-		    		? ether_addmulti(ifr, &sc->arpcom)
-				    : ether_delmulti(ifr, &sc->arpcom);
+/*
+ * TODO
+ *
+ * 		case SIOCADDMULTI:
+ * 		case SIOCDELMULTI:
+ *
+ *		break;
+ */

-			if (error == ENETRESET) {
-				if (ifp->if_flags & IFF_RUNNING) {
-					tsec_update_mcast(ifp);
-				}
-				error = 0;
-			}
-		break;

 		case SIO_RTEMS_SHOW_STATS:
 			BSP_tsec_dump_stats( &sc->pvt, stdout );
@@ -2697,7 +2570,7 @@ struct	ifnet		*ifp;
 		ifp->if_timer			= 0;

 		sc->bsd.oif_flags		= /* ... */
-		ifp->if_flags			= IFF_BROADCAST | IFF_MULTICAST | IFF_SIMPLEX;
+		ifp->if_flags			= IFF_BROADCAST | IFF_SIMPLEX;

 		/*
 		 * if unset, this set to 10Mbps by ether_ifattach; seems to be unused by bsdnet stack;
--- a/c/src/lib/libbsp/powerpc/mvme5500/ChangeLog
+++ b/c/src/lib/libbsp/powerpc/mvme5500/ChangeLog
@@ -1,25 +1,3 @@
-2009-05-08	Joel Sherrill <joel.sherrill@oarcorp.com>
-
-	* irq/irq.c, network/if_1GHz/POSSIBLEBUG: Removed.
-
-2009-05-08	Kate Feng <feng1@bnl.gov>
-
-	PR1395/bsps
-	* Updated the changes from RTEMS-4.8.0, which were made since Oct. 2007.
-	* network/if_1GHz/if_wm.c: fixed some bugs in the 1GHz driver.
-	* pci/pci_interface.c:
-	  + Enabled PCI "Read", "Read Line", and "Read Multiple"
-	  +  Agressive Prefetch to improve the performance of the PCI based
-	     applications (e.g. 1GHz NIC).
-	* irq/BSP_irq.c : Replaced the irq/irq.c, and used GT_GPP_Value
-	register to monitor the cause of the level sensitive interrupts.
-	This unique solution solves various bugs in the 1GHz network drivers
-	Fixed bugs in compute_pic_masks_from_prio()
-	* pci/pci.c : Updated it to be consistent with the original pci.c
-	* written by Eric Valette.  There is no change in its function.
-	* irq/irq_init.c : set defaultIrq->next_handler to be 0 
-	* for BSP_SHARED_HANDLER_SUPPORT.
-
 2008-12-08	Ralf Corsépius <ralf.corsepius@rtems.org>

 	* bsp_specs: Backport from CVS-HEAD.
--- a/c/src/lib/libbsp/powerpc/mvme5500/GT64260/VPD.h
+++ b/c/src/lib/libbsp/powerpc/mvme5500/GT64260/VPD.h
@@ -5,5 +5,7 @@
 *
 */

+extern unsigned char ConfVPD_buff[200];
+
 #define VPD_ENET0_OFFSET  0x3c
 #define VPD_ENET1_OFFSET  0x45
--- a/c/src/lib/libbsp/powerpc/mvme5500/GT64260/gtreg.h
+++ b/c/src/lib/libbsp/powerpc/mvme5500/GT64260/gtreg.h
@@ -190,7 +190,7 @@
 #define GT_MPP_Control2			0xf008
 #define GT_MPP_Control3			0xf00c

-/* <skf> added for GT64260 */
+/* <skf> added */
 #define GT_MPP_SerialPortMultiplex      0xf010

 #define	GT_GPP_IO_Control		0xf100
@@ -789,13 +789,14 @@
 #define TWSI_BAUDE_RATE		0xc00c
 #define TWSI_SFT_RST		0xc01c

+/* Interrupt Controller - Interrupt Controller Registers */
 /* Section 25.2 : Table 734 <skf> */

-#define GT64260_MAIN_INT_CAUSE_LO	0xc18 /* read Only */
-#define GT64260_MAIN_INT_CAUSE_HI       0xc68 /* read Only */
-#define GT64260_CPU_INT_MASK_LO 	0xc1c
-#define GT64260_CPU_INT_MASK_HI	        0xc6c
-#define GT64260_CPU_SEL_CAUSE	0xc70 /* read Only */
+#define GT_MAIN_INT_CAUSE_LO	0xc18 /* read Only */
+#define GT_MAIN_INT_CAUSE_HI   0xc68 /* read Only */
+#define GT_CPU_INT_MASK_LO 	0xc1c
+#define GT_CPU_INT_MASK_HI	0xc6c
+#define GT_CPU_SEL_CAUSE	0xc70 /* read Only */
 #define GT_PCI0_INT_MASK_LO	0xc24
 #define GT_PCI0_INT_MASK_HI	0xc64
 #define GT_PCI0_SEL_CAUSE	0xc74 /* read Only */
--- a/c/src/lib/libbsp/powerpc/mvme5500/Makefile.am
+++ b/c/src/lib/libbsp/powerpc/mvme5500/Makefile.am
@@ -32,9 +32,7 @@ startup_SOURCES = startup/bspstart.c \
    ../../powerpc/shared/startup/sbrk.c ../../shared/bootcard.c \
    ../../shared/bsppredriverhook.c startup/bspclean.c \
    ../../shared/bsplibc.c ../../shared/bsppost.c \
-    ../../shared/gnatinstallhandler.c startup/reboot.c \
-    ../../powerpc/shared/startup/probeMemEnd.c
-
+    ../../shared/gnatinstallhandler.c startup/reboot.c
 pclock_SOURCES = ../../powerpc/shared/clock/p_clock.c

 include_bsp_HEADERS = ../../powerpc/shared/console/uart.h
@@ -47,7 +45,7 @@ pci_SOURCES = pci/pci.c pci/pci_interface.c pci/detect_host_bridge.c \
    pci/pcifinddevice.c

 include_bsp_HEADERS += irq/irq.h
-irq_SOURCES = irq/irq_init.c irq/BSP_irq.c 
+irq_SOURCES = irq/irq_init.c irq/irq.c 

 nodist_include_HEADERS += ../../shared/tod.h
 tod_SOURCES = ../../shared/tod.c tod/todcfg.c
--- a/c/src/lib/libbsp/powerpc/mvme5500/README
+++ b/c/src/lib/libbsp/powerpc/mvme5500/README
@@ -1,5 +1,5 @@
 #
-#  $Id: README,v 1.4.1  Shuchen Kate Feng, NSLS, BNL (03/16/2009)
+#  $Id: README,v 1.3.1  Shuchen Kate Feng, NSLS, BNL (08/27/07)
 #

 Please reference README.booting for the boot/load process.
@@ -7,10 +7,7 @@ Please reference README.booting for the boot/load process.
 For the priority setting of the Interrupt Requests (IRQs), please
 reference README.irq 

-The BSP is built and tested on the RTEMS 4.9.1 release. The
-PR1385 patch for c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S
-is not needed for the mvme5500 BSP because the PowerPC BSPs
-use the shared exception framework in the RTEMS 4.9 release.
+The BSP is built and tested on the 4.7.1 and 4.7.99.2 CVS RTEMS release.

 I believe in valuable real-time programming, where technical neatness,
 performance and truth are.  I hope I still believe. Any suggestion,
--- a/c/src/lib/libbsp/powerpc/mvme5500/README.booting
+++ b/c/src/lib/libbsp/powerpc/mvme5500/README.booting
@@ -1,9 +1,8 @@
-README.booting: written by S. Kate Feng <feng1@bnl.gov>, March 16, 2009
+README.booting: written by S. Kate Feng <feng1@bnl.gov>, Aug. 28, 2007

-The BSP is built and tested on the RTEMS 4.9.1 release. The
-PR1385 patch for c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S
-is not needed for the mvme5500 BSP because the PowerPC BSPs
-use the shared exception framework in the RTEMS 4.9 release.
+The bootloader is adapted from Till Straumann's Generic Mini-loader,
+which he wrote originally for the SVGM powerpc board. 
+The BSP is built and tested on the 4.7 CVS RTEMS release.

 Booting requirement :
 -------------------------
@@ -12,7 +11,12 @@ Booting requirement :
   or /etc/dhcpd.conf (DHCP) properly to boot the system.
   (Note : EPICS needs a NTP server).
 
-2) Example of the boot script setup carried out on the MOTLoad 
+2) Please copy the prebuilt RTEMS binary (e.g. misc/rtems5500-cexp.bin)
+   and perhaps others (e.g. misc/st.sys) to the /tftpboot/epics/hostname/bin/
+   directory or the TFTPBOOT one you specified in the 'tftpGet'
+   command of the boot script (as shown in the following example).
+
+3) Example of the boot script setup carried out on the MOTLoad 
   command line : 

 MVME5500> gevEdit mot-script-boot
@@ -28,14 +32,23 @@ MVME5500>
 Note : (cxx.xx.xx.xx is the client IP address and 
        sxx.xx.xx.xx is the server IP address)

-3) Other reference web sites for mvme5500 BSP:
+4) Other reference web sites for mvme5500 BSP:
+http://lansce.lanl.gov/EPICS/presentations/KateFeng%20RTEMS-mvme55001.ppt
 http://www.nsls.bnl.gov/facility/expsys/software/EPICS/
+http://www.nsls.bnl.gov/facility/expsys/software/EPICS/FAQ.txt

+5) When generating code (especially C++) for this system, one should
+   use at least gcc-3.2 (preferrably a copy downloaded from the RTEMS
+   site [snapshot area] )

-4) To reboot the RTEMS-MVME5500 (board reset), one can invoke the
+6) To reboot the RTEMS-MVME5500 (board reset), one can invoke the
   rtemsReboot() command at Cexp> prompt.
 
-5) To get started with RTEMS/EPICS and to build development
+7) Please reference http://www.slac.stanford.edu/~strauman/rtems
+for the source code and installation guidance of cexp, GeSys and
+other useful utilities such as telnet, nfs, and so on. 
+
+8) To get started with RTEMS/EPICS and to build development
 tools and BSP, I would recommend one to reference
 http://www.aps.anl.gov/epics/base/RTEMS/tutorial/
 in additional to the RTEMS document.
--- a/c/src/lib/libbsp/powerpc/mvme5500/include/bsp.h
+++ b/c/src/lib/libbsp/powerpc/mvme5500/include/bsp.h
@@ -7,8 +7,7 @@
 *  found in found in the file LICENSE in this distribution or at
 *  http://www.rtems.com/license/LICENSE.
 *
- *  (C) S. Kate Feng 2003-2007 : Modified it to support the mvme5500 BSP.
- *
+ *  S. Kate Feng 2003-2007 : Modified it to support the mvme5500 BSP.
 *
 */

@@ -23,57 +22,10 @@
 #include <libcpu/io.h>
 #include <bsp/vectors.h>

-/* Board type */
-typedef enum {
-	undefined = 0,
-	MVME5500,
-	MVME6100
-} BSP_BoardTypes;
-
-BSP_BoardTypes BSP_getBoardType();
-
-/* Board type */
-typedef enum {
-	Undefined,
-	UNIVERSE2,
-	TSI148,
-} BSP_VMEchipTypes;
-
-BSP_VMEchipTypes BSP_getVMEchipType();
-
-/* The version of Discovery system controller */
-
-typedef enum {
-	notdefined, 
-	GT64260A,
-	GT64260B,	    
-	MV64360,
-} DiscoveryChipVersion;
-
-DiscoveryChipVersion BSP_getDiscoveryChipVersion();
-
-#define _256M           0x10000000
-#define _512M           0x20000000
-
-#define GT64x60_REG_BASE	0xf1000000  /* Base of GT64260 Reg Space */
-#define GT64x60_REG_SPACE_SIZE	0x10000     /* 64Kb Internal Reg Space */
-
-#define GT64x60_DEV1_BASE       0xf1100000  /* Device bank1(chip select 1) base
-                                             */
-#define GT64260_DEV1_SIZE 	0x00100000 /* Device bank size */
+#include <bsp/bspMvme5500.h>

 /* fundamental addresses for this BSP (PREPxxx are from libcpu/io.h) */
-#define _IO_BASE GT64x60_REG_BASE
-
-#define BSP_NVRAM_BASE_ADDR     0xf1110000
-
-#define BSP_RTC_INTA_REG        0x7ff0
-#define BSP_RTC_SECOND	        0x7ff2  
-#define BSP_RTC_MINUTE	        0x7ff3
-#define BSP_RTC_HOUR	        0x7ff4  
-#define BSP_RTC_DATE	        0x7ff5
-#define BSP_RTC_INTERRUPTS      0x7ff6
-#define BSP_RTC_WATCHDOG        0x7ff7
+#define _IO_BASE GT64260_REG_BASE

 /* PCI0 Domain I/O space */
 #define PCI0_IO_BASE            0xf0000000
@@ -117,15 +69,17 @@ DiscoveryChipVersion BSP_getDiscoveryChipVersion();
 */

 #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2
-#define BSP_INTERRUPT_STACK_SIZE  (16 * 1024) /* <skf> 2/09 wants it to be adjustable by BSP */

 /* uart.c uses out_8 instead of outb  */
-#define BSP_UART_IOBASE_COM1	GT64x60_DEV1_BASE + 0x20000
-#define BSP_UART_IOBASE_COM2	GT64x60_DEV1_BASE + 0x21000
+#define BSP_UART_IOBASE_COM1	GT64260_DEV1_BASE + 0x20000
+#define BSP_UART_IOBASE_COM2	GT64260_DEV1_BASE + 0x21000

 #define BSP_CONSOLE_PORT		BSP_UART_COM1  /* console */
 #define BSP_UART_BAUD_BASE		115200

+/*
+ * Vital Board data Start using DATA RESIDUAL
+ */
 /*
 * Total memory using RESIDUAL DATA
 */
@@ -146,7 +100,6 @@ extern unsigned int BSP_time_base_divisor;
 #define BSP_Convert_decrementer( _value ) \
  ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value)))

-extern rtems_configuration_table  BSP_Configuration;
 extern void BSP_panic(char *s);
 extern void bsp_reset(void);
 /* extern int printk(const char *, ...) __attribute__((format(printf, 1, 2))); */
@@ -165,31 +118,24 @@ extern unsigned int BSP_heap_start;
 #define RTEMS_BSP_NETWORK_DRIVER_ATTACH	rtems_i82544EI_driver_attach
 #endif

-extern int RTEMS_BSP_NETWORK_DRIVER_ATTACH();
+extern int
+RTEMS_BSP_NETWORK_DRIVER_ATTACH(/* struct rtems_bsdnet_ifconfig * */);

 /*
 *  BSP Configuration Default Overrides
 */
 #define BSP_ZERO_WORKSPACE_AUTOMATICALLY TRUE

-#define gccMemBar() RTEMS_COMPILER_MEMORY_BARRIER()
+/* As per Linux, This should be in the ppc/system.h */

-static inline void lwmemBar()
-{
-    asm volatile("lwsync":::"memory");
-}
-
-static inline void io_flush()
-{
-    asm volatile("isync":::"memory");
-}
 static inline void memBar()
 {
    asm volatile("sync":::"memory");
 }
+
 static inline void ioBar()
 {
-    asm volatile("eieio":::"memory");
+    asm volatile("eieio");
 }

 #endif 
--- a/c/src/lib/libbsp/powerpc/mvme5500/irq/BSP_irq.c
+++ b/c/src/lib/libbsp/powerpc/mvme5500/irq/BSP_irq.c
@@ -1,4 +1,4 @@
-/*  BSP_irq.c
+/*  irq.c
 *
 *  This file contains the implementation of the function described in irq.h
 *
@@ -8,25 +8,21 @@
 *  found in the file LICENSE in this distribution or at
 *  http://www.OARcorp.com/rtems/license.html.
 *
- *  Acknowledgement May 2004, to Till Straumann <strauman@slac.stanford.edu>
+ *  Acknowledgement May 2004 : to Till Straumann <strauman@slac.stanford.edu>
 *  for some inputs.
 *
 *  Copyright 2003, 2004, 2005, 2007  Shuchen Kate Feng <feng1@bnl.gov>,
- *            NSLS, Brookhaven National Laboratory. All rights reserved.
- *
- *  1) Used GT_GPP_Value register instead of the GT_GPP_Interrupt_Cause
- *     register to monitor the cause of the level sensitive interrupts.
- *     (Copyright : NDA item)
- *  2) The implementation of picPrioTable[] is an original work by the
+ *                  NSLS,Brookhaven National Laboratory
+ *  1) Modified and added support for the MVME5500 board.
+ *  2) The implementation of picIsrTable[] is an original work by the
 *     author to optimize the software IRQ priority scheduling because
 *     Discovery controller does not provide H/W IRQ priority schedule. 
 *     It ensures the fastest/faster interrupt service to the
 *     highest/higher priority IRQ, if pendig.
 *  3) _CPU_MSR_SET() needs RTEMS_COMPILER_MEMORY_BARRIER()
- * 
+ *
 */
-
-#include <stdio.h>  
+  
 #include <rtems/system.h>
 #include <bsp.h>
 #include <bsp/irq.h>
@@ -43,7 +39,9 @@

 #define HI_INT_CAUSE 0x40000000

-#define MAX_IRQ_LOOP 20
+#define MAX_IRQ_LOOP 30
+
+#define EDGE_TRIGGER

 /* #define DEBUG_IRQ*/

@@ -59,11 +57,11 @@ static unsigned int BSP_irq_prio_mask_tbl[3][BSP_PIC_IRQ_NUMBER];

 /*
 * location used to store initial tables used for interrupt
- * management.BSP copy of the configuration 
+ * management.
 */
-static rtems_irq_global_settings	BSP_config;
+static rtems_irq_global_settings* 	internal_config;
+/* handler table (cached copy ) */
 static rtems_irq_connect_data*		rtems_hdl_tbl;
-
 /*
 * default handler connected on each irq after bsp initialization
 * (locally cached copy)
@@ -75,33 +73,32 @@ static volatile unsigned  *BSP_irqMask_reg[3];
 static volatile unsigned  *BSP_irqCause_reg[3];
 static volatile unsigned  BSP_irqMask_cache[3]={0,0,0}; 

-static int picPrioTblPtr=0;
+
+static int picIsrTblPtr=0;
 static unsigned int GPPIrqInTbl=0;
 static unsigned long long MainIrqInTbl=0;

 /* 
- * The software developers are forbidden to setup picPrioTable[],
+ * The software developers are forbidden to setup picIsrTable[],
 * as it is a powerful engine for the BSP to find the pending
 * highest priority IRQ at run time.  It ensures the fastest/faster
 * interrupt service to the highest/higher priority IRQ, if pendig.
 *
- * The picPrioTable[96] is updated dynamically at run time
+ * The picIsrTable[96] is updated dynamically at run time
 * based on the priority levels set at BSPirqPrioTable[96],
- * while the BSP_enable_irq_at_pic(), and BSP_disable_irq_at_pic()
+ * while the BSP_enable_pic_irq(), and BSP_disable_pic_irq()
 * commands are invoked.
 *
- * The picPrioTable[96] lists the enabled CPU main and GPP external interrupt 
+ * The picIsrTable[96] lists the enabled CPU main and GPP external interrupt 
 * numbers [0 (lowest)- 95 (highest)] starting from the highest priority
 * one to the lowest priority one. The highest priority interrupt is
- * located at picPrioTable[0], and the lowest priority interrupt is located
- * at picPrioTable[picPrioTblPtr-1].
+ * located at picIsrTable[0], and the lowest priority interrupt is located
+ * at picIsrTable[picIsrTblPtr-1].
 *
 *
 */
-#define DynamicIsrTable
-#ifdef DynamicIsrTable
-/* BitNums for Main Interrupt Lo/High Cause, -1 means invalid bit */ 
-static unsigned int picPrioTable[BSP_PIC_IRQ_NUMBER]={ 
+/* BitNums for Main Interrupt Lo/High Cause and GPP, -1 means invalid bit */ 
+static unsigned int picIsrTable[BSP_PIC_IRQ_NUMBER]={  
     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
@@ -112,19 +109,7 @@ static unsigned int picPrioTable[BSP_PIC_IRQ_NUMBER]={
     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
     -1, -1, -1, -1, -1, -1 };
-#else
-static unsigned int picPrioTable[BSP_PIC_IRQ_NUMBER]={ 
-     80, 84, 76, 77, 32, -1, -1, -1, -1, -1,
-     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-     -1, -1, -1, -1, -1, -1 };
-#endif
+

 /*
 * Check if IRQ is a MAIN CPU internal IRQ or GPP external IRQ
@@ -146,18 +131,28 @@ static inline int is_processor_irq(const rtems_irq_number irqLine)
 	 );
 }

+static inline unsigned int divIrq32(unsigned irq)
+{
+  return(irq/32);
+}
+
+static inline unsigned int modIrq32(unsigned irq)
+{
+   return(irq%32);
+}
+
 /*
 * ------------------------ RTEMS Irq helper functions ----------------
 */
 
 /*
- * Caution : this function assumes the variable "BSP_config"
+ * Caution : this function assumes the variable "internal_config"
 * is already set and that the tables it contains are still valid
 * and accessible.
 */
-static void compute_pic_masks_from_prio(void)
+static void compute_pic_masks_from_prio(rtems_irq_global_settings *config)
 {
-  int i,j, k, isGppMain;
+  int i,j, k;
  unsigned long long irq_prio_mask=0;

  /*
@@ -173,27 +168,26 @@ static void compute_pic_masks_from_prio(void)
 	    BSP_irq_prio_mask_tbl[k][i]=0;

        irq_prio_mask =0;
-        isGppMain =1;
        break;
      default : 
-        isGppMain =0;
        irq_prio_mask = (unsigned long long) (1LLU << i);
 	break;
    }
-    if ( isGppMain) continue; 
+    
+    if (irq_prio_mask) {
    for (j = 0; j <BSP_MAIN_IRQ_NUMBER; j++) {
        /*
         * Mask interrupts at PIC level that have a lower priority
         * or <Till Straumann> a equal priority. 
         */
-        if (BSP_config.irqPrioTbl [i] >= BSP_config.irqPrioTbl [j])
+        if (config->irqPrioTbl [i] >= config->irqPrioTbl [j])
 	   irq_prio_mask |= (unsigned long long)(1LLU << j);
    }
    

    BSP_irq_prio_mask_tbl[0][i] = irq_prio_mask & 0xffffffff;
    BSP_irq_prio_mask_tbl[1][i] = (irq_prio_mask>>32) & 0xffffffff;
-#if 0
+#ifdef DEBUG
    printk("irq_mask_prio_tbl[%d]:0x%8x%8x\n",i,BSP_irq_prio_mask_tbl[1][i],
 	   BSP_irq_prio_mask_tbl[0][i]);
 #endif 
@@ -201,15 +195,14 @@ static void compute_pic_masks_from_prio(void)
    BSP_irq_prio_mask_tbl[2][i] = 1<<i;
    /* Compute for the GPP priority interrupt mask */
    for (j=BSP_GPP_IRQ_LOWEST_OFFSET; j <BSP_PROCESSOR_IRQ_LOWEST_OFFSET; j++) {      
-      if (BSP_config.irqPrioTbl [i] >= BSP_config.irqPrioTbl [j])
+      if (config->irqPrioTbl [i] >= config->irqPrioTbl [j])
 	   BSP_irq_prio_mask_tbl[2][i] |= 1 << (j-BSP_GPP_IRQ_LOWEST_OFFSET); 
    }
-#if 0
-    printk("GPPirq_mask_prio_tbl[%d]:0x%8x\n",i,BSP_irq_prio_mask_tbl[2][i]);
-#endif 
+    }
  }
 }

+
 static void UpdateMainIrqTbl(int irqNum)
 {
  int i=0, j, shifted=0;
@@ -232,25 +225,23 @@ static void UpdateMainIrqTbl(int irqNum)
       ((irqNum>BSP_MICH_IRQ_MAX_OFFSET) && 
        (!(( 1 << (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)) & GPPIrqInTbl))))
  { 
-      while ( picPrioTable[i]!=-1) {
-        if (BSP_config.irqPrioTbl[irqNum]>BSP_config.irqPrioTbl[picPrioTable[i]]) {
+      while ( picIsrTable[i]!=-1) {
+        if (internal_config->irqPrioTbl[irqNum]>internal_config->irqPrioTbl[picIsrTable[i]]) {
          /* all other lower priority entries shifted right */
-          for (j=picPrioTblPtr;j>i; j--) {
-              picPrioTable[j]=picPrioTable[j-1];
-          }
-          picPrioTable[i]=irqNum;
+          for (j=picIsrTblPtr;j>i; j--) 
+              picIsrTable[j]=picIsrTable[j-1];
+          picIsrTable[i]=irqNum;
          shifted=1;
          break;
       }
       i++;
     }
-     if (!shifted) picPrioTable[picPrioTblPtr] =irqNum;
-
+     if (!shifted) picIsrTable[picIsrTblPtr]=irqNum;
     if (irqNum >BSP_MICH_IRQ_MAX_OFFSET)
        GPPIrqInTbl |= (1<< (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)); 
     else      
        MainIrqInTbl |= (unsigned long long)(1LLU << irqNum);
-     picPrioTblPtr++;
+     picIsrTblPtr++;
  }
 #ifdef SHOW_MORE_INIT_SETTINGS
  val2 = (MainIrqInTbl>>32) & 0xffffffff;
@@ -280,23 +271,22 @@ static void CleanMainIrqTbl(int irqNum)
        (( 1 << (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)) & GPPIrqInTbl)))
  { /* If entry in table*/
     for (i=0; i<64; i++) {
-       if (picPrioTable[i]==irqNum) {/*remove it from the entry */
+       if (picIsrTable[i]==irqNum) {/*remove it from the entry */
          /* all other lower priority entries shifted left */
-	  for (j=i;j<picPrioTblPtr; j++) {
-              picPrioTable[j]=picPrioTable[j+1];
-          }
+          for (j=i;j<picIsrTblPtr; j++) 
+              picIsrTable[j]=picIsrTable[j+1];
          if (irqNum >BSP_MICH_IRQ_MAX_OFFSET)
            GPPIrqInTbl &= ~(1<< (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)); 
          else      
            MainIrqInTbl &= ~(1LLU << irqNum);
-          picPrioTblPtr--;
+          picIsrTblPtr--;
          break;
       }
     }
  }
 }

-void BSP_enable_irq_at_pic(const rtems_irq_number irqNum)
+void BSP_enable_pic_irq(const rtems_irq_number irqNum)
 {
  unsigned bitNum, regNum;
  unsigned int level;
@@ -304,14 +294,12 @@ void BSP_enable_irq_at_pic(const rtems_irq_number irqNum)
  if ( !is_pic_irq(irqNum) )
  	return;

-  bitNum = (((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET)%32;
-  regNum = (((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET)>>5;
+  bitNum = modIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET);
+  regNum = divIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET);

  rtems_interrupt_disable(level); 

-#ifdef DynamicIsrTable
  UpdateMainIrqTbl((int) irqNum);
-#endif
  BSP_irqMask_cache[regNum] |= (1 << bitNum);

  out_le32(BSP_irqMask_reg[regNum], BSP_irqMask_cache[regNum]);
@@ -320,9 +308,9 @@ void BSP_enable_irq_at_pic(const rtems_irq_number irqNum)
  rtems_interrupt_enable(level);
 }

-void BSP_enable_pic_irq(const rtems_irq_number irqNum)
+void BSP_enable_irq_at_pic(const rtems_irq_number irqNum)
 {
-	BSP_enable_irq_at_pic(irqNum);
+	BSP_enable_pic_irq(irqNum);
 }

 int BSP_disable_irq_at_pic(const rtems_irq_number irqNum)
@@ -334,14 +322,12 @@ int BSP_disable_irq_at_pic(const rtems_irq_number irqNum)
  if ( ! is_pic_irq(irqNum) )
  	return -1;

-  bitNum = (((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET)%32;
-  regNum = (((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET)>>5;
+  bitNum = modIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET);
+  regNum = divIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET);

  rtems_interrupt_disable(level); 

-#ifdef DynamicIsrTable
  CleanMainIrqTbl((int) irqNum);
-#endif

  rval = BSP_irqMask_cache[regNum] & (1<<bitNum);

@@ -360,29 +346,35 @@ void BSP_disable_pic_irq(const rtems_irq_number irqNum)
 	(void)BSP_disable_irq_at_pic(irqNum);
 }

-/* Use shared/irq : 2008 */
-int BSP_setup_the_pic(rtems_irq_global_settings* config)  
+int BSP_setup_the_pic(rtems_irq_global_settings *config)  /* adapt the same name as shared/irq */
 {
    int i;

-    BSP_config = *config;
-    default_rtems_hdl = config->defaultEntry.hdl;
-    rtems_hdl_tbl     = config->irqHdlTbl;
+	internal_config   = config;
+	default_rtems_hdl = config->defaultEntry.hdl;
+	rtems_hdl_tbl     = config->irqHdlTbl;

    /* Get ready for discovery BSP */
-    BSP_irqMask_reg[0]= (volatile unsigned int *) (GT64x60_REG_BASE + GT64260_CPU_INT_MASK_LO);
-    BSP_irqMask_reg[1]= (volatile unsigned int *) (GT64x60_REG_BASE + GT64260_CPU_INT_MASK_HI);
-    BSP_irqCause_reg[0]= (volatile unsigned int *) (GT64x60_REG_BASE + GT64260_MAIN_INT_CAUSE_LO);
-    BSP_irqCause_reg[1]= (volatile unsigned int *) (GT64x60_REG_BASE + GT64260_MAIN_INT_CAUSE_HI);
-    BSP_irqMask_reg[2]= (volatile unsigned int *) (GT64x60_REG_BASE + GT_GPP_Interrupt_Mask);
-    BSP_irqCause_reg[2]= (volatile unsigned int *) (GT64x60_REG_BASE + GT_GPP_Value);
+    BSP_irqMask_reg[0]= (volatile unsigned int *) (GT64260_REG_BASE + GT_CPU_INT_MASK_LO);
+    BSP_irqMask_reg[1]= (volatile unsigned int *) (GT64260_REG_BASE + GT_CPU_INT_MASK_HI);
+    BSP_irqMask_reg[2]= (volatile unsigned int *) (GT64260_REG_BASE + GT_GPP_Interrupt_Mask);
+
+    BSP_irqCause_reg[0]= (volatile unsigned int *) (GT64260_REG_BASE + GT_MAIN_INT_CAUSE_LO);
+    BSP_irqCause_reg[1]= (volatile unsigned int *) (GT64260_REG_BASE + GT_MAIN_INT_CAUSE_HI);
+    BSP_irqCause_reg[2]= (volatile unsigned int *) (GT64260_REG_BASE + GT_GPP_Interrupt_Cause);
+
+#ifdef EDGE_TRIGGER

    /* Page 401, Table 598:
     * Comm Unit Arbiter Control register :
     * bit 10:GPP interrupts as level sensitive(1) or edge sensitive(0).
-     * MOTload default is set as level sensitive(1). Set it agin to make sure.
+     * We set the GPP interrupts to be edge sensitive.
+     * MOTload default is set as level sensitive(1).
     */
-    out_le32(GT_CommUnitArb_Ctrl, (in_le32(GT_CommUnitArb_Ctrl)| (1<<10)));
+    outl((inl(GT_CommUnitArb_Ctrl)& (~(1<<10))), GT_CommUnitArb_Ctrl);
+#else
+    outl((inl(GT_CommUnitArb_Ctrl)| (1<<10)), GT_CommUnitArb_Ctrl);
+#endif

 #if 0
    printk("BSP_irqMask_reg[0] = 0x%x, BSP_irqCause_reg[0] 0x%x\n", 
@@ -396,13 +388,13 @@ int BSP_setup_the_pic(rtems_irq_global_settings* config)
 	   in_le32(BSP_irqCause_reg[2]));
 #endif

-    /* Initialize the interrupt related  registers */
+    /* Initialize the interrupt related GT64260 registers */
    for (i=0; i<3; i++) {
      out_le32(BSP_irqCause_reg[i], 0);
      out_le32(BSP_irqMask_reg[i], 0);
    }         
    in_le32(BSP_irqMask_reg[2]);
-    compute_pic_masks_from_prio();
+    compute_pic_masks_from_prio(config);

 #if 0
    printk("BSP_irqMask_reg[0] = 0x%x, BSP_irqCause_reg[0] 0x%x\n", 
@@ -416,65 +408,74 @@ int BSP_setup_the_pic(rtems_irq_global_settings* config)
 	   in_le32(BSP_irqCause_reg[2]));
 #endif

-    /*
-     * 
-     */
-    for (i=BSP_MICL_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET ; i++) {
-      if ( BSP_config.irqHdlTbl[i].hdl != BSP_config.defaultEntry.hdl) {
-	BSP_enable_irq_at_pic(i);
-	BSP_config.irqHdlTbl[i].on(&BSP_config.irqHdlTbl[i]);
-      }
-      else {
-	BSP_config.irqHdlTbl[i].off(&BSP_config.irqHdlTbl[i]);
-	BSP_disable_irq_at_pic(i);
-      }
-    }
-    for (i= BSP_MAIN_GPP7_0_IRQ; i < BSP_MAIN_GPP31_24_IRQ; i++) 
-      BSP_enable_irq_at_pic(i);
-    
    return(1);
 }

+/*
+ * This function check that the value given for the irq line
+ * is valid.
+ */
+
 /*
 * High level IRQ handler called from shared_raw_irq_code_entry
 */
+
 int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum)
 {
  unsigned long irqCause[3]={0, 0,0};
+  register unsigned long selectCause;
  unsigned oldMask[3]={0,0,0};
-  int loop=0, wloop=0, i=0, j;
-  int irq=0, group=0;
+  register unsigned i=0, j, irq=0, bitmask=0, group=0;

  if (excNum == ASM_DEC_VECTOR) {
-      bsp_irq_dispatch_list( rtems_hdl_tbl, BSP_DECREMENTER, default_rtems_hdl);
-      return 0;   
+
+  	bsp_irq_dispatch_list( rtems_hdl_tbl, BSP_DECREMENTER, default_rtems_hdl);
+
+    return 0;
+    
  }

  for (j=0; j<3; j++ ) oldMask[j] = BSP_irqMask_cache[j];
-  for (j=0; j<3; j++) irqCause[j] = in_le32(BSP_irqCause_reg[j]) & in_le32(BSP_irqMask_reg[j]);

-  while (((irq = picPrioTable[i++])!=-1)&& (loop++ < MAX_IRQ_LOOP))
-  {    
-    if (irqCause[group= irq/32] & ( 1<<(irq % 32))) {
+  if ((selectCause= in_le32((volatile unsigned *)0xf1000c70)) & HI_INT_CAUSE ){
+    irqCause[1] = (selectCause & BSP_irqMask_cache[1]);
+    irqCause[2] = in_le32(BSP_irqCause_reg[2]) & BSP_irqMask_cache[2];
+  }
+  else {
+    irqCause[0] = (selectCause & BSP_irqMask_cache[0]);
+    if ((irqCause[1] =(in_le32((volatile unsigned *)0xf1000c68)&BSP_irqMask_cache[1])))
+       irqCause[2] = in_le32(BSP_irqCause_reg[2]) & BSP_irqMask_cache[2];
+  }
+  
+  while ((irq = picIsrTable[i++])!=-1)
+  {
+    if (irqCause[group=(irq/32)] && (irqCause[group]&(bitmask=(1<<(irq % 32))))) {
      for (j=0; j<3; j++)
        BSP_irqMask_cache[j] &= (~ BSP_irq_prio_mask_tbl[j][irq]);

-      out_le32(BSP_irqMask_reg[0], BSP_irqMask_cache[0]);
-      out_le32(BSP_irqMask_reg[1], BSP_irqMask_cache[1]);
-      out_le32(BSP_irqMask_reg[2], BSP_irqMask_cache[2]);
-      in_le32(BSP_irqMask_reg[2]);
+      RTEMS_COMPILER_MEMORY_BARRIER();
+      out_le32((volatile unsigned *)0xf1000c1c, BSP_irqMask_cache[0]);
+      out_le32((volatile unsigned *)0xf1000c6c, BSP_irqMask_cache[1]);
+      out_le32((volatile unsigned *)0xf100f10c, BSP_irqMask_cache[2]);
+      in_le32((volatile unsigned *)0xf100f10c);

-      bsp_irq_dispatch_list( rtems_hdl_tbl, irq, default_rtems_hdl);
+#ifdef EDGE_TRIGGER
+      if (irq > BSP_MICH_IRQ_MAX_OFFSET)
+         out_le32(BSP_irqCause_reg[2], ~bitmask);/* Till Straumann: Ack the edge triggered GPP IRQ */
+#endif

+  	  bsp_irq_dispatch_list( rtems_hdl_tbl, irq, default_rtems_hdl);
+      
      for (j=0; j<3; j++ ) BSP_irqMask_cache[j] = oldMask[j];
- 
-      out_le32(BSP_irqMask_reg[0], oldMask[0]);
-      out_le32(BSP_irqMask_reg[1], oldMask[1]);
-      out_le32(BSP_irqMask_reg[2], oldMask[2]);
-      in_le32(BSP_irqMask_reg[2]);
+      break;
    }
  }

+  out_le32((volatile unsigned *)0xf1000c1c, oldMask[0]);
+  out_le32((volatile unsigned *)0xf1000c6c, oldMask[1]);
+  out_le32((volatile unsigned *)0xf100f10c, oldMask[2]);
+  in_le32((volatile unsigned *)0xf100f10c);
+
  return 0;
 }

@@ -483,10 +484,10 @@ void BSP_printPicIsrTbl()
 {
  int i;

-  printf("picPrioTable[12]={ {irq# : ");
+  printk("picIsrTable[12]={");
  for (i=0; i<12; i++)
-    printf("%d,", picPrioTable[i]);
-  printf("}\n");
+    printk("%d,", picIsrTable[i]);
+  printk("}\n");

-  printf("GPPIrqInTbl: 0x%x :\n", GPPIrqInTbl);
+  printk("GPPIrqInTbl: 0x%x :\n", GPPIrqInTbl);
 }
--- a/c/src/lib/libbsp/powerpc/mvme5500/irq/irq_init.c
+++ b/c/src/lib/libbsp/powerpc/mvme5500/irq/irq_init.c
@@ -36,18 +36,10 @@ static int connected(void) {return 1;}

 static rtems_irq_connect_data     	rtemsIrq[BSP_IRQ_NUMBER];
 static rtems_irq_global_settings     	initial_config;
-
-#ifdef BSP_SHARED_HANDLER_SUPPORT
-static rtems_irq_connect_data     	defaultIrq = {
-  /* vectorIdex,  hdl	    ,handle  , on	, off	   , isOn      ,next_handler, */
-  0, 		  nop_func  , NULL   , nop_func	, nop_func , not_connected, 0
-};
-#else
 static rtems_irq_connect_data     	defaultIrq = {
  /* vectorIdex,	 hdl	  , handle	, on		, off		, isOn */
  0, 			 nop_func  , NULL	, nop_func	, nop_func	, not_connected
 };
-#endif

 rtems_irq_prio BSPirqPrioTable[BSP_PIC_IRQ_NUMBER]={
  /*
@@ -143,6 +135,12 @@ void BSP_rtems_irq_mng_init(unsigned cpuId)
 #ifdef TRACE_IRQ_INIT  
  printk("Done setup irq mngt configuration\n");
 #endif
+  
+  /* I don't really understand why all sources are enable here... (T.S) */
+  for (i= BSP_MAIN_GPP7_0_IRQ; i <= BSP_MAIN_GPP31_24_IRQ; i++) 
+      BSP_enable_pic_irq(i);
+
+  rtems_interrupt_enable(l);

 #ifdef TRACE_IRQ_INIT  
  printk("RTEMS IRQ management is now operationnal\n");
--- a/c/src/lib/libbsp/powerpc/mvme5500/network/if_100MHz/GT64260eth.c
+++ b/c/src/lib/libbsp/powerpc/mvme5500/network/if_100MHz/GT64260eth.c
@@ -7,6 +7,12 @@
 * Acknowledgements:
 * netBSD : Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 
 * Marvell : NDA document for the discovery system controller
+ * The author referenced two RTEMS network drivers of other NICs.
+ * rtems : 1) dec21140.c, a network driver for for TULIP based Ethernet Controller
+ *            (C) 1999 Emmanuel Raguet. raguet@crf.canon.fr
+ *
+ *         2) yellowfin.c, a network driver for the SVGM5 BSP.
+ *           Stanford Linear Accelerator Center, Till Straumann 
 *
 * Some notes from the author, S. Kate Feng :
 *
@@ -360,7 +366,8 @@ int rtems_GT64260eth_driver_attach(struct rtems_bsdnet_ifconfig *config, int att
  if (unit < 0) return 0;
 
  printk("\nEthernet driver name %s unit %d \n",name, unit);
-  printk("RTEMS-mvme5500 BSP Copyright (c) 2004, Brookhaven National Lab., Shuchen Kate Feng \n");
+  printk("(c) 2004, Brookhaven National Lab. <feng1@bnl.gov> (RTEMS/mvme5500 port)\n");
+
  /* Make certain elements e.g. descriptor lists are aligned. */
  softc_mem = rtems_bsdnet_malloc(sizeof(*sc) + SOFTC_ALIGN, M_FREE, M_NOWAIT);

@@ -386,7 +393,7 @@ int rtems_GT64260eth_driver_attach(struct rtems_bsdnet_ifconfig *config, int att
  } else {
    printk("Read EEPROM ");
     for (i = 0; i < 6; i++)
-       hwaddr[i] = ReadConfVPD_buff(VPD_ENET0_OFFSET+i);
+       hwaddr[i] = ConfVPD_buff[VPD_ENET0_OFFSET+i];
  }

 #ifdef GT_DEBUG
@@ -1130,6 +1137,7 @@ static void GTeth_tx_stop(struct GTeth_softc *sc)
  sc->arpcom.ac_if.if_timer = 0;
 }

+/* TOCHECK : Should it be about rx or tx ? */
 static void GTeth_ifchange(struct GTeth_softc *sc)
 {
  if (GTeth_debug>0) printk("GTeth_ifchange(");
@@ -1437,7 +1445,6 @@ static void GTeth_hash_init(struct GTeth_softc *sc)
 #endif
 }

-#ifdef GT64260eth_DEBUG
 static void GT64260eth_error(struct GTeth_softc *sc)
 {
  struct ifnet	        *ifp = &sc->arpcom.ac_if;
@@ -1467,7 +1474,7 @@ static void GT64260eth_error(struct GTeth_softc *sc)
  sc->intr_errsts[sc->intr_err_ptr1++]=0;  
  sc->intr_err_ptr1 %= INTR_ERR_SIZE;   /* Till Straumann */
 }
-#endif
+

 /* The daemon does all of the work; RX, TX and cleaning up buffers/descriptors */
 static void GT64260eth_daemon(void *arg)
@@ -1541,9 +1548,7 @@ static void GT64260eth_daemon(void *arg)
       ifp->if_flags &= ~IFF_OACTIVE;

       /* Log errors and other uncommon events. */
-#ifdef GT64260eth_DEBUG
       if (events & ERR_EVENT) GT64260eth_error(sc); 
-#endif
  } /* end for(;;) { rtems_bsdnet_event_receive() .....*/

  ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
--- a/c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/POSSIBLEBUG
+++ b/c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/POSSIBLEBUG
@@ -0,0 +1,4 @@
+S. Kate Feng <feng1@bnl.gov>, Sept. 06, 2007
+
+This driver boots smoothly with the 1GHZ media.
+It might not boot with the 10/100MHZ media.
--- a/c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/if_wm.c
+++ b/c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/if_wm.c
@@ -1,6 +1,5 @@
 /*
 * Copyright (c) 2004,2005 RTEMS/Mvme5500 port by S. Kate Feng <feng1@bnl.gov>
- *      under the Deaprtment of Energy contract DE-AC02-98CH10886
 *      Brookhaven National Laboratory, All rights reserved
 *
 * Acknowledgements:
@@ -26,7 +25,8 @@
 *    hardware auto-neg. state machine disabled. PCI control "snoop
 *    to WB region", MII mode (PHY) instead of TBI mode.
 * 6) We currently only use 32-bit (instead of 64-bit) DMA addressing.
- * 7) Implementation for Jumbo Frame and TCP checksum is not completed yet.
+ * 7) Support for checksum offloading and TCP segmentation offload will
+ *    be available for releasing in 2008, upon request, if I still believe.
 *    
 */

@@ -34,11 +34,8 @@

 #define INET

-/*#define RTEMS_ETHERMTU_JUMBO*/
-
 #include <rtems.h>
 #include <rtems/bspIo.h>      /* printk */
-
 #include <stdio.h>	      /* printf for statistics */
 #include <string.h>

@@ -67,7 +64,6 @@
 #include <net/if_dl.h>
 #include <netinet/in.h>
 #include <netinet/if_ether.h>
-#include <net/ethernet.h>

 #ifdef INET
 #include <netinet/in_var.h>
@@ -79,12 +75,14 @@
 #include <bsp/if_wmreg.h>
 #define	WMREG_RADV	0x282c	/* Receive Interrupt Absolute Delay Timer */

+/*#define CKSUM_OFFLOAD*/
+
 #define	ETHERTYPE_FLOWCONTROL	0x8808	/* 802.3x flow control packet */

-#define i82544EI_TASK_NAME "IGHz"
+#define i82544EI_TASK_NAME "IGHZ"
 #define SOFTC_ALIGN        4095

-#define IF_ERR_BUFSZE        16
+#define INTR_ERR_SIZE        16

 /*#define WM_DEBUG*/
 #ifdef WM_DEBUG
@@ -92,7 +90,7 @@
 #define	WM_DEBUG_TX		0x02
 #define	WM_DEBUG_RX		0x04
 #define	WM_DEBUG_GMII		0x08
-static int	wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK; /* May 7, 2009 */
+int	wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK;

 #define	DPRINTF(x, y)	if (wm_debug & (x)) printk y
 #else
@@ -111,12 +109,12 @@ static int	wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK; /* May 7, 2009 */
 
 #define ALL_EVENTS (KILL_EVENT|START_TRANSMIT_EVENT|RX_EVENT|TX_EVENT|ERR_EVENT|INIT_EVENT)

-/* <skf> used 64 in 4.8.0, TOD; try 4096 */
-#define	NTXDESC		        256
+
+#define	NTXDESC		        128
 #define	NTXDESC_MASK		(NTXDESC - 1)
 #define	WM_NEXTTX(x)		(((x) + 1) & NTXDESC_MASK)

-#define	NRXDESC		        256
+#define	NRXDESC		        64
 #define	NRXDESC_MASK		(NRXDESC - 1)
 #define	WM_NEXTRX(x)		(((x) + 1) & NRXDESC_MASK)
 #define	WM_PREVRX(x)		(((x) - 1) & NRXDESC_MASK)
@@ -125,10 +123,9 @@ static int	wm_debug = WM_DEBUG_TX|WM_DEBUG_RX|WM_DEBUG_LINK; /* May 7, 2009 */
 #define	WM_CDTXOFF(x)	WM_CDOFF(sc_txdescs[(x)])
 #define	WM_CDRXOFF(x)	WM_CDOFF(sc_rxdescs[(x)])

-#define TXQ_HiLmt_OFF 32
+#define TXQ_HiLmt_OFF 64

 static uint32_t TxDescCmd;
-static unsigned BSP_1GHz_membase;

 /*
 * Software state per device.
@@ -139,9 +136,9 @@ struct wm_softc {
 	struct mbuf *txs_mbuf[NTXDESC];	       /* transmit buffer memory */
 	struct mbuf *rxs_mbuf[NRXDESC];	       /* receive buffer memory */
        struct wm_softc *next_module;
-        volatile unsigned int if_errsts[IF_ERR_BUFSZE]; /* intr_status */
-        unsigned int if_err_ptr1;     /* ptr used in i82544EI_error() */
-        unsigned int if_err_ptr2;     /* ptr used in ISR */
+        volatile unsigned int intr_errsts[INTR_ERR_SIZE]; /* intr_status */
+        unsigned int intr_err_ptr1;     /* ptr used in i82544EI_error() */
+        unsigned int intr_err_ptr2;     /* ptr used in ISR */
 	int txs_firstdesc;		/* first descriptor in packet */
 	int txs_lastdesc;		/* last descriptor in packet */
 	int txs_ndesc;			/* # of descriptors used */
@@ -171,16 +168,15 @@ struct wm_softc {
 	int	sc_rxptr;		/* next ready Rx descriptor/queue ent */
 	int	sc_rxdiscard;
 	int	sc_rxlen;
-
 	uint32_t sc_ctrl;		/* prototype CTRL register */
+#if 0
 	uint32_t sc_ctrl_ext;		/* prototype CTRL_EXT register */
-
+#endif
 	uint32_t sc_icr;		/* prototype interrupt bits */
 	uint32_t sc_tctl;		/* prototype TCTL register */
 	uint32_t sc_rctl;		/* prototype RCTL register */
 	uint32_t sc_tipg;		/* prototype TIPG register */
 	uint32_t sc_fcrtl;		/* prototype FCRTL register */
-	uint32_t sc_pba;		/* prototype PBA register */

 	int sc_mchash_type;		/* multicast filter offset */

@@ -188,6 +184,11 @@ struct wm_softc {
        struct {
          volatile unsigned long     rxInterrupts;
          volatile unsigned long     txInterrupts;
+          unsigned long	    txMultiBuffPacket;
+          unsigned long     txMultiMaxLen;
+          unsigned long     txSinglMaxLen;
+          unsigned long     txMultiMaxLoop;
+          unsigned long     txBuffMaxLen;
 	  unsigned long     linkInterrupts;
          unsigned long     length_errors;
          unsigned long	    frame_errors;
@@ -223,20 +224,22 @@ struct wm_softc {
 static struct wm_softc *root_i82544EI_dev = NULL;

 static void i82544EI_ifstart(struct ifnet *ifp);
-static int  wm_ioctl(struct ifnet *ifp, ioctl_command_t cmd,caddr_t data);
+static int  wm_ioctl(struct ifnet *ifp, u_long cmd,uint32_t data);
 static void i82544EI_ifinit(void *arg);
 static void wm_stop(struct ifnet *ifp, int disable);
-static void wm_gmii_mediainit(struct wm_softc *sc);

 static void wm_rxdrain(struct wm_softc *sc);
 static int  wm_add_rxbuf(struct wm_softc *sc, int idx);
 static int  wm_read_eeprom(struct wm_softc *sc,int word,int wordcnt, uint16_t *data);
 static void i82544EI_daemon(void *arg);
 static void wm_set_filter(struct wm_softc *sc);
-static void i82544EI_rx(struct wm_softc *sc);
-static void i82544EI_isr(rtems_irq_hdl_param handle);
+
+static void i82544EI_isr(void);
 static void i82544EI_sendpacket(struct wm_softc *sc, struct mbuf *m);
-extern int  pci_mem_find(), pci_io_find(), pci_get_capability();
+extern int pci_mem_find(int b, int d, int f, int reg, unsigned *basep,unsigned *sizep);
+extern int pci_io_find(int b, int d, int f, int reg,unsigned *basep,unsigned *sizep);
+extern int pci_get_capability(int b, int d, int f, int capid,int *offset,uint32_t *value);
+extern char * ether_sprintf1(void);

 static void i82544EI_irq_on(const rtems_irq_connect_data *irq)
 {
@@ -268,7 +271,6 @@ static int i82544EI_irq_is_on(const rtems_irq_connect_data *irq)
 static rtems_irq_connect_data i82544IrqData={
 	BSP_GPP_82544_IRQ,
 	(rtems_irq_hdl) i82544EI_isr,
-        (rtems_irq_hdl_param) NULL,
 	(rtems_irq_enable) i82544EI_irq_on,
 	(rtems_irq_disable) i82544EI_irq_off,
 	(rtems_irq_is_enabled) i82544EI_irq_is_on, 
@@ -288,12 +290,9 @@ int rtems_i82544EI_driver_attach(struct rtems_bsdnet_ifconfig *config, int attac

  unit = rtems_bsdnet_parse_driver_name(config, &name);
  if (unit < 0) return 0;
-
-  if ( !strncmp((const char *)name,"autoz",5))
-     memcpy(name,"gtGHz",5);
-          
-  printk("\nAttaching MVME5500 1GHz NIC%d\n", unit); 
-  printk("RTEMS-mvme5500 BSP Copyright (c) 2004,2005,2008, Brookhaven National Lab., Shuchen Kate Feng \n");
+ 
+  printk("\nEthernet driver name %s unit %d \n",name, unit);
+  printk("Copyright (c) 2004,2005 S. Kate Feng <feng1@bnl.gov> (RTEMS/mvme5500 port)\n");

  /* Make sure certain elements e.g. descriptor lists are aligned.*/ 
  softc_mem = rtems_bsdnet_malloc(sizeof(*sc) + SOFTC_ALIGN, M_FREE, M_NOWAIT);
@@ -311,7 +310,7 @@ int rtems_i82544EI_driver_attach(struct rtems_bsdnet_ifconfig *config, int attac
 			unit-1,&b, &d, &f))
    rtems_panic("i82544EI device ID not found\n");

-#ifdef WM_DEBUG
+#if WM_DEBUG
  printk("82544EI:b%d, d%d, f%d\n", b, d,f);
 #endif

@@ -319,18 +318,13 @@ int rtems_i82544EI_driver_attach(struct rtems_bsdnet_ifconfig *config, int attac
  if ( pci_mem_find(b,d,f,PCI_MAPREG_START, &sc->sc_membase, &sc->sc_memsize))
     rtems_panic("i82544EI: unable to map memory space\n");

-#ifdef WM_DEBUG 
-  printk("Memory base addr 0x%x\n", sc->sc_membase);
-#endif
-  BSP_1GHz_membase= sc->sc_membase;
-
 #ifdef WM_DEBUG
  printk("Memory base addr 0x%x\n", sc->sc_membase);
  printk("txdesc[0] addr:0x%x, rxdesc[0] addr:0x%x, sizeof sc %d\n",&sc->sc_txdescs[0], &sc->sc_rxdescs[0], sizeof(*sc));      
 #endif


-  sc->sc_ctrl=CSR_READ(sc,WMREG_CTRL);  
+  sc->sc_ctrl |=CSR_READ(sc,WMREG_CTRL);  
  /*
   * Determine a few things about the bus we're connected to.
   */
@@ -368,10 +362,11 @@ int rtems_i82544EI_driver_attach(struct rtems_bsdnet_ifconfig *config, int attac
  enaddr[4] = myea[2] & 0xff;
  enaddr[5] = myea[2] >> 8;

+
  memcpy(sc->arpcom.ac_enaddr, enaddr, ETHER_ADDR_LEN);
 #ifdef WM_DEBUG
  printk("%s: Ethernet address %s\n", sc->dv_xname,
-	    ether_sprintf(enaddr));
+	    ether_sprintf1(enaddr));
 #endif

  /*
@@ -402,39 +397,13 @@ int rtems_i82544EI_driver_attach(struct rtems_bsdnet_ifconfig *config, int attac
  CSR_WRITE(sc,WMREG_CTRL_EXT, sc->sc_ctrl_ext);
 #endif

-  /*
-   * Determine if we're TBI or GMII mode, and initialize the
-   * media structures accordingly.
-   */
-  if ((CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) {
-    /* 1000BASE-X : fiber  (TBI mode) 
-       wm_tbi_mediainit(sc); */
-  } else {   /* 1000BASE-T : copper (internal PHY mode), for the mvme5500 */
-	   wm_gmii_mediainit(sc);
-  }  
-
  ifp = &sc->arpcom.ac_if;
  /* set this interface's name and unit */
  ifp->if_unit = unit;
  ifp->if_name = name;
  ifp->if_softc = sc;
  ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
-#ifdef RTEMS_ETHERMTU_JUMBO 
-  sc->arpcom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
-  ifp->if_mtu = config->mtu ? config->mtu : ETHERMTU_JUMBO;
-#else
  ifp->if_mtu = config->mtu ? config->mtu : ETHERMTU;
-#endif
-#ifdef RTEMS_CKSUM_OFFLOAD 
-  /* < skf> The following is really not related to jumbo frame
-  sc->arpcom.ec_capabilities |= ETHERCAP_VLAN_MTU;*/
-  ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
-		    IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
-		    IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
-		    IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx |
-                    IFCAP_TSOv4;  /* TCP segmentation offload. */
-#endif
-
  ifp->if_ioctl = wm_ioctl;
  ifp->if_start = i82544EI_ifstart;
  /*  ifp->if_watchdog = wm_watchdog;*/
@@ -449,8 +418,7 @@ int rtems_i82544EI_driver_attach(struct rtems_bsdnet_ifconfig *config, int attac
     rtems_build_name('I','G','H','Z'),0,0,0,&sc->daemonSync))
     rtems_panic("i82544EI: semaphore creation failed");

-  i82544IrqData.handle= (rtems_irq_hdl_param) sc;
-  /* sc->next_module = root_i82544EI_dev;*/
+  sc->next_module = root_i82544EI_dev;
  root_i82544EI_dev = sc;

  /* Attach the interface. */
@@ -463,47 +431,6 @@ int rtems_i82544EI_driver_attach(struct rtems_bsdnet_ifconfig *config, int attac
  return(1);
 }

-/*
- * wm_reset:
- *
- *	Reset the i82544 chip.
- */
-static void wm_reset(struct wm_softc *sc)
-{
-  int i;
-
- /* Packet Buffer Allocation (PBA)
-  * Writing PBA sets the receive portion of the buffer.
-  * the remainder is used for the transmit buffer.
-  *
-  * 82544 has a Packet Buffer of 64K.
-  * Default allocation : PBA=40K for Rx, leaving 24K for Tx.
-  * Default for jumbo: PBA=48K for Rx, leaving 16K for Tx.
-  */  
-  sc->sc_pba = sc->arpcom.ac_if.if_mtu > 8192 ? PBA_40K : PBA_48K;
-  CSR_WRITE(sc, WMREG_PBA, sc->sc_pba);
-
-  /* device reset */
-  CSR_WRITE(sc, WMREG_CTRL, CTRL_RST);
-  rtems_bsp_delay(10000);
-
-  for (i = 0; i < 1000; i++) {
-      if ((CSR_READ(sc, WMREG_CTRL) & CTRL_RST) == 0)
-	break;
-      rtems_bsp_delay(20);
-  }
-  if (CSR_READ(sc, WMREG_CTRL) & CTRL_RST)
-      printk("Intel 82544 1GHz reset failed to complete\n");
-
-  sc->sc_ctrl_ext = CSR_READ(sc,WMREG_CTRL_EXT);
-  sc->sc_ctrl_ext |= CTRL_EXT_EE_RST;
-  CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext);  
-  CSR_READ(sc, WMREG_STATUS);
-  /* Wait for EEPROM reload */
-  rtems_bsp_delay(2000);
-  sc->sc_ctrl= CSR_READ(sc, WMREG_CTRL);
-}
-
 /*
 * i82544EI_ifstart:		[ifnet interface function]
 *
@@ -536,21 +463,27 @@ static void i82544EI_stats(struct wm_softc *sc)
 {
  struct ifnet *ifp = &sc->arpcom.ac_if;

-  printf("    Ghost Interrupts:%-8lu\n", sc->stats.ghostInterrupts);
-  printf("       Rx Interrupts:%-8lu\n", sc->stats.rxInterrupts);
+  printf("       Rx Interrupts:%-8u\n", sc->stats.rxInterrupts);
  printf("     Receive Packets:%-8u\n", CSR_READ(sc,WMREG_GPRC));
-  printf("     Receive Overrun:%-8lu\n", sc->stats.rxOvrRunInterrupts);
+  printf("     Receive Overrun:%-8u\n", sc->stats.rxOvrRunInterrupts);
  printf("     Receive  errors:%-8u\n", CSR_READ(sc,WMREG_RXERRC));
-  printf("   Rx sequence error:%-8lu\n", sc->stats.rxSeqErr);
-  printf("      Rx /C/ ordered:%-8lu\n", sc->stats.rxC_ordered);
+  printf("   Rx sequence error:%-8u\n", sc->stats.rxSeqErr);
+  printf("      Rx /C/ ordered:%-8u\n", sc->stats.rxC_ordered);
  printf("    Rx Length Errors:%-8u\n", CSR_READ(sc,WMREG_RLEC));
-  printf("       Tx Interrupts:%-8lu\n", sc->stats.txInterrupts);
+  printf("       Tx Interrupts:%-8u\n", sc->stats.txInterrupts);
+#if 0
+  printf("Multi-BuffTx Packets:%-8u\n", sc->stats.txMultiBuffPacket);
+  printf("Multi-BuffTx max len:%-8u\n", sc->stats.txMultiMaxLen);
+  printf("SingleBuffTx max len:%-8u\n", sc->stats.txSinglMaxLen);
+  printf("Multi-BuffTx maxloop:%-8u\n", sc->stats.txMultiMaxLoop);
+  printf("Tx buffer max len   :%-8u\n", sc->stats.txBuffMaxLen);
+#endif
  printf("   Transmitt Packets:%-8u\n", CSR_READ(sc,WMREG_GPTC));
-  printf("   Transmitt  errors:%-8lu\n", ifp->if_oerrors);
-  printf("         Active Txqs:%-8lu\n", sc->txq_nactive); 
+  printf("   Transmitt  errors:%-8u\n", ifp->if_oerrors);
+  printf("         Active Txqs:%-8u\n", sc->txq_nactive); 
  printf("          collisions:%-8u\n", CSR_READ(sc,WMREG_COLC));
  printf("          Crc Errors:%-8u\n", CSR_READ(sc,WMREG_CRCERRS));
-  printf("  Link Status Change:%-8lu\n", sc->stats.linkStatusChng);
+  printf("  Link Status Change:%-8u\n", sc->stats.linkStatusChng);
 }

 /*
@@ -558,7 +491,7 @@ static void i82544EI_stats(struct wm_softc *sc)
 *
 *	Handle control requests from the operator.
 */
-static int wm_ioctl(struct ifnet *ifp, ioctl_command_t cmd,caddr_t data)
+static int wm_ioctl(struct ifnet *ifp, u_long cmd,uint32_t data)
 {
  struct wm_softc *sc = ifp->if_softc;
  int error=0;
@@ -590,9 +523,9 @@ static int wm_ioctl(struct ifnet *ifp, ioctl_command_t cmd,caddr_t data)
 *
 *	Interrupt service routine.
 */
-static void i82544EI_isr(rtems_irq_hdl_param handle)
+static void i82544EI_isr()
 {
-  volatile struct wm_softc *sc = (struct wm_softc *) handle;
+  volatile struct wm_softc *sc = root_i82544EI_dev;
  uint32_t icr;
  rtems_event_set  events=0;

@@ -616,8 +549,8 @@ static void i82544EI_isr(rtems_irq_hdl_param handle)
     events |= INIT_EVENT;
  }
  if (icr & ICR_RXSEQ) /* framing error */ {
-     sc->if_errsts[sc->if_err_ptr2++]=icr;
-     if ( sc->if_err_ptr2 ==IF_ERR_BUFSZE) sc->if_err_ptr2=0;
+     sc->intr_errsts[sc->intr_err_ptr2++]=icr;
+     sc->intr_err_ptr2 %=INTR_ERR_SIZE; /* Till Straumann */
     events |= ERR_EVENT;
     sc->stats.rxSeqErr++;
  }
@@ -675,12 +608,15 @@ static void i82544EI_sendpacket(struct wm_softc *sc, struct mbuf *m)
         * The other way is effective for packets < 2K
         */
        if ( ((y=(len+mtp->m_len)) > sizeof(union mcluster))) {
-          printk(" >%d, use next descriptor\n", sizeof(union mcluster));
+          printk(">2048, use next descriptor\n");
 	  break; 
        }
        memcpy((void *)pt,(char *)mtp->m_data, mtp->m_len);
        pt += mtp->m_len;
        len += mtp->m_len;
+#if 0
+        sc->stats.txSinglMaxLen= MAX(mtp->m_len, sc->stats.txSinglMaxLen);
+#endif
      } /* end for loop */
      mdest->m_len=len;
      sc->txs_mbuf[sc->txq_next] = mdest;
@@ -694,8 +630,15 @@ static void i82544EI_sendpacket(struct wm_softc *sc, struct mbuf *m)
         sc->txq_free--;
      else
         rtems_panic("i8254EI : no more free descriptors");
+#if 0
+      sc->stats.txMultiMaxLen= MAX(mdest->m_len, sc->stats.txMultiMaxLen);
+      sc->stats.txMultiBuffPacket++;
+#endif
    } /* end for while */
    /* free old mbuf chain */
+#if 0
+    sc->stats.txMultiMaxLoop=MAX(loop, sc->stats.txMultiMaxLoop);
+#endif
    m_freem(m); 
    m=0;
  }  /* end  multiple mbufs */
@@ -801,11 +744,12 @@ static void i82544EI_rx(struct wm_softc *sc)
 		    sc->dv_xname, i));

    status = sc->sc_rxdescs[i].wrx_status;
-    if ((status & WRX_ST_DD) == 0)  break; /* descriptor not done */
-
    errors = sc->sc_rxdescs[i].wrx_errors;
    len = le16toh(sc->sc_rxdescs[i].wrx_len);
    m = sc->rxs_mbuf[i];
+
+    if ((status & WRX_ST_DD) == 0)  break; /* descriptor not done */
+
    if (sc->sc_rxdiscard) {
       printk("RX: discarding contents of descriptor %d\n", i);
       wm_init_rxdesc(sc, i);
@@ -877,46 +821,16 @@ static int i82544EI_init_hw(struct wm_softc *sc)
  int i,error;
  uint8_t cksumfields;

-#if 0
-  /* KATETODO : sc_align_tweak */
-	/*
-	 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set.
-	 * There is a small but measurable benefit to avoiding the adjusment
-	 * of the descriptor so that the headers are aligned, for normal mtu,
-	 * on such platforms.  One possibility is that the DMA itself is
-	 * slightly more efficient if the front of the entire packet (instead
-	 * of the front of the headers) is aligned.
-	 *
-	 * Note we must always set align_tweak to 0 if we are using
-	 * jumbo frames.
-	 */
-#ifdef __NO_STRICT_ALIGNMENT
-	sc->sc_align_tweak = 0;
-#else
-	if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2))
-		sc->sc_align_tweak = 0;
-	else
-		sc->sc_align_tweak = 2;
-#endif /* __NO_STRICT_ALIGNMENT */
-#endif
-
  /* Cancel any pending I/O. */
  wm_stop(ifp, 0);

-  /* update statistics before reset */
-  ifp->if_collisions += CSR_READ(sc, WMREG_COLC);
-  ifp->if_ierrors += CSR_READ(sc, WMREG_RXERRC);
-
-  /* Reset the chip to a known state. */
-  wm_reset(sc);
-
  /* Initialize the error buffer ring */
-  sc->if_err_ptr1=0;
-  sc->if_err_ptr2=0;
-  for (i=0; i< IF_ERR_BUFSZE; i++) sc->if_errsts[i]=0;
+  sc->intr_err_ptr1=0;
+  sc->intr_err_ptr2=0;
+  for (i=0; i< INTR_ERR_SIZE; i++) sc->intr_errsts[i]=0;

  /* Initialize the transmit descriptor ring. */
-  memset( (void *) sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
+  memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
  sc->txq_free = NTXDESC;
  sc->txq_next = 0;
  sc->txs_lastdesc = 0;
@@ -935,8 +849,8 @@ static int i82544EI_init_hw(struct wm_softc *sc)
  CSR_WRITE(sc,WMREG_TDLEN, sizeof(sc->sc_txdescs));
  CSR_WRITE(sc,WMREG_TDH, 0);
  CSR_WRITE(sc,WMREG_TDT, 0);
-  CSR_WRITE(sc,WMREG_TIDV, 0 ); 
-  /* CSR_WRITE(sc,WMREG_TADV, 128);  not for 82544 */
+  CSR_WRITE(sc,WMREG_TIDV, 64 ); 
+  CSR_WRITE(sc,WMREG_TADV, 128);

  CSR_WRITE(sc,WMREG_TXDCTL, TXDCTL_PTHRESH(0) |
 		    TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0));
@@ -950,11 +864,10 @@ static int i82544EI_init_hw(struct wm_softc *sc)
   * Set up checksum offload parameters for
   * this packet.
   */
-#ifdef RTEMS_CKSUM_OFFLOAD
-  if (m0->m_pkthdr.csum_flags & (M_CSUM_TSOv4|M_CSUM_TSOv6|
-		    M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4|
-				 M_CSUM_TCPv6|M_CSUM_UDPv6)) {
-     if (wm_tx_offload(sc, txs, &TxDescCmd,&cksumfields) != 0) {
+#ifdef CKSUM_OFFLOAD
+  if (m0->m_pkthdr.csum_flags &
+     (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) {
+     if (wm_tx_cksum(sc, txs, &TxDescCmd,&cksumfields) != 0) {
 	 /* Error message already displayed. */
 	 continue;
     }
@@ -962,7 +875,7 @@ static int i82544EI_init_hw(struct wm_softc *sc)
 #endif
     TxDescCmd = 0;
     cksumfields = 0;
-#ifdef RTEMS_CKSUM_OFFLOAD
+#ifdef CKSUM_OFFLOAD
  }
 #endif

@@ -981,14 +894,14 @@ static int i82544EI_init_hw(struct wm_softc *sc)
   * Initialize the receive descriptor and receive job
   * descriptor rings.
   */
-  memset( (void *) sc->sc_rxdescs, 0, sizeof(sc->sc_rxdescs));
+  memset(sc->sc_rxdescs, 0, sizeof(sc->sc_rxdescs));
  CSR_WRITE(sc,WMREG_RDBAH, 0);
  CSR_WRITE(sc,WMREG_RDBAL, WM_CDRXADDR(sc));
  CSR_WRITE(sc,WMREG_RDLEN, sizeof(sc->sc_rxdescs));
  CSR_WRITE(sc,WMREG_RDH, 0);
  CSR_WRITE(sc,WMREG_RDT, 0);
  CSR_WRITE(sc,WMREG_RDTR, 0 |RDTR_FPD); 
-  /* CSR_WRITE(sc, WMREG_RADV, 256);  not for 82544.  */
+  CSR_WRITE(sc, WMREG_RADV, 256);

  for (i = 0; i < NRXDESC; i++) {
      if (sc->rxs_mbuf[i] == NULL) {
@@ -1017,14 +930,14 @@ static int i82544EI_init_hw(struct wm_softc *sc)
  for (i = 0; i < WM_VLAN_TABSIZE; i++)
       CSR_WRITE(sc,WMREG_VFTA + (i << 2), 0);

-#if 0
-  /* Use MOTLoad default
  /*
   * Set up flow-control parameters.
+   *
+   * XXX Values could probably stand some tuning.
   */
-  CSR_WRITE(sc,WMREG_FCAL, FCAL_CONST);/* same as MOTLOAD 0x00c28001 */
-  CSR_WRITE(sc,WMREG_FCAH, FCAH_CONST);/* same as MOTLOAD 0x00000100 */
-  CSR_WRITE(sc,WMREG_FCT, ETHERTYPE_FLOWCONTROL);/* same as MOTLoad 0x8808 */
+  CSR_WRITE(sc,WMREG_FCAL, FCAL_CONST);/*safe,even though MOTLOAD 0x00c28001 */
+  CSR_WRITE(sc,WMREG_FCAH, FCAH_CONST);/*safe,even though MOTLOAD 0x00000100 */
+  CSR_WRITE(sc,WMREG_FCT, ETHERTYPE_FLOWCONTROL);/*safe,even though MOTLoad 0x8808 */


  /* safe,even though MOTLoad default all 0 */
@@ -1032,14 +945,12 @@ static int i82544EI_init_hw(struct wm_softc *sc)

  CSR_WRITE(sc,WMREG_FCRTH, FCRTH_DFLT);
  CSR_WRITE(sc,WMREG_FCRTL, sc->sc_fcrtl);
-  /*KATETO   CSR_WRITE(sc,WMREG_FCTTV, FCTTV_DFLT);*/
-  CSR_WRITE(sc,WMREG_FCTTV, 0x100);
-#endif
+  CSR_WRITE(sc,WMREG_FCTTV, FCTTV_DFLT);

  sc->sc_ctrl &= ~CTRL_VME;
-  /* TODO : not here.
-     Configures flow control settings after link is established
-     sc->sc_ctrl |= CTRL_TFCE | CTRL_RFCE; */
+  /*sc->sc_ctrl |= CTRL_TFCE | CTRL_RFCE;*/
+  /* enable Big Endian Mode for the powerPC 
+  sc->sc_ctrl |= CTRL_BEM;*/

  /* Write the control registers. */
  CSR_WRITE(sc,WMREG_CTRL, sc->sc_ctrl);
@@ -1047,27 +958,12 @@ static int i82544EI_init_hw(struct wm_softc *sc)
  CSR_WRITE(sc,WMREG_CTRL_EXT, sc->sc_ctrl_ext);
 #endif

-  /* MOTLoad : WMREG_RXCSUM (0x5000)= 0, no Rx checksum offloading */ 
-#ifdef RTEMS_CKSUM_OFFLOAD
-  /*
-   * Set up checksum offload parameters.
-   */
-   reg = CSR_READ(sc, WMREG_RXCSUM);
-   reg &= ~(RXCSUM_IPOFL | RXCSUM_IPV6OFL | RXCSUM_TUOFL);
-   if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx)
-	    reg |= RXCSUM_IPOFL;
-   if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx))
-	    reg |= RXCSUM_IPOFL | RXCSUM_TUOFL;
-   if (ifp->if_capenable & (IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx))
-	    reg |= RXCSUM_IPV6OFL | RXCSUM_TUOFL;
-   CSR_WRITE(sc, WMREG_RXCSUM, reg);
-#endif
+  /* MOTLoad : WMREG_RXCSUM (0x5000)= 0, no Rx checksum offloading */  

  /*
   * Set up the interrupt registers.
   */
  CSR_WRITE(sc,WMREG_IMC, 0xffffffffU);
-
  /* Reading the WMREG_ICR clears the interrupt bits */
  CSR_READ(sc,WMREG_ICR);

@@ -1091,8 +987,7 @@ static int i82544EI_init_hw(struct wm_softc *sc)
   * we resolve the media type.
   */
  sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) |
-	    TCTL_COLD(TX_COLLISION_DISTANCE_FDX) |
-            TCTL_RTLC /* retransmit on late collision */; 
+	    TCTL_COLD(TX_COLLISION_DISTANCE_FDX) | TCTL_RTLC; /*transmitter enable*/

  /*
   * Set up the receive control register; we actually program
@@ -1100,31 +995,14 @@ static int i82544EI_init_hw(struct wm_softc *sc)
   * address offset type 0.
   *
   * Only the i82544 has the ability to strip the incoming
-   * CRC (RCTL_SECRC).
+   * CRC, so we don't enable that feature. (TODO)
   */
  sc->sc_mchash_type = 0;
  sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_LPE |
-    RCTL_DPF | RCTL_MO(sc->sc_mchash_type)|RCTL_SECRC;
+	    RCTL_DPF | RCTL_MO(sc->sc_mchash_type);

-  if (MCLBYTES == 2048) {
-     sc->sc_rctl |= RCTL_2k;
-  } else {
-	switch(MCLBYTES) {
-	case 4096:
-	     sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k;
-	     break;
-	case 8192:
-	     sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k;
-	     break;
-        case 16384:
-	     sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k;
-	     break;
-	default:
-	     rtems_panic("wm_init: MCLBYTES %d unsupported",
-		    MCLBYTES);
-	     break;
-	}
-  }
+  /* (MCLBYTES == 2048) */
+  sc->sc_rctl |= RCTL_2k;

 #ifdef WM_DEBUG
  printk("RDBAL 0x%x,RDLEN %d, RDT %d\n",CSR_READ(sc,WMREG_RDBAL),CSR_READ(sc,WMREG_RDLEN), CSR_READ(sc,WMREG_RDT));
@@ -1142,24 +1020,6 @@ static int i82544EI_init_hw(struct wm_softc *sc)
  return(0);
 }

-void BSP_rdTIDV()
-{
-  printf("Reg TIDV: 0x%x\n", in_le32((volatile unsigned *) (BSP_1GHz_membase+WMREG_TIDV)));
-}
-void BSP_rdRDTR()
-{
-  printf("Reg RDTR: 0x%x\n", in_le32((volatile unsigned *) (BSP_1GHz_membase+WMREG_RDTR)));
-}
-
-void BSP_setTIDV(int val)
-{
-  out_le32((volatile unsigned *) (BSP_1GHz_membase+WMREG_TIDV), val);
-}
-
-void BSP_setRDTR(int val)
-{
-  out_le32((volatile unsigned *) (BSP_1GHz_membase+WMREG_RDTR), val);
-}
 /*
 * i82544EI_ifinit:		[ifnet interface function]
 *
@@ -1375,7 +1235,6 @@ static int wm_read_eeprom_uwire(struct wm_softc *sc, int word, int wordcnt, uint
  return (0);
 }

-#if 0
 /*
 * wm_acquire_eeprom:
 *
@@ -1407,7 +1266,6 @@ static int wm_acquire_eeprom(struct wm_softc *sc)

  return (0);
 }
-#endif

 /*
 * wm_read_eeprom:
@@ -1512,7 +1370,7 @@ static void wm_set_filter(struct wm_softc *sc)
  mta_reg = WMREG_CORDOVA_MTA;
  sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE);

-  if (ifp->if_flags & IFF_BROADCAST)
+  /*  if (ifp->if_flags & IFF_BROADCAST)*/
     sc->sc_rctl |= RCTL_BAM;
  if (ifp->if_flags & IFF_PROMISC) {
     sc->sc_rctl |= RCTL_UPE;
@@ -1582,11 +1440,12 @@ static void wm_set_filter(struct wm_softc *sc)
 static void i82544EI_error(struct wm_softc *sc)
 {
  struct ifnet	        *ifp = &sc->arpcom.ac_if;
-  unsigned long		intr_status= sc->if_errsts[sc->if_err_ptr1];
+  unsigned long		intr_status= sc->intr_errsts[sc->intr_err_ptr1++];

  /* read and reset the status; because this is written
   * by the ISR, we must disable interrupts here
   */
+  sc->intr_err_ptr1 %=INTR_ERR_SIZE; /* Till Straumann */
  if (intr_status) {
    printk("Error %s%d:", ifp->if_name, ifp->if_unit);
    if (intr_status & ICR_RXSEQ) {
@@ -1596,8 +1455,6 @@ static void i82544EI_error(struct wm_softc *sc)
  }
  else 
    printk("%s%d: Ghost interrupt ?\n",ifp->if_name,ifp->if_unit);
-  sc->if_errsts[sc->if_err_ptr1]=0;  
-  if ((++sc->if_err_ptr1)==IF_ERR_BUFSZE) sc->if_err_ptr1=0; /* Till Straumann */
 }

 void i82544EI_printStats()
@@ -1638,7 +1495,7 @@ static void i82544EI_daemon(void *arg)
 				&events);
     if (KILL_EVENT & events)  break;

-     if (events & RX_EVENT)  i82544EI_rx(sc); /* in ISR instead */
+     if (events & RX_EVENT)  i82544EI_rx(sc);

     /* clean up and try sending packets */
     do { 
@@ -1646,7 +1503,6 @@ static void i82544EI_daemon(void *arg)

        while (sc->txq_free>0) {
           if (sc->txq_free>TXQ_HiLmt_OFF) {
-	      m=0;
 	      IF_DEQUEUE(&ifp->if_snd,m);
              if (m==0) break;
              i82544EI_sendpacket(sc, m); 
@@ -1655,6 +1511,7 @@ static void i82544EI_daemon(void *arg)
 	      i82544EI_txq_done(sc);
 	      break;
           }
+           if (events & RX_EVENT)  i82544EI_rx(sc);
        }
         /* we leave this loop
 	  *  - either because there's no free buffer
@@ -1662,7 +1519,7 @@ static void i82544EI_daemon(void *arg)
 	  *  - or there's nothing to send (IF_DEQUEUE
 	  *    returned 0
 	  */
-     } while (m);
+     } while (m && sc->txq_free);

     ifp->if_flags &= ~IFF_OACTIVE;

@@ -1699,70 +1556,3 @@ static void i82544EI_daemon(void *arg)
   */
  rtems_task_delete(RTEMS_SELF);
 }
-
-/*
- * wm_gmii_reset:
- *
- *	Reset the PHY.
- */
-static void wm_gmii_reset(struct wm_softc *sc)
-{
-
-  CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
-  rtems_bsp_delay(20000);
-
-  CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
-  rtems_bsp_delay(20000);
-
-}
-
-/*
- * wm_gmii_mediainit:
- *
- *	Initialize media for use on 1000BASE-T devices.
- */
-static void wm_gmii_mediainit(struct wm_softc *sc)
-{
-  /*  struct ifnet *ifp = &sc->arpcom.ac_if;*/
-
-  /* We have MII. */
-  sc->sc_flags |= WM_F_HAS_MII;
-
-#if 1
-  /* <skf> May 2009 : The value that should be programmed into IPGT is 10 */
-  sc->sc_tipg = TIPG_IPGT(10)+TIPG_IPGR1(8)+TIPG_IPGR2(6); 
-#else
-  sc->sc_tipg = TIPG_1000T_DFLT; /* 0x602008 */
-#endif
-
-  /*
-   * Let the chip set speed/duplex on its own based on
-   * signals from the PHY.
-   * XXXbouyer - I'm not sure this is right for the 80003,
-   * the em driver only sets CTRL_SLU here - but it seems to work.
-   */
-  sc->sc_ctrl |= CTRL_SLU;
-  CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
-
-  wm_gmii_reset(sc);
-
-#if 0
-  /* Initialize our media structures and probe the GMII. */
-  sc->sc_mii.mii_ifp = ifp;
-
-  sc->sc_mii.mii_readreg = wm_gmii_i82544_readreg;
-  sc->sc_mii.mii_writereg = wm_gmii_i82544_writereg;
-  sc->sc_mii.mii_statchg = wm_gmii_statchg;
-
-  ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange,
-	    wm_gmii_mediastatus);
-
-  mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
-	    MII_OFFSET_ANY, MIIF_DOPAUSE);
-  if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
-     ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
-     ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
-  } else
-      ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
-#endif
-}
--- a/c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/if_wmreg.h
+++ b/c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/if_wmreg.h
@@ -5,9 +5,6 @@
 * All rights reserved.
 *
 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
- * Some are added by Shuchen Kate Feng <feng1@bnl.gov>,
- *            NSLS, Brookhaven National Laboratory. All rights reserved.
- *            under the Deaprtment of Energy contract DE-AC02-98CH10886
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
@@ -59,7 +56,7 @@ typedef struct wiseman_addr {
 * The receive descriptor ring must be aligned to a 4K boundary,
 * and there must be an even multiple of 8 descriptors in the ring.
 */
-typedef volatile struct wiseman_rxdesc {
+typedef struct wiseman_rxdesc {
 	wiseman_addr_t	wrx_addr;	/* buffer address */

 	uint16_t	wrx_len;	/* buffer length */
@@ -106,7 +103,7 @@ typedef struct wiseman_tx_fields {
 	uint8_t wtxu_options;		/* options */
 	uint16_t wtxu_vlan;		/* VLAN info */
 } __attribute__((__packed__)) wiseman_txfields_t;
-typedef volatile struct wiseman_txdesc {
+typedef struct wiseman_txdesc {
 	wiseman_addr_t	wtx_addr;	/* buffer address */
 	uint32_t	wtx_cmdlen;	/* command and length */
 	wiseman_txfields_t wtx_fields;	/* fields; see below */
--- a/c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/pcireg.h
+++ b/c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/pcireg.h
@@ -4,7 +4,6 @@
 * Copyright (c) 1995, 1996, 1999, 2000
 *     Christopher G. Demetriou.  All rights reserved.
 * Copyright (c) 1994, 1996 Charles M. Hannum.  All rights reserved.
- * Copyright (C) 2007 Brookhaven National Laboratory, Shuchen Kate Feng
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
@@ -31,7 +30,6 @@
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
-#include <bsp.h>

 /*
 * PCI Class and Revision Register; defines type and revision of device.
@@ -307,7 +305,7 @@
 #define	PCI_MAPREG_MEM64_ADDR_MASK		0xfffffffffffffff0ULL

 #define	PCI_MAPREG_IO_ADDR(mr)						\
-	    ((mr+PCI0_IO_BASE) & PCI_MAPREG_IO_ADDR_MASK)
+	    ((mr) & PCI_MAPREG_IO_ADDR_MASK)
 #define	PCI_MAPREG_IO_SIZE(mr)						\
 	    (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr))
 #define	PCI_MAPREG_IO_ADDR_MASK			0xfffffffc
--- a/c/src/lib/libbsp/powerpc/mvme5500/pci/pci.c
+++ b/c/src/lib/libbsp/powerpc/mvme5500/pci/pci.c
@@ -13,31 +13,29 @@
 *  found in the file LICENSE in this distribution or at
 *  http://www.rtems.com/rtems/license.html.
 *
- *  pci.c,v 1.2 2002/05/14 17:10:16 joel Exp
+ *  Copyright 2004, Brookhaven National Laboratory and
+ *                  Shuchen K. Feng, <feng1@bnl.gov>, 2004
+ *   - modified and added support for MVME5500 board
+ *   - added 2nd PCI support for the mvme5500/GT64260 PCI bridge
+ *   - added bus support for the expansion of PMCSpan, thanks to 
+ *     Peter Dufault (dufault@hda.com) for inputs.
 *
- *  Copyright 2004, 2008 Brookhaven National Laboratory and
- *                  Shuchen K. Feng, <feng1@bnl.gov>
- *   
- *   - to be consistent with the original pci.c written by Eric Valette
- *   - added 2nd PCI support for discovery based PCI bridge (e.g. mvme5500/mvme6100)
- *   - added bus support for the expansion of PMCSpan as per request by Peter
+ * $Id$
 */
 #define PCI_MAIN

 #include <libcpu/io.h>
 #include <rtems/bspIo.h>	    /* printk */

-#include <bsp/irq.h>
 #include <bsp/pci.h>
 #include <bsp/gtreg.h>
 #include <bsp/gtpcireg.h> 
-#include <bsp.h>

 #include <stdio.h>
 #include <string.h>

 #define PCI_DEBUG 0
-#define PCI_PRINT 1
+#define PCI_PRINT 0

 /* allow for overriding these definitions */
 #ifndef PCI_CONFIG_ADDR
@@ -58,31 +56,17 @@
 #define PCI_MULTI_FUNCTION		0x80
 #define HOSTBRIDGET_ERROR               0xf0000000

-#define GT64x60_PCI_CONFIG_ADDR         GT64x60_REG_BASE + PCI_CONFIG_ADDR
-#define GT64x60_PCI_CONFIG_DATA         GT64x60_REG_BASE + PCI_CONFIG_DATA
-
-#define GT64x60_PCI1_CONFIG_ADDR        GT64x60_REG_BASE + PCI1_CONFIG_ADDR
-#define GT64x60_PCI1_CONFIG_DATA        GT64x60_REG_BASE + PCI1_CONFIG_DATA
-
-static int      numPCIDevs=0;
-static DiscoveryChipVersion BSP_sysControllerVersion = 0;
-static BSP_VMEchipTypes BSP_VMEinterface = 0;
-static pci_config BSP_pci[2]={
-  {(volatile unsigned char*) (GT64x60_PCI_CONFIG_ADDR),
-   (volatile unsigned char*) (GT64x60_PCI_CONFIG_DATA),
-   0 /* defined at BSP_pci_configuration */},
-  {(volatile unsigned char*) (GT64x60_PCI1_CONFIG_ADDR),
-   (volatile unsigned char*) (GT64x60_PCI1_CONFIG_DATA),
-   0 /* defined at BSP_pci_configuration */}
-};
+/* define a shortcut */
+#define pci	BSP_pci_configuration

+static int		  numPCIDevs=0;
 extern void pci_interface(void);

 /* Pack RegNum,FuncNum,DevNum,BusNum,and ConfigEnable for
 * PCI Configuration Address Register
 */
 #define pciConfigPack(bus,dev,func,offset)\
-((offset&~3)<<24)|(PCI_DEVFN(dev,func)<<16)|(bus<<8)|0x80
+(((func&7)<<8)|((dev&0x1f )<<11)|(( bus&0xff)<<16)|(offset&0xfc))|0x80000000

 /*
 * Bit encode for PCI_CONFIG_HEADER_TYPE register
@@ -91,36 +75,44 @@ unsigned char ucMaxPCIBus=0;

 /* Please note that PCI0 and PCI1 does not correlate with the busNum 0 and 1.
 */
-static int indirect_pci_read_config_byte(unsigned char bus,unsigned char dev,unsigned char func,
+static int direct_pci_read_config_byte(unsigned char bus,unsigned char dev,unsigned char func,
 unsigned char offset,unsigned char *val)
 {
-  int n=0;
+  volatile unsigned char *config_addr, *config_data;

  if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
     bus-=BSP_MAX_PCI_BUS_ON_PCI0;
-     n=1;
+     config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR;
+     config_data = (volatile unsigned char*) PCI1_CONFIG_DATA;
+  }
+  else {
+     config_addr = pci.pci_config_addr;
+     config_data = pci.pci_config_data;
  }
-
  *val = 0xff;
  if (offset & ~0xff) return PCIBIOS_BAD_REGISTER_NUMBER;
 #if 0
-  printk("addr %x, data %x, pack %x \n", BSP_pci[n].pci_config_addr),
-    BSP_pci[n].config_data,pciConfigPack(bus,dev,func,offset));
+  printk("addr %x, data %x, pack %x \n", config_addr,
+    config_data,pciConfigPack(bus,dev,func,offset));
 #endif
-
-  out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
-  *val = in_8(BSP_pci[n].pci_config_data + (offset&3));
+  outl(pciConfigPack(bus,dev,func,offset),config_addr);
+  *val = inb(config_data + (offset&3));
  return PCIBIOS_SUCCESSFUL;
 }

-static int indirect_pci_read_config_word(unsigned char bus, unsigned char dev,
+static int direct_pci_read_config_word(unsigned char bus, unsigned char dev,
 unsigned char func, unsigned char offset, unsigned short *val)
 {
-  int n=0;
+  volatile unsigned char *config_addr, *config_data;

  if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
     bus-=BSP_MAX_PCI_BUS_ON_PCI0;
-     n=1;
+     config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR;
+     config_data = (volatile unsigned char*) PCI1_CONFIG_DATA;
+  }
+  else {
+     config_addr = (volatile unsigned char*) pci.pci_config_addr;
+     config_data = (volatile unsigned char*) pci.pci_config_data;
  }

  *val = 0xffff; 
@@ -129,101 +121,123 @@ unsigned char func, unsigned char offset, unsigned short *val)
  printk("addr %x, data %x, pack %x \n", config_addr,
    config_data,pciConfigPack(bus,dev,func,offset));
 #endif
-  out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
-  *val = in_le16(BSP_pci[n].pci_config_data + (offset&2));
+  outl(pciConfigPack(bus,dev,func,offset),config_addr);
+  *val = inw(config_data + (offset&2));
  return PCIBIOS_SUCCESSFUL;
 }

-static int indirect_pci_read_config_dword(unsigned char bus, unsigned char dev,
+static int direct_pci_read_config_dword(unsigned char bus, unsigned char dev,
 unsigned char func, unsigned char offset, unsigned int *val) 
 {
-  int n=0;
+  volatile unsigned char *config_addr, *config_data;

  if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
     bus-=BSP_MAX_PCI_BUS_ON_PCI0;
-     n=1;
+     config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR;
+     config_data = (volatile unsigned char*) PCI1_CONFIG_DATA;
+  }
+  else {
+     config_addr = (volatile unsigned char*) pci.pci_config_addr;
+     config_data = (volatile unsigned char*) pci.pci_config_data;
  }

  *val = 0xffffffff; 
  if ((offset&3)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER;
-
-  out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
-  *val = in_le32(BSP_pci[n].pci_config_data);
+#if 0
+  printk("addr %x, data %x, pack %x \n", config_addr,
+    pci.pci_config_data,pciConfigPack(bus,dev,func,offset)); 
+#endif
+  outl(pciConfigPack(bus,dev,func,offset),config_addr);
+  *val = inl(config_data);
  return PCIBIOS_SUCCESSFUL;
 }

-static int indirect_pci_write_config_byte(unsigned char bus, unsigned char dev,unsigned char func, unsigned char offset, unsigned char val) 
+static int direct_pci_write_config_byte(unsigned char bus, unsigned char dev,unsigned char func, unsigned char offset, unsigned char val) 
 {
-  int n=0;
+  volatile unsigned char *config_addr, *config_data;

  if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
     bus-=BSP_MAX_PCI_BUS_ON_PCI0;
-     n=1;
+     config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR;
+     config_data = (volatile unsigned char*) PCI1_CONFIG_DATA;
+  }
+  else {
+     config_addr = pci.pci_config_addr;
+     config_data = pci.pci_config_data;
  }

  if (offset & ~0xff) return PCIBIOS_BAD_REGISTER_NUMBER;
+#if 0
+  printk("addr %x, data %x, pack %x \n", config_addr,
+    config_data,pciConfigPack(bus,dev,func,offset));
+#endif

-  out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
-  out_8(BSP_pci[n].pci_config_data + (offset&3), val);
+  outl(pciConfigPack(bus,dev,func,offset), config_addr);
+  outb(val, config_data + (offset&3));
  return PCIBIOS_SUCCESSFUL;
 }

-static int indirect_pci_write_config_word(unsigned char bus, unsigned char dev,unsigned char func, unsigned char offset, unsigned short val) 
+static int direct_pci_write_config_word(unsigned char bus, unsigned char dev,unsigned char func, unsigned char offset, unsigned short val) 
 {
-  int n=0;
+  volatile unsigned char *config_addr, *config_data;

  if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
     bus-=BSP_MAX_PCI_BUS_ON_PCI0;
-     n=1;
+     config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR;
+     config_data = (volatile unsigned char*) PCI1_CONFIG_DATA;
+  }
+  else {
+     config_addr = (volatile unsigned char*) pci.pci_config_addr;
+     config_data = (volatile unsigned char*) pci.pci_config_data;
  }

  if ((offset&1)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER;
-
-  out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
-  out_le16(BSP_pci[n].pci_config_data + (offset&3), val);
+#if 0
+  printk("addr %x, data %x, pack %x \n", config_addr,
+    config_data,pciConfigPack(bus,dev,func,offset));
+#endif
+  outl(pciConfigPack(bus,dev,func,offset),config_addr);
+  outw(val, config_data + (offset&3));
  return PCIBIOS_SUCCESSFUL;
 }

-static int indirect_pci_write_config_dword(unsigned char bus,unsigned char dev,unsigned char func, unsigned char offset, unsigned int val) 
+static int direct_pci_write_config_dword(unsigned char bus,unsigned char dev,unsigned char func, unsigned char offset, unsigned int val) 
 {
-  int n=0;
+  volatile unsigned char *config_addr, *config_data;

  if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
     bus-=BSP_MAX_PCI_BUS_ON_PCI0;
-     n=1;
+     config_addr = (volatile unsigned char *) PCI1_CONFIG_ADDR;
+     config_data = (volatile unsigned char *) PCI1_CONFIG_DATA;
+  }
+  else {
+     config_addr = (volatile unsigned char*) pci.pci_config_addr;
+     config_data = (volatile unsigned char*) pci.pci_config_data;
  }

  if ((offset&3)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER;
-
-  out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
-  out_le32(BSP_pci[n].pci_config_data, val);
+#if 0
+  printk("addr %x, data %x, pack %x \n", config_addr,
+    config_data,pciConfigPack(bus,dev,func,offset));
+#endif
+  outl(pciConfigPack(bus,dev,func,offset),config_addr);
+  outl(val,config_data);
  return PCIBIOS_SUCCESSFUL;
 }

-const pci_config_access_functions pci_indirect_functions = {
-  	indirect_pci_read_config_byte,
-  	indirect_pci_read_config_word,
-  	indirect_pci_read_config_dword,
-  	indirect_pci_write_config_byte,
-  	indirect_pci_write_config_word,
-  	indirect_pci_write_config_dword
+const pci_config_access_functions pci_direct_functions = {
+  	direct_pci_read_config_byte,
+  	direct_pci_read_config_word,
+  	direct_pci_read_config_dword,
+  	direct_pci_write_config_byte,
+  	direct_pci_write_config_word,
+  	direct_pci_write_config_dword
 };


-pci_config BSP_pci_configuration = {
-           (volatile unsigned char*) (GT64x60_PCI_CONFIG_ADDR),
-	   (volatile unsigned char*) (GT64x60_PCI_CONFIG_DATA),
-	   &pci_indirect_functions};
-
-DiscoveryChipVersion BSP_getDiscoveryChipVersion(void)
-{
-  return(BSP_sysControllerVersion);
-}
-
-BSP_VMEchipTypes BSP_getVMEchipType(void)
-{
-  return(BSP_VMEinterface);
-}
+pci_config BSP_pci_configuration = {(volatile unsigned char*) PCI_CONFIG_ADDR,
+			 (volatile unsigned char*)PCI_CONFIG_DATA,
+				    &pci_direct_functions};

 /*
 * This routine determines the maximum bus number in the system.
@@ -234,12 +248,12 @@ BSP_VMEchipTypes BSP_getVMEchipType(void)
 int pci_initialize(void)
 {
  int deviceFound;
-  unsigned char ucBusNumber, ucSlotNumber, ucFnNumber, ucNumFuncs, data8;
-  uint32_t ulHeader, ulClass, ulDeviceID;
-#if PCI_DEBUG
-  uint32_t pcidata;
-#endif
+  unsigned char ucBusNumber, ucSlotNumber, ucFnNumber, ucNumFuncs;
+  unsigned int ulHeader;
+  unsigned int pcidata, ulClass, ulDeviceID;

+  pci_interface();
+  
  /*
   * Scan PCI0 and PCI1 buses
   */
@@ -265,49 +279,38 @@ int pci_initialize(void)
      if (!deviceFound) deviceFound=1;
      switch(ulDeviceID) { 
        case (PCI_VENDOR_ID_MARVELL+(PCI_DEVICE_ID_MARVELL_GT6426xAB<<16)):
-          pci_read_config_byte(0,0,0,PCI_REVISION_ID, &data8);
-          switch(data8) {
-	  case 0x10:
-	    BSP_sysControllerVersion = GT64260A;
 #if PCI_PRINT
-	    printk("Marvell GT64260A (Discovery I) hostbridge detected at bus%d slot%d\n",
+	  printk("Marvell GT6426xA/B hostbridge detected at bus%d slot%d\n",
                 ucBusNumber,ucSlotNumber);
 #endif
-	    break;
-          case 0x20:
-	    BSP_sysControllerVersion = GT64260B;
-#if PCI_PRINT
-	    printk("Marvell GT64260B (Discovery I) hostbridge detected at bus%d slot%d\n",
-                 ucBusNumber,ucSlotNumber);
-#endif
-	    break;
-	  default:
-	    printk("Undefined revsion of GT64260 chip\n");
-            break;
-          }
 	  break;
+        case (PCI_VENDOR_ID_PLX2+(PCI_DEVICE_ID_PLX2_PCI6154_HB2<<16)):
+#if PCI_PRINT
+          printk("PLX PCI6154 PCI-PCI bridge detected at bus%d slot%d\n",
+                 ucBusNumber,ucSlotNumber);
+#endif
+          break;
        case PCI_VENDOR_ID_TUNDRA:
 #if PCI_PRINT
          printk("TUNDRA PCI-VME bridge detected at bus%d slot%d\n",
                 ucBusNumber,ucSlotNumber);
 #endif
          break;
-      case (PCI_VENDOR_ID_DEC+(PCI_DEVICE_ID_DEC_21150<<16)):
+      case (PCI_VENDOR_ID_INTEL+(PCI_DEVICE_INTEL_82544EI_COPPER<<16)):
 #if PCI_PRINT
+          printk("INTEL 82544EI COPPER network controller detected at bus%d slot%d\n",
+                 ucBusNumber,ucSlotNumber);
+#endif
+          break;
+      case (PCI_VENDOR_ID_DEC+(PCI_DEVICE_ID_DEC_21150<<16)):
+ #if PCI_PRINT
          printk("DEC21150 PCI-PCI bridge detected at bus%d slot%d\n",
                 ucBusNumber,ucSlotNumber);
 #endif
 	  break;
       default : 
-#if PCI_PRINT
          printk("BSP unlisted vendor, Bus%d Slot%d DeviceID 0x%x \n",
             ucBusNumber,ucSlotNumber, ulDeviceID);
-#endif
-	  /* Kate Feng : device not supported by BSP needs to remap the IRQ line on mvme5500/mvme6100 */
-          pci_read_config_byte(ucBusNumber,ucSlotNumber,0,PCI_INTERRUPT_LINE,&data8);
-	  if (data8 < BSP_GPP_IRQ_LOWEST_OFFSET)  pci_write_config_byte(ucBusNumber,
- 	     ucSlotNumber,0,PCI_INTERRUPT_LINE,BSP_GPP_IRQ_LOWEST_OFFSET+data8);
-
          break;
      }

@@ -400,6 +403,34 @@ int pci_initialize(void)
 #endif

      }
+
+      pci_read_config_dword(ucBusNumber,
+			       ucSlotNumber,
+			       0,
+			  PCI_COMMAND,
+                          &pcidata); 
+#if PCI_DEBUG
+      printk("MOTLoad command staus 0x%x, ", pcidata);
+#endif
+      /* Clear the error on the host bridge */
+      if ( (ucBusNumber==0) && (ucSlotNumber==0))
+	pcidata |= PCI_STATUS_CLRERR_MASK;
+      /* Enable bus,I/O and memory master access. */
+      pcidata |= (PCI_COMMAND_MASTER|PCI_COMMAND_IO|PCI_COMMAND_MEMORY);
+      pci_write_config_dword(ucBusNumber,
+ 			       ucSlotNumber,
+			       0,
+			  PCI_COMMAND,
+                          pcidata);
+
+      pci_read_config_dword(ucBusNumber,
+			       ucSlotNumber,
+			       0,
+			  PCI_COMMAND,
+                          &pcidata); 
+#if PCI_DEBUG      
+      printk("Now command/staus 0x%x\n", pcidata);
+#endif
    }
    if (deviceFound) ucMaxPCIBus++;
  } /* for (ucBusNumber=0; ucBusNumber<BSP_MAX_PCI_BUS; ... */
@@ -407,7 +438,6 @@ int pci_initialize(void)
  printk("number of PCI buses: %d, numPCIDevs %d\n", 
 	 pci_bus_count(), numPCIDevs);
 #endif
-  pci_interface(); 
  return(0);
 }

--- a/c/src/lib/libbsp/powerpc/mvme5500/pci/pci_interface.c
+++ b/c/src/lib/libbsp/powerpc/mvme5500/pci/pci_interface.c
@@ -7,14 +7,10 @@
 * found in the file LICENSE in this distribution.
 *
 * 8/17/2006 : S. Kate Feng
- *             uses in_le32()/out_le32(), instead of inl()/outl() for compatibility.
+ *             uses in_le32()/out_le32(), instead of inl()/outl() so that
+ *             it is easier to be ported.
 *
- * 11/2008 : Enable "PCI Read Agressive Prefetch", 
- *           "PCI Read Line Agressive Prefetch", and
- *           "PCI Read Multiple Agressive Prefetch" to improve the
- *           performance of the PCI based applications (e.g. 1GHz NIC).
 */
-
 #include <libcpu/io.h>
 #include <rtems/bspIo.h>	    /* printk */

@@ -23,29 +19,55 @@
 #include <bsp/gtreg.h>
 #include <bsp/gtpcireg.h> 

+#define REG32_READ(reg) in_le32((volatile unsigned int *)(GT64260_REG_BASE+reg))
+#define REG32_WRITE(data, reg) out_le32((volatile unsigned int *)(GT64260_REG_BASE+reg), data)
+
 #define PCI_DEBUG     0

-#if 0
-#define CPU2PCI_ORDER
-#define PCI2CPU_ORDER
-#endif
-
-/* PCI Read Agressive Prefetch Enable (1<<16 ),
- * PCI Read Line Agressive Prefetch Enable( 1<<17),
- * PCI Read Multiple Agressive Prefetch Enable (1<<18).
+/* Please reference the GT64260B datasheet, for the PCI interface, 
+ * Synchronization Barriers and PCI ordering.
+ *
+ * Some PCI devices require Synchronization Barriers or PCI ordering
+ * for synchronization (only one mechanism allowed. See section 11.1.2).
+ * To use the former mechanism(default), one needs to call 
+ * CPU0_PciEnhanceSync() or CPU1_PciEnhanceSync() to perform software
+ * synchronization between the CPU and PCI activities.
+ * 
+ * To use the PCI-ordering, one can call pciToCpuSync() to trigger
+ * the PCI-to-CPU sync barrier after the out_xx(). In this mode,
+ * PCI configuration reads suffer sync barrier latency. Please reference
+ * the datasheet to explore other options.
+ *
+ * Note : If PCI_ORDERING is needed for the PCI0, while disabling the
+ * deadlock  for the PCI0, one should keep the CommDLEn bit enabled
+ * for the deadlock mechanism so that the 10/100 MB ethernet will
+ * function correctly.
+ *
 */
-#ifdef PCI2CPU_ORDER
-#define PCI_ACCCTLBASEL_VALUE          0x01079000
-#else
-#define PCI_ACCCTLBASEL_VALUE          0x01071000 
-#endif
+/*#define PCI_ORDERING*/

+#define EN_SYN_BAR   /* take MOTLoad default for enhanced SYN Barrier mode */
+
+/*#define PCI_DEADLOCK*/
+
+#ifdef PCI_ORDERING
+#define PCI_ACCCTLBASEL_VALUE          0x01009000
+#else
+#define PCI_ACCCTLBASEL_VALUE          0x01001000
+#endif

 #define ConfSBDis     0x10000000  /* 1: disable, 0: enable */
 #define IOSBDis       0x20000000  /* 1: disable, 0: enable */
 #define ConfIOSBDis   0x30000000
 #define CpuPipeline   0x00002000  /* optional, 1:enable, 0:disable */

+#define CPU0_SYNC_TRIGGER   0xD0  /* CPU0 Sync Barrier trigger */
+#define CPU0_SYNC_VIRTUAL   0xC0  /* CPU0 Sync Barrier Virtual */
+
+#define CPU1_SYNC_TRIGGER   0xD8  /* CPU1 Sync Barrier trigger */
+#define CPU1_SYNC_VIRTUAL   0xC8  /* CPU1 Sync Barrier Virtual */
+
+
 /* CPU to PCI ordering register */
 #define DLOCK_ORDER_REG    0x2D0  /* Deadlock and Ordering register */
 #define PCI0OrEn      0x00000001
@@ -69,30 +91,69 @@ void  pciAccessInit(void);
 void pci_interface(void)
 {

-#ifdef CPU2PCI_ORDER
-    /* MOTLOad deafult : 0x07ff8600 */
-    out_le32((volatile unsigned int *)(GT64x60_REG_BASE+CNT_SYNC_REG), 0x07fff600);
+#ifdef PCI_DEADLOCK
+  REG32_WRITE(0x07fff600, CNT_SYNC_REG);
+#endif
+#ifdef PCI_ORDERING
+  /* Let's leave this to be MOTLOad deafult : 0x80070000 
+     REG32_WRITE(0xc0070000, DLOCK_ORDER_REG);*/
+  /* Leave the CNT_SYNC_REG b/c MOTload default had the SyncBarMode set to 1 */
 #endif
-    /* asserts SERR upon various detection */
-    out_le32((volatile unsigned int *)(GT64x60_REG_BASE+0xc28), 0x3fffff);
-    pciAccessInit();
-}

+  /* asserts SERR upon various detection */
+  REG32_WRITE(0x3fffff, 0xc28);
+
+  pciAccessInit();
+}
+/* Use MOTLoad default for Writeback Priority and Buffer Depth 
+ */
 void pciAccessInit(void)
 {
  unsigned int PciLocal, data;

  for (PciLocal=0; PciLocal < 2; PciLocal++) {
-    data = in_le32((volatile unsigned int *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)));
-#if 0
-    printk("PCI%d_ACCESS_CNTL_BASE0_LOW was 0x%x\n",PciLocal,data);
-#endif 
+    /* MOTLoad combines the two banks of SDRAM into
+     * one PCI access control because the top = 0x1ff
+     */
+    data = REG32_READ(GT_SCS0_Low_Decode) & 0xfff; 
    data |= PCI_ACCCTLBASEL_VALUE;
    data &= ~0x300000;
-    out_le32((volatile unsigned int *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)), data);
-#if 0
-      printf("PCI%d_ACCESS_CNTL_BASE0_LOW now 0x%x\n",PciLocal,in_le32((volatile unsigned int *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)))); 
+    REG32_WRITE(data, PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80));
+#if PCI_DEBUG
+    printk("PCI%d_ACCESS_CNTL_BASE0_LOW 0x%x\n",PciLocal,REG32_READ(PCI_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80))); 
 #endif
+
  }
 }

+/* Sync Barrier Trigger. A write to the CPU_SYNC_TRIGGER register triggers
+ * the sync barrier process.  The three bits, define which buffers should
+ * be flushed.
+ * Bit 0 = PCI0 slave write buffer.
+ * Bit 1 = PCI1 slave write buffer.
+ * Bit 2 = SDRAM snoop queue.
+ */
+void CPU0_PciEnhanceSync(unsigned int syncVal)
+{
+  REG32_WRITE(syncVal,CPU0_SYNC_TRIGGER);
+  while (REG32_READ(CPU0_SYNC_VIRTUAL));
+}
+
+void CPU1_PciEnhanceSync(unsigned int syncVal)
+{
+  REG32_WRITE(syncVal,CPU1_SYNC_TRIGGER);
+  while (REG32_READ(CPU1_SYNC_VIRTUAL));
+}
+
+/* Currently, if PCI_ordering is used for synchronization, configuration
+ * reads is programmed to be the PCI slave "synchronization barrier" 
+ * cycles. 
+ */
+void pciToCpuSync(int pci_num)
+{
+  unsigned char data;
+  unsigned char bus=0;
+
+  if (pci_num) bus += BSP_MAX_PCI_BUS_ON_PCI0;
+  pci_read_config_byte(bus,0,0,4, &data);
+}
--- a/c/src/lib/libbsp/powerpc/mvme5500/startup/bspclean.c
+++ b/c/src/lib/libbsp/powerpc/mvme5500/startup/bspclean.c
@@ -1,6 +1,3 @@
-/* Copyright 2003, Shuchen Kate Feng <feng1@bnl.gov>,
- *                    NSLS,Brookhaven National Laboratory
- */
 #include <bsp.h>
 #include <rtems/bspIo.h>
 #include <libcpu/stackTrace.h>
--- a/c/src/lib/libbsp/powerpc/mvme5500/startup/bspstart.c
+++ b/c/src/lib/libbsp/powerpc/mvme5500/startup/bspstart.c
@@ -24,6 +24,8 @@
 *  $Id$
 */

+#warning The interrupt disable mask is now stored in SPRG0, please verify that this is compatible to this BSP (see also bootcard.c).
+
 #include <string.h>
 #include <stdlib.h>
 #include <ctype.h>
@@ -50,12 +52,12 @@
 #undef __RTEMS_APPLICATION__
 #endif

-
-/*#define SHOW_MORE_INIT_SETTINGS
-#define CONF_VPD
+/*
+#define SHOW_MORE_INIT_SETTINGS
 #define SHOW_LCR1_REGISTER
 #define SHOW_LCR2_REGISTER
 #define SHOW_LCR3_REGISTER
+#define CONF_VPD
 */

 /* there is no public Workspace_Free() variant :-( */
@@ -71,7 +73,6 @@ extern Triv121PgTbl BSP_pgtbl_setup(unsigned long);
 extern void BSP_pgtbl_activate(Triv121PgTbl);
 extern int I2Cread_eeprom(unsigned char I2cBusAddr, uint32_t devA2A1A0, uint32_t AddrBytes, unsigned char *pBuff, uint32_t numBytes);
 extern void BSP_vme_config(void);
-extern uint32_t probeMemoryEnd();

 uint32_t bsp_clicks_per_usec;

@@ -266,10 +267,12 @@ void bsp_start( void )
  setdbat(2, PCI0_MEM_BASE, PCI0_MEM_BASE, 0x10000000, IO_PAGE);

  /* Till Straumann: 2004
-   * map the PCI 0, 1 Domain I/O space, GT64260B registers,
-   * Flash Bank 0 and Flash Bank 2.
+   * map the PCI 0, 1 Domain I/O space, GT64260B registers
+   * and the reserved area so that the size is the power of 2.
+   * 
   */
-  setdbat(3,PCI0_IO_BASE, PCI0_IO_BASE, 0x10000000, IO_PAGE);
+  setdbat(3,PCI0_IO_BASE, PCI0_IO_BASE, 0x2000000, IO_PAGE);
+

  /*
   * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
@@ -324,7 +327,29 @@ void bsp_start( void )
  printk("Welcome to %s on MVME5500-0163\n", _RTEMS_version );
  printk("-----------------------------------------\n");

-  BSP_mem_size         =  probeMemoryEnd();
+#ifdef TEST_RETURN_TO_PPCBUG  
+  printk("Hit <Enter> to return to PPCBUG monitor\n");
+  printk("When Finished hit GO. It should print <Back from monitor>\n");
+  debug_getc();
+  _return_to_ppcbug();
+  printk("Back from monitor\n");
+  _return_to_ppcbug();
+#endif /* TEST_RETURN_TO_PPCBUG  */
+
+#ifdef TEST_RAW_EXCEPTION_CODE  
+  printk("Testing exception handling Part 1\n");
+  /*
+   * Cause a software exception
+   */
+  __asm__ __volatile ("sc");
+  /*
+   * Check we can still catch exceptions and returned coorectly.
+   */
+  printk("Testing exception handling Part 2\n");
+  __asm__ __volatile ("sc");
+#endif  
+
+  BSP_mem_size         =  _512M;
  /* TODO: calculate the BSP_bus_frequency using the REF_CLK bit
   *       of System Status  register
   */
@@ -396,19 +421,6 @@ void bsp_start( void )
 #endif
    BSP_pgtbl_activate(pt);
  }
-  /* Read Configuration Vital Product Data (VPD) */
-  if ( I2Cread_eeprom(0xa8, 4,2, &ConfVPD_buff[0], 150))
-     printk("I2Cread_eeprom() error \n");
-  else {
-#ifdef CONF_VPD
-    printk("\n");
-    for (i=0; i<150; i++) {
-      printk("%2x ", ConfVPD_buff[i]);  
-      if ((i % 20)==0 ) printk("\n");
-    }
-    printk("\n");
-#endif
-  }

  /*
   * PCI 1 domain memory space
@@ -432,14 +444,23 @@ void bsp_start( void )
   */
  _BSP_clear_hostbridge_errors(0, 1 /*quiet*/);

+  /* Read Configuration Vital Product Data (VPD) */
+  if ( I2Cread_eeprom(0xa8, 4,2, &ConfVPD_buff[0], 150))
+     printk("I2Cread_eeprom() error \n");
+  else {
+#ifdef CONF_VPD
+    printk("\n");
+    for (i=0; i<150; i++) {
+      printk("%2x ", ConfVPD_buff[i]);  
+      if ((i % 20)==0 ) printk("\n");
+    }
+    printk("\n");
+#endif
+  }
+
 #ifdef SHOW_MORE_INIT_SETTINGS
  printk("MSR %x \n", _read_MSR());
  printk("Exit from bspstart\n");
 #endif

 }
-
-unsigned char ReadConfVPD_buff(int offset)
-{
-  return(ConfVPD_buff[offset]);
-}
--- a/c/src/lib/libbsp/powerpc/mvme5500/startup/reboot.c
+++ b/c/src/lib/libbsp/powerpc/mvme5500/startup/reboot.c
@@ -1,10 +1,3 @@
-/* Copyright 2003, Shuchen Kate Feng <feng1@bnl.gov>,
- *                    NSLS,Brookhaven National Laboratory
- *
- * Ported it from powerpc/shared/console/reboot.c for mvme5500
- *
- */
-
 #include <rtems.h>
 #include <bsp.h>
 #include <rtems/bspIo.h>
@@ -19,5 +12,5 @@ void bsp_reset()

  printk("RTEMS terminated; Rebooting ...\n");
  /* Mvme5500 board reset : 2004 S. Kate Feng <feng1@bnl.gov>  */
-  out_8((volatile unsigned char*) (GT64x60_DEV1_BASE +2), 0x80);
+  out_8((volatile unsigned char*) (GT64260_DEV1_BASE +2), 0x80);
 }
--- a/c/src/lib/libbsp/powerpc/mvme5500/vectors/exceptionhandler.c
+++ b/c/src/lib/libbsp/powerpc/mvme5500/vectors/exceptionhandler.c
@@ -134,8 +134,6 @@ int			quiet=0;
       /* register dump */
       printk("\t Next PC or Address of fault = %x, ", excPtr->EXC_SRR0);
       printk("Mvme5500 Saved MSR = %x\n", excPtr->EXC_SRR1);
-       printk("The Interrupt mask (e.g. MSR_EE) stored in SPRG0= 0x%x\n", 
-	      ppc_interrupt_get_disable_mask());
       printk("\t R0  = %08x", excPtr->GPR0);
       printk(" R1  = %08x", excPtr->GPR1);
       printk(" R2  = %08x", excPtr->GPR2);
--- a/c/src/lib/libbsp/powerpc/psim/ChangeLog
+++ b/c/src/lib/libbsp/powerpc/psim/ChangeLog
@@ -1,7 +1,3 @@
-2009-10-16	Jennifer Averett <jennifer.averett@OARcorp.com>
-
-	* startup/bspstart.c: Add bsp_clicks_per_usec.
-
 2008-12-08	Ralf Corsépius <ralf.corsepius@rtems.org>

 	* bsp_specs: Backport from CVS-HEAD.
--- a/c/src/lib/libbsp/powerpc/psim/startup/bspstart.c
+++ b/c/src/lib/libbsp/powerpc/psim/startup/bspstart.c
@@ -4,7 +4,7 @@
 *  The generic CPU dependent initialization has been performed
 *  before any of these are invoked.
 *
- *  COPYRIGHT (c) 1989-20089
+ *  COPYRIGHT (c) 1989-2008.
 *  On-Line Applications Research Corporation (OAR).
 *
 *  The license and distribution terms for this file may be
@@ -44,11 +44,6 @@ extern int PSIM_INSTRUCTIONS_PER_MICROSECOND;
 */
 unsigned int BSP_bus_frequency;

-/*
- *  Driver configuration parameters
- */
-uint32_t   bsp_clicks_per_usec;
-
 /*
 * Time base divisior (how many tick for 1 second).
 */
@@ -111,7 +106,6 @@ void bsp_start( void )
   *  initialize the device driver parameters
   */
  BSP_bus_frequency        = (unsigned int)&PSIM_INSTRUCTIONS_PER_MICROSECOND;
-  bsp_clicks_per_usec      = BSP_bus_frequency;
  BSP_time_base_divisor    = 1;

  /*
--- a/c/src/lib/libbsp/powerpc/score603e/ChangeLog
+++ b/c/src/lib/libbsp/powerpc/score603e/ChangeLog
@@ -1,24 +1,3 @@
-2009-10-16	Jennifer Averett <jennifer@OARcorp.com>
-
-	* configure.ac: Default to having PSC8 mezzanine so code builds
-	all the time.
-	* startup/bspstart.c: Calibrated clock using an VMEBus controlled
-	discrete pulsed at a 20ms rate.
-
-2009-05-05	Jennifer Averett <jennifer.averett@OARcorp.com>
-
-	* Makefile.am, README, configure.ac, preinstall.am, PCI_bus/PCI.c,
-	PCI_bus/PCI.h, PCI_bus/flash.c, PCI_bus/universe.c, console/85c30.c,
-	console/85c30.h, console/console.c, console/consolebsp.h,
-	console/tbl85c30.c, include/bsp.h, include/coverhd.h, include/gen2.h,
-	include/irq-config.h, include/tm27.h, irq/FPGA.c, irq/irq.h,
-	irq/irq_init.c, start/start.S, startup/Hwr_init.c,
-	startup/bspstart.c, timer/timer.c, tod/tod.c: Updated and tested with
-	the latest powerpc isr source
-	* irq/no_pic.c: New file.
-	* irq/irq.c, startup/genpvec.c, startup/setvec.c, startup/vmeintr.c:
-	Removed.
-
 2008-12-08	Ralf Corsépius <ralf.corsepius@rtems.org>

 	* bsp_specs: Backport from CVS-HEAD.
--- a/c/src/lib/libbsp/powerpc/score603e/Makefile.am
+++ b/c/src/lib/libbsp/powerpc/score603e/Makefile.am
@@ -26,7 +26,7 @@ dist_project_lib_DATA += startup/linkcmds
 startup_SOURCES = ../../shared/bspclean.c ../../shared/bsplibc.c \
    startup/bspstart.c ../../shared/bootcard.c \
    ../../shared/sbrk.c startup/Hwr_init.c \
-    ../../shared/gnatinstallhandler.c \
+    startup/genpvec.c ../../shared/gnatinstallhandler.c \
    ../../powerpc/shared/showbats.c

 pclock_SOURCES = ../../powerpc/shared/clock/p_clock.c
@@ -37,20 +37,39 @@ include_bsp_HEADERS = ../../powerpc/shared/pci/pci.h \
 	PCI_bus/PCI.h \
 	../../powerpc/shared/residual/residual.h \
 	../../powerpc/shared/residual/pnp.h \
-	../../powerpc/shared/console/consoleIo.h 
+	../../powerpc/shared/console/consoleIo.h \
+	../../shared/include/irq-generic.h \
+	include/irq-config.h 

-pci_SOURCES = PCI_bus/flash.c ../../powerpc/shared/pci/pci.c \
+pci_SOURCES = ../../powerpc/shared/pci/pci.c \
    ../../powerpc/shared/pci/pcifinddevice.c  PCI_bus/PCI.c  PCI_bus/universe.c

 include_bsp_HEADERS += irq/irq.h \
 	../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h \
 	../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h \
 	../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h
+irq_SOURCES = include/irq-config.h \
+    irq/FPGA.c irq/irq.c       \
+    ../../shared/src/irq-generic.c       \
+    ../../powerpc/shared/irq/irq_asm.S

-irq_SOURCES =  irq/no_pic.c irq/irq_init.c \
-    irq/FPGA.c 
+include_bsp_HEADERS += ../../powerpc/shared/vectors/vectors.h
+vectors_SOURCES = ../../powerpc/shared/vectors/vectors_init.c \
+    ../../powerpc/shared/vectors/vectors.S

-vectors_SOURCES = 
+include_bsp_HEADERS += ../../shared/vmeUniverse/vmeUniverse.h \
+    ../../shared/include/irq-generic.h \
+    ../../shared/vmeUniverse/vme_am_defs.h \
+    ../../shared/vmeUniverse/VME.h \
+    vme/VMEConfig.h \
+    ../../powerpc/shared/motorola/motorola.h \
+    ../../shared/vmeUniverse/vmeUniverseDMA.h\
+    ../../shared/vmeUniverse/bspVmeDmaList.h\
+    ../../shared/vmeUniverse/VMEDMA.h
+vme_SOURCES = \
+    ../../shared/vmeUniverse/bspVmeDmaList.c \
+    ../../shared/vmeUniverse/vme_am_defs.h \
+	../shared/vme/vmeconfig.c 

 EXTRA_DIST = start/start.S
 start.$(OBJEXT): start/start.S
@@ -64,7 +83,7 @@ project_lib_DATA += rtems_crti.$(OBJEXT)

 noinst_LIBRARIES = libbsp.a
 libbsp_a_SOURCES = $(pclock_SOURCES) $(console_SOURCES) $(irq_SOURCES) \
-    $(pci_SOURCES) $(vectors_SOURCES) $(startup_SOURCES) 
+    $(pci_SOURCES) $(vectors_SOURCES) $(startup_SOURCES) $(vme_SOURCES)

 libbsp_a_LIBADD = \
    ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
@@ -72,7 +91,6 @@ libbsp_a_LIBADD = \
    ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
    ../../../libcpu/@RTEMS_CPU@/mpc6xx/clock.rel \
    ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
-    ../../../libcpu/@RTEMS_CPU@/@exceptions@/irq_bspsupport.rel \
    ../../../libcpu/@RTEMS_CPU@/@exceptions@/raw_exception.rel \
     ../../../libcpu/@RTEMS_CPU@/mpc6xx/mmu.rel \
    ../../../libcpu/@RTEMS_CPU@/mpc6xx/timer.rel
--- a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.c
+++ b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.c
@@ -1,12 +1,8 @@
 /*
 *
- *  COPYRIGHT (c) 1989-2009.
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994, 1997.
 *  On-Line Applications Research Corporation (OAR).
 *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.com/license/LICENSE.
- *
 * $Id$
 */

--- a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.h
+++ b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.h
@@ -3,11 +3,11 @@
 *  This include file contains prototypes for chips attached to the
 *  PCI bus.
 *
- *  COPYRIGHT (c) 1989-2009.
+ *  COPYRIGHT (c) 1989-1997.
 *  On-Line Applications Research Corporation (OAR).
 *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
+ *  The license and distribution terms for this file may in
+ *  the file LICENSE in this distribution or at
 *  http://www.rtems.com/license/LICENSE.
 *
 *  $Id:
--- a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/flash.c
+++ b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/flash.c
@@ -1,12 +1,8 @@
 /*
 *
- *  COPYRIGHT (c) 1989-2009.
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994, 1997.
 *  On-Line Applications Research Corporation (OAR).
 *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.com/license/LICENSE.
- *
 * $Id$
 */

@@ -15,9 +11,7 @@
 #include <stdio.h>

 #include <bsp.h>
-#include <bsp/irq.h>
 #include "PCI.h"
-
 /*PAGE
 *
 *  SCORE603e_FLASH_Disable
--- a/c/src/lib/libbsp/powerpc/score603e/PCI_bus/universe.c
+++ b/c/src/lib/libbsp/powerpc/score603e/PCI_bus/universe.c
@@ -1,10 +1,7 @@
 /*
- *  COPYRIGHT (c) 1989-2009.
- *  On-Line Applications Research Corporation (OAR).
 *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.com/license/LICENSE.
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994, 1997.
+ *  On-Line Applications Research Corporation (OAR).
 *
 * $Id$
 */
--- a/c/src/lib/libbsp/powerpc/score603e/README
+++ b/c/src/lib/libbsp/powerpc/score603e/README
@@ -22,9 +22,6 @@ DMA:                none
 VIDEO:              none
 SCSI:               none
 NETWORKING:         none
-MEZZANINE CARD      optional with HAS_PMC_PSC8
-                    4 Z85C30s
-                    ACE1553

 DRIVER INFORMATION
 ==================
@@ -46,7 +43,9 @@ STOP BITS:          1
 Notes
 =====
 This BSP has been modified to use the latest exception model.
-The modifications were verified.
+However, the modifications were never verified.  This version
+has been partially verified in that Hello.ralf will load and
+run on the board.

 This BSP has been tested using DINK Rom monitor.  There have
 been three rom chips loaded on the boards.  One with the SDS
--- a/c/src/lib/libbsp/powerpc/score603e/console/85c30.c
+++ b/c/src/lib/libbsp/powerpc/score603e/console/85c30.c
@@ -4,14 +4,14 @@
 *
 *  Currently only polled mode is supported.
 *
- *  COPYRIGHT (c) 1989-2009.
+ *  COPYRIGHT (c) 1989-2008.
 *  On-Line Applications Research Corporation (OAR).
 *
 *  The license and distribution terms for this file may be
 *  found in the file LICENSE in this distribution or at
 *  http://www.rtems.com/license/LICENSE.
- * 
- *  $Id$
+ *
+ *  $Id:
 */

 #include <rtems.h>
@@ -129,6 +129,8 @@ void initialize_85c30_port(
  Console_Protocol        *Setup;
  uint16_t                baud_constant;

+printk("initialize_85c30_port start\n");
+
  Setup = Port->Protocol;
  ctrl  = Port->ctrl;

@@ -153,17 +155,20 @@ void initialize_85c30_port(
  /*
   *  Set Write Register 2 to contain the interrupt vector
   */
+printk("initialize_85c30_port 2, %d\n", Port->Chip->vector );
  Write_85c30_register( ctrl, 2, Port->Chip->vector );
 #endif

  /*
   *  Set Write Register 3 to disable the Receiver
   */
+printk("initialize_85c30_port 0x03, 0x00\n");
  Write_85c30_register( ctrl, 0x03, 0x00 );

  /*
   *  Set Write Register 5 to disable the Transmitter
   */
+printk("initialize_85c30_port 5, 0x00\n");
  Write_85c30_register( ctrl, 5, 0x00 );

  /* WR 6 -- unneeded in asynchronous mode */
@@ -173,11 +178,13 @@ void initialize_85c30_port(
  /*
   *  Set Write Register 9 to disable all interrupt sources
   */
+printk("initialize_85c30_port 9, 0x00\n");
  Write_85c30_register( ctrl, 9, 0x00 );

  /*
   *  Set Write Register 10 for simple Asynchronous operation
   */
+printk("initialize_85c30_port 0x0a, 0x00\n");
  Write_85c30_register( ctrl, 0x0a, 0x00 );

  /*
@@ -185,6 +192,7 @@ void initialize_85c30_port(
   * clock as BRG output and the transmit clock
   * as the output source for TRxC pin via register 11
   */
+printk("initialize_85c30_port 0x0b, 0x56\n");
  Write_85c30_register( ctrl, 0x0b, 0x56 );

  value = baud_constant;
@@ -194,12 +202,14 @@ void initialize_85c30_port(
   * If the time constans = 1E, then the desire
   * baud rate will be equilvalent to 9600, via register 12.
   */
+printk("initialize_85c30_port 0x0c, 0x%x\n", value & 0xff);
  Write_85c30_register( ctrl, 0x0c, value & 0xff );

  /*
   * using register 13
   * Setup the upper 8 bits time constants = 0
   */
+printk("initialize_85c30_port 0x0d, 0x%x\n", value>>8);
  Write_85c30_register( ctrl, 0x0d, value>>8 );

  /*
@@ -208,6 +218,7 @@ void initialize_85c30_port(
   * rate generator enable with clock from the
   * SCC's PCLK input via register 14.
   */
+printk("initialize_85c30_port 0x0e, 0x07\n");
  Write_85c30_register( ctrl, 0x0e, 0x07 );

  /*
@@ -223,6 +234,7 @@ void initialize_85c30_port(
  value = 0x01;
  value = value | Char_size_85c30[ Setup->read_char_bits ].read_setup;

+printk("initialize_85c30_port 0x03, 0x%x\n", value);
  Write_85c30_register( ctrl, 0x03, value );

  /*
@@ -237,18 +249,21 @@ void initialize_85c30_port(
   */
  value = 0x8a;
  value = value |  Char_size_85c30[ Setup->write_char_bits ].write_setup;
+printk("initialize_85c30_port 0x05, 0x%x\n", value);
  Write_85c30_register( ctrl, 0x05, value );

  /*
   * Reset Tx UNDERRUN/EOM LATCH and ERROR
   * via register 0
   */
+printk("initialize_85c30_port 0x00, 0xf0\n");
   Write_85c30_register( ctrl, 0x00, 0xf0 );

 #if CONSOLE_USE_INTERRUPTS
  /*
   *  Set Write Register 1 to interrupt on Rx characters or special condition.
   */
+printk("initialize_85c30_port 1, 0x10\n");
  Write_85c30_register( ctrl, 1, 0x10 );
 #endif

@@ -256,11 +271,13 @@ void initialize_85c30_port(
   *  Set Write Register 15 to disable extended functions.
   */

+printk("initialize_85c30_port 15, 0x00\n");
  Write_85c30_register( ctrl, 15, 0x00 );

  /*
   *  Set the Command Register to Reset Ext/STATUS.
   */
+printk("initialize_85c30_port 0x00, 0x10\n");
  Write_85c30_register( ctrl, 0x00, 0x10 );

 #if CONSOLE_USE_INTERRUPTS
@@ -271,12 +288,14 @@ void initialize_85c30_port(
   *    Enables parity as a special condition.
   *    Enables Tx interrupt.
   */
+printk("initialize_85c30_port 1, 0x16\n");
  Write_85c30_register( ctrl, 1, 0x16 );

  /*
   *  Set Write Register 9 to enable all interrupt sources
   *  Changed from 0 to a
   */
+printk("initialize_85c30_port 9, 0x0A\n");
  Write_85c30_register( ctrl, 9, 0x0A );

  /* XXX */
@@ -284,10 +303,12 @@ void initialize_85c30_port(
  /*
   *  Issue reset highest Interrupt Under Service (IUS) command.
   */
+printk("initialize_85c30_port STATUS_REGISTER, 0X38\n");
  Write_85c30_register( Port->ctrl, STATUS_REGISTER, 0x38 );

 #endif

+printk("initialize_85c30_port end of method\n");
 }

 /* PAGE
--- a/c/src/lib/libbsp/powerpc/score603e/console/85c30.h
+++ b/c/src/lib/libbsp/powerpc/score603e/console/85c30.h
@@ -2,14 +2,14 @@
 *
 *  This include file contains z85c30 chip information.
 *
- *  COPYRIGHT (c) 1989-2009.
+ *  COPYRIGHT (c) 1989-1999.
 *  On-Line Applications Research Corporation (OAR).
 *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
+ *  The license and distribution terms for this file may in
+ *  the file LICENSE in this distribution or at
 *  http://www.rtems.com/license/LICENSE.
 *
- *  $Id$
+ *  $Id:
 */

 #ifndef __85c30_H
--- a/c/src/lib/libbsp/powerpc/score603e/console/console.c
+++ b/c/src/lib/libbsp/powerpc/score603e/console/console.c
@@ -5,7 +5,7 @@
 *
 *  Currently only polled mode is supported.
 *
- *  COPYRIGHT (c) 1989-2009.
+ *  COPYRIGHT (c) 1989-1997.
 *  On-Line Applications Research Corporation (OAR).
 *
 *  The license and distribution terms for this file may be
@@ -181,6 +181,8 @@ rtems_device_driver console_initialize(
  rtems_device_minor_number  console;
  int                        port, chip, p0,p1;

+printk("console_initialize start\n");
+
  /*
   * initialize the termio interface.
   */
@@ -205,6 +207,7 @@ rtems_device_driver console_initialize(
 * debugger...)
 */
 #if ( INITIALIZE_COM_PORTS )
+
  /*
   * Force to perform a hardware reset w/o
   * Master interrupt enable via register 9
@@ -236,13 +239,16 @@ rtems_device_driver console_initialize(

  for (port=1; port<NUM_Z85C30_PORTS; port++) {
   chip = port >> 1;
+printk("console_initialize initialize_85c30_port %d\n", port);
    initialize_85c30_port( &Ports_85C30[port] );
  }

 #if CONSOLE_USE_INTERRUPTS
+printk("console_initialize console_initialize_interrupts\n");
  console_initialize_interrupts();
 #endif

+printk("console_initialize end\n");
  return RTEMS_SUCCESSFUL;
 }

@@ -414,13 +420,12 @@ debug_putc_onlcr(const char c)
  if ('\n'==c){
    rtems_interrupt_disable( isrlevel );
    outbyte_polled_85c30( csr, '\r' );
-    asm volatile("isync");
    rtems_interrupt_enable( isrlevel );
+    asm volatile("isync");
  }

  rtems_interrupt_disable( isrlevel );
  outbyte_polled_85c30( csr, c );
-  asm volatile("isync");
  rtems_interrupt_enable( isrlevel );
 }

--- a/c/src/lib/libbsp/powerpc/score603e/console/consolebsp.h
+++ b/c/src/lib/libbsp/powerpc/score603e/console/consolebsp.h
@@ -2,14 +2,14 @@
 *
 *  This include file contains all console driver definations
 *
- *  COPYRIGHT (c) 1989-2009.
+ *  COPYRIGHT (c) 1989-1997.
 *  On-Line Applications Research Corporation (OAR).
 *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
+ *  The license and distribution terms for this file may in
+ *  the file LICENSE in this distribution or at
 *  http://www.rtems.com/license/LICENSE.
 *
- *  $Id$
+ *  $Id:
 */

 #ifndef __CONSOLEBSP_H
--- a/c/src/lib/libbsp/powerpc/score603e/console/tbl85c30.c
+++ b/c/src/lib/libbsp/powerpc/score603e/console/tbl85c30.c
@@ -2,19 +2,18 @@
 *  This file contains the table for the z85c30 port
 *  used by the console driver.
 *
- *  COPYRIGHT (c) 1989-2009.
+ *  COPYRIGHT (c) 1989-1997.
 *  On-Line Applications Research Corporation (OAR).
 *
 *  The license and distribution terms for this file may be
 *  found in the file LICENSE in this distribution or at
 *  http://www.rtems.com/license/LICENSE.
 *
- *  $Id$
+ *  $Id:
 */

 #include "consolebsp.h"
 #include <bsp.h>
-#include <bsp/irq.h>

 #define CONSOLE_DEFAULT_BAUD_RATE            9600
 #define CONSOLE_DEFAULT_BAUD_CONSTANT        Score603e_Z8530_Chip0_Baud(9600)
--- a/c/src/lib/libbsp/powerpc/score603e/include/bsp.h
+++ b/c/src/lib/libbsp/powerpc/score603e/include/bsp.h
@@ -2,11 +2,11 @@
 *
 *  This include file contains all board IO definitions.
 *
- *  COPYRIGHT (c) 1989-2009.
+ *  COPYRIGHT (c) 1989-1997.
 *  On-Line Applications Research Corporation (OAR).
 *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
+ *  The license and distribution terms for this file may in
+ *  the file LICENSE in this distribution or at
 *  http://www.rtems.com/license/LICENSE.
 *
 *  $Id$
@@ -19,8 +19,6 @@
 extern "C" {
 #endif

-#define BSP_ZERO_WORKSPACE_AUTOMATICALLY TRUE
-
 #include <bspopts.h>
 #include <rtems.h>
 #include <rtems/console.h>
@@ -37,6 +35,8 @@ extern "C" {
 #if (HAS_PMC_PSC8)
 #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS (4 + 4)
 #else
+/* XXXXX FIX THIS */
+#error "MUST HAVE PSC8 SET FOR BOEING CODE"
 #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS (4)
 #endif

@@ -55,7 +55,6 @@ extern "C" {
 */

 #include <gen2.h>
-#include <bsp/irq.h>

 /*
 * The following macro calculates the Baud constant. For the Z8530 chip.
@@ -174,10 +173,6 @@ void unmask_irq(
  uint16_t         irq_idx
 );

-void mask_irq(
-  uint16_t         irq_idx
-);
-
 void init_irq_data_register();

 uint16_t         read_and_clear_PMC_irq(
--- a/c/src/lib/libbsp/powerpc/score603e/include/coverhd.h
+++ b/c/src/lib/libbsp/powerpc/score603e/include/coverhd.h
@@ -15,11 +15,11 @@
 *         calling overhead including passing of arguments.
 *
 *
- *  COPYRIGHT (c) 1989-2009.
+ *  COPYRIGHT (c) 1989-1997.
 *  On-Line Applications Research Corporation (OAR).
 *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
+ *  The license and distribution terms for this file may in
+ *  the file LICENSE in this distribution or at
 *  http://www.rtems.com/license/LICENSE.
 *
 *  $Id$
--- a/c/src/lib/libbsp/powerpc/score603e/include/gen2.h
+++ b/c/src/lib/libbsp/powerpc/score603e/include/gen2.h
@@ -2,14 +2,14 @@
 *
 *  This include file contains all Generation 2 board addreses
 *
- *  COPYRIGHT (c) 1989-2009.
+ *  COPYRIGHT (c) 1989-1997.
 *  On-Line Applications Research Corporation (OAR).
 *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
+ *  The license and distribution terms for this file may in
+ *  the file LICENSE in this distribution or at
 *  http://www.rtems.com/license/LICENSE.
 *
- *  $Id$
+ *  $Id:
 */

 #ifndef __SCORE_GENERATION_2_h
@@ -178,6 +178,67 @@ extern "C" {
 *  Score603e Interupt Definations.
 */

+/*
+ * First Score Unique IRQ
+ */
+#define Score_IRQ_First ( PPC_IRQ_LAST +  1 )
+
+/*
+ * The Following Are part of a Score603e FPGA.
+ */
+#define SCORE603E_IRQ00   ( Score_IRQ_First +  0 )
+#define SCORE603E_IRQ01   ( Score_IRQ_First +  1 )
+#define SCORE603E_IRQ02   ( Score_IRQ_First +  2 )
+#define SCORE603E_IRQ03   ( Score_IRQ_First +  3 )
+#define SCORE603E_IRQ04   ( Score_IRQ_First +  4 )
+#define SCORE603E_IRQ05   ( Score_IRQ_First +  5 )
+#define SCORE603E_IRQ06   ( Score_IRQ_First +  6 )
+#define SCORE603E_IRQ07   ( Score_IRQ_First +  7 )
+#define SCORE603E_IRQ08   ( Score_IRQ_First +  8 )
+#define SCORE603E_IRQ09   ( Score_IRQ_First +  9 )
+#define SCORE603E_IRQ10   ( Score_IRQ_First + 10 )
+#define SCORE603E_IRQ11   ( Score_IRQ_First + 11 )
+#define SCORE603E_IRQ12   ( Score_IRQ_First + 12 )
+#define SCORE603E_IRQ13   ( Score_IRQ_First + 13 )
+#define SCORE603E_IRQ14   ( Score_IRQ_First + 14 )
+#define SCORE603E_IRQ15   ( Score_IRQ_First + 15 )
+
+#define SCORE603E_TIMER1_IRQ           SCORE603E_IRQ00
+#define SCORE603E_TIMER2_IRQ           SCORE603E_IRQ01
+#define SCORE603E_TIMER3_IRQ           SCORE603E_IRQ02
+#define SCORE603E_85C30_1_IRQ          SCORE603E_IRQ03
+#define SCORE603E_85C30_0_IRQ          SCORE603E_IRQ04
+#define SCORE603E_RTC_IRQ              SCORE603E_IRQ05
+#define SCORE603E_PCI_IRQ_0            SCORE603E_IRQ06
+#define SCORE603E_PCI_IRQ_1            SCORE603E_IRQ07
+#define SCORE603E_PCI_IRQ_2            SCORE603E_IRQ08
+#define SCORE603E_PCI_IRQ_3            SCORE603E_IRQ09
+#define SCORE603E_UNIVERSE_IRQ         SCORE603E_IRQ10
+#define SCORE603E_1553_IRQ             SCORE603E_IRQ11
+#define SCORE603E_MAIL_BOX_IRQ_0       SCORE603E_IRQ12
+#define SCORE603E_MAIL_BOX_IRQ_1       SCORE603E_IRQ13
+#define SCORE603E_MAIL_BOX_IRQ_2       SCORE603E_IRQ14
+#define SCORE603E_MAIL_BOX_IRQ_3       SCORE603E_IRQ15
+
+/*
+ * The Score FPGA maps all interrupts comming from the PMC card to
+ * the FPGA interrupt SCORE603E_PCI_IRQ_0 the PMC status word must be
+ * read to indicate which interrupt was chained to the FPGA.
+ */
+#define SCORE603E_IRQ16   ( Score_IRQ_First + 16 )
+#define SCORE603E_IRQ17   ( Score_IRQ_First + 17 )
+#define SCORE603E_IRQ18   ( Score_IRQ_First + 18 )
+#define SCORE603E_IRQ19   ( Score_IRQ_First + 19 )
+
+/*
+ * IRQ'a read from the PMC card
+ */
+#define SCORE603E_85C30_4_IRQ          SCORE603E_IRQ16    /* SCC 422-1 */
+#define SCORE603E_85C30_2_IRQ          SCORE603E_IRQ17    /* SCC 232-1 */
+#define SCORE603E_85C30_5_IRQ          SCORE603E_IRQ18    /* SCC 422-2 */
+#define SCORE603E_85C30_3_IRQ          SCORE603E_IRQ19    /* SCC 232-2 */
+
+#define MAX_BOARD_IRQS                 SCORE603E_IRQ19

 /*
 *  BSP_TIMER_AVG_OVERHEAD and BSP_TIMER_LEAST_VALID for the shared timer
@@ -203,9 +264,8 @@ extern "C" {
 #define BSP_Convert_decrementer( _value ) \
  (int) (((_value) * 4000) / 6667)

+#endif
+
 #ifdef __cplusplus
 }
 #endif
-
-#endif
-
--- a/c/src/lib/libbsp/powerpc/score603e/include/irq-config.h
+++ b/c/src/lib/libbsp/powerpc/score603e/include/irq-config.h
@@ -4,8 +4,6 @@
 * @ingroup bsp_interrupt
 *
 * @brief BSP interrupt support configuration.
- *
- * $Id$
 */

 /*
--- a/c/src/lib/libbsp/powerpc/score603e/include/tm27.h
+++ b/c/src/lib/libbsp/powerpc/score603e/include/tm27.h
@@ -1,9 +1,6 @@
 /*
 *  tm27.h
 *
- *  COPYRIGHT (c) 1989-2009.
- *  On-Line Applications Research Corporation (OAR).
- *
 *  The license and distribution terms for this file may be
 *  found in the file LICENSE in this distribution or at
 *  http://www.rtems.com/license/LICENSE.
--- a/c/src/lib/libbsp/powerpc/score603e/irq/FPGA.c
+++ b/c/src/lib/libbsp/powerpc/score603e/irq/FPGA.c
@@ -1,17 +1,16 @@
 /*  FPGA.c -- Bridge for second and subsequent generations
 *
- *  COPYRIGHT (c) 1989-2009.
+ *  COPYRIGHT (c) 1989-2001.
 *  On-Line Applications Research Corporation (OAR).
 *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
+ *  The license and distribution terms for this file may in
+ *  the file LICENSE in this distribution or at
 *  http://www.rtems.com/license/LICENSE.
 *
 *  $Id$
 */

 #include <bsp.h>
-#include <bsp/irq.h>
 #include <string.h>
 #include <fcntl.h>
 #include <assert.h>
@@ -28,13 +27,14 @@ void initialize_PCI_bridge (void)
  /* Note: Accept DINKs setup of the PCI Bridge and don't 
   *       change anything.
   */
+  printk("initialize_PCI_bridge: \n");
 }

 void set_irq_mask(
  uint16_t         value
 )
 {
-  volatile uint16_t   *loc;
+  uint16_t          *loc;

  loc = (uint16_t*)SCORE603E_FPGA_MASK_DATA;

@@ -43,8 +43,8 @@ void set_irq_mask(

 uint16_t         get_irq_mask(voi)
 {
-  volatile uint16_t  *loc;
-  uint16_t            value;
+  uint16_t          *loc;
+  uint16_t          value;

  loc =  (uint16_t*)SCORE603E_FPGA_MASK_DATA;

@@ -53,32 +53,6 @@ uint16_t         get_irq_mask(voi)
  return value;
 }

-void mask_irq(
-  uint16_t         irq_idx
-)
-{
-  uint16_t         value;
-  uint32_t         mask_idx = irq_idx;
-
-  value = get_irq_mask();
-
-#if (HAS_PMC_PSC8)
-  switch (irq_idx + Score_IRQ_First ) {
-    case SCORE603E_85C30_4_IRQ:
-    case SCORE603E_85C30_2_IRQ:
-    case SCORE603E_85C30_5_IRQ:
-    case SCORE603E_85C30_3_IRQ:
-      mask_idx = SCORE603E_PCI_IRQ_0 - Score_IRQ_First;
-      break;
-    default:
-      break;
-  }
-#endif
-
-  value |= (0x1 << mask_idx);
-  set_irq_mask( value );
-}
-
 void unmask_irq(
  uint16_t         irq_idx
 )
@@ -126,7 +100,7 @@ uint16_t         read_and_clear_PMC_irq(
  uint16_t            irq
 )
 {
-  uint16_t   status_word = irq;
+  uint16_t            status_word = irq;

  status_word = (*BSP_PMC_STATUS_ADDRESS);

@@ -165,15 +139,14 @@ uint16_t         read_and_clear_irq(void)
 {
  uint16_t            irq;

-
  irq = (*SCORE603E_FPGA_VECT_DATA);
-  Processor_Synchronize();
+
  if ((irq & 0xffff0) != 0x10) {
-    printk( "read_and_clear_irq:: ERROR==>no irq data 0x%x\n", irq);
+    printk( "ERROR:: no irq data\n");
    return (irq | 0x80);
  }

  irq &=0xf;
-  irq += Score_IRQ_First;
+
  return irq;
 }
--- a/c/src/lib/libbsp/powerpc/score603e/irq/irq.c
+++ b/c/src/lib/libbsp/powerpc/score603e/irq/irq.c
@@ -0,0 +1,513 @@
+/*
+ *
+ *  This file contains the implementation of the function described in irq.h
+ *
+ *  Copyright (C) 1998, 1999 valette@crf.canon.fr
+ *
+ *  The license and distribution terms for this file may be
+ *  found in found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ */
+
+#include <stdlib.h>
+
+#include <bsp.h>
+#include <bsp/irq.h>
+#include <bsp/VME.h>
+#include <rtems/score/apiext.h>  /* for post ISR signal processing */
+#include <libcpu/raw_exception.h>
+#include <libcpu/io.h>
+#include <bsp/vectors.h>
+#include <stdlib.h>
+#include <rtems/bspIo.h> /* for printk */
+
+/*
+ * default handler connected on each irq after bsp initialization
+ */
+static rtems_irq_connect_data	default_rtems_entry;
+
+/*
+ * location used to store initial tables used for interrupt
+ * management.
+ */
+static rtems_irq_global_settings* 	internal_config;
+static rtems_irq_connect_data*		rtems_hdl_tbl;
+
+/*
+ * Check if IRQ is an ISA IRQ
+ */
+static inline int is_isa_irq(const rtems_irq_number irqLine)
+{
+  return (((int) irqLine <= BSP_ISA_IRQ_MAX_OFFSET) &
+	  ((int) irqLine >= BSP_ISA_IRQ_LOWEST_OFFSET)
+	 );
+}
+
+/*
+ * Check if IRQ is an pci IRQ
+ */
+static inline int is_pci_irq(const rtems_irq_number irqLine)
+{
+  return (((int) irqLine <= BSP_PCI_IRQ_MAX_OFFSET) &
+	  ((int) irqLine >= BSP_PCI_IRQ_LOWEST_OFFSET)
+	 );
+}
+
+/*
+ * Check if IRQ is a Processor IRQ
+ */
+static inline int is_processor_irq(const rtems_irq_number irqLine)
+{
+  return (((int) irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) &
+	  ((int) irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
+	 );
+}
+
+/*
+ * ------------------------ RTEMS Irq helper functions ----------------
+ */
+
+/*
+ * This function check that the value given for the irq line
+ * is valid.
+ */
+
+static int isValidInterrupt(int irq)
+{
+  if ( (irq < BSP_LOWEST_OFFSET) || (irq > BSP_MAX_OFFSET))
+    return 0;
+  return 1;
+}
+
+/*
+ * ------------------------ RTEMS Shared Irq Handler Mngt Routines ----------------
+ */
+int BSP_install_rtems_shared_irq_handler  (const rtems_irq_connect_data* irq)
+{
+    rtems_interrupt_level   level;
+    rtems_irq_connect_data* vchain;
+
+printk(" BSP_install_rtems_shared_irq_handler %d\n", irq->name );
+
+    if (!isValidInterrupt(irq->name)) {
+      printk("Invalid interrupt vector %d\n",irq->name);
+      return 0;
+    }
+
+    rtems_interrupt_disable(level);
+
+    if ( (int)rtems_hdl_tbl[irq->name].next_handler  == -1 ) {
+      rtems_interrupt_enable(level);
+      printk("IRQ vector %d already connected to an unshared handler\n",irq->name);
+      return 0;
+    }
+
+     vchain = (rtems_irq_connect_data*)malloc(sizeof(rtems_irq_connect_data));
+
+    /* save off topmost handler */
+    vchain[0]= rtems_hdl_tbl[irq->name];
+
+    /*
+     * store the data provided by user
+     */
+    rtems_hdl_tbl[irq->name] = *irq;
+
+    /* link chain to new topmost handler */
+    rtems_hdl_tbl[irq->name].next_handler = (void *)vchain;
+
+    /*
+     * XXX FIX ME
+     */
+    if (is_pci_irq(irq->name)) {
+    }
+
+    if (is_processor_irq(irq->name)) {
+      /*
+       * Enable exception at processor level
+       */
+    }
+    /*
+     * Enable interrupt on device
+     */
+	if (irq->on)
+    	irq->on(irq);
+
+    rtems_interrupt_enable(level);
+
+    return 1;
+}
+
+/*
+ * This function disables a given XXX interrupt
+ */
+rtems_status_code bsp_interrupt_vector_disable( rtems_vector_number irqLine)
+{
+  /* XXX FIX ME!!!! */
+
+  printk("bsp_interrupt_vector_disable: 0x%x\n", irqLine );
+  return RTEMS_SUCCESSFUL;
+}
+
+rtems_status_code bsp_interrupt_vector_enable( rtems_vector_number irqLine)
+{
+  /* XXX FIX ME!!!! */
+  printk("bsp_interrupt_vector_enable: 0x%x\n", irqLine );
+
+  return RTEMS_SUCCESSFUL;
+}
+
+
+
+/*
+ * ------------------------ RTEMS Single Irq Handler Mngt Routines ----------------
+ */
+
+int BSP_install_rtems_irq_handler  (const rtems_irq_connect_data* irq)
+{
+    rtems_interrupt_level       level;
+
+printk(" BSP_install_rtems_irq_handler %d\n", irq->name );
+
+    if (!isValidInterrupt(irq->name)) {
+      printk("Invalid interrupt vector %d\n",irq->name);
+      return 0;
+    }
+    /*
+     * Check if default handler is actually connected. If not issue an error.
+     * You must first get the current handler via i386_get_current_idt_entry
+     * and then disconnect it using i386_delete_idt_entry.
+     * RATIONALE : to always have the same transition by forcing the user
+     * to get the previous handler before accepting to disconnect.
+     */
+    rtems_interrupt_disable(level);
+    if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) {
+      rtems_interrupt_enable(level);
+      printk("IRQ vector %d already connected\n",irq->name);
+      return 0;
+    }
+
+    /*
+     * store the data provided by user
+     */
+    rtems_hdl_tbl[irq->name] = *irq;
+    rtems_hdl_tbl[irq->name].next_handler = (void *)-1;
+
+    /* XXX -FIX ME !! */
+    if (is_pci_irq(irq->name)) {
+      /*
+       * Enable interrupt 
+       */
+      printk("is_pci_irq = TRUE - FIX THIS!\n");
+    }
+
+    if (is_processor_irq(irq->name)) {
+      /*
+       * Enable exception at processor level
+       */
+      printk("is_processor_irq = TRUE : Fix This\n");
+    }
+
+    /*
+     * Enable interrupt on device
+     */
+    if (irq->on) {
+        printk("Call 0x%x\n", irq->on );
+    	irq->on(irq);
+    }
+
+    rtems_interrupt_enable(level);
+
+    return 1;
+}
+
+int BSP_get_current_rtems_irq_handler	(rtems_irq_connect_data* irq)
+{
+    rtems_interrupt_level       level;
+
+printk(" BSP_get_current_rtems_irq_handler %d\n", irq->name );
+    if (!isValidInterrupt(irq->name)) {
+      return 0;
+    }
+    rtems_interrupt_disable(level);
+      *irq = rtems_hdl_tbl[irq->name];
+    rtems_interrupt_enable(level);
+    return 1;
+}
+
+int BSP_remove_rtems_irq_handler  (const rtems_irq_connect_data* irq)
+{
+    rtems_irq_connect_data *pchain= NULL, *vchain = NULL;
+    rtems_interrupt_level       level;
+
+printk(" BSP_remove_rtems_irq_handler %d\n", irq->name );
+    if (!isValidInterrupt(irq->name)) {
+      return 0;
+    }
+    /*
+     * Check if default handler is actually connected. If not issue an error.
+     * You must first get the current handler via i386_get_current_idt_entry
+     * and then disconnect it using i386_delete_idt_entry.
+     * RATIONALE : to always have the same transition by forcing the user
+     * to get the previous handler before accepting to disconnect.
+     */
+    rtems_interrupt_disable(level);
+    if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) {
+      rtems_interrupt_enable(level);
+      return 0;
+    }
+
+    if( (int)rtems_hdl_tbl[irq->name].next_handler != -1 )
+    {
+       int found = 0;
+
+       for( (pchain= NULL, vchain = &rtems_hdl_tbl[irq->name]);
+            (vchain->hdl != default_rtems_entry.hdl);
+            (pchain= vchain, vchain = (rtems_irq_connect_data*)vchain->next_handler) )
+       {
+          if( vchain->hdl == irq->hdl )
+          {
+             found= -1; break;
+          }
+       }
+
+       if( !found )
+       {
+          rtems_interrupt_enable(level);
+          return 0;
+       }
+    }
+    else
+    {
+       if (rtems_hdl_tbl[irq->name].hdl != irq->hdl)
+       {
+          rtems_interrupt_enable(level);
+         return 0;
+       }
+    }
+
+    /* XXX - FIX ME !! */
+    if (is_pci_irq(irq->name)) {
+      /*
+       * disable interrupt 
+       */
+    }
+    if (is_processor_irq(irq->name)) {
+      /*
+       * disable exception at processor level
+       */
+    }
+
+    /*
+     * Disable interrupt on device
+     */
+	if (irq->off)
+    	irq->off(irq);
+
+    /*
+     * restore the default irq value
+     */
+    if( !vchain )
+    {
+       /* single handler vector... */
+       rtems_hdl_tbl[irq->name] = default_rtems_entry;
+    }
+    else
+    {
+       if( pchain )
+       {
+          /* non-first handler being removed */
+          pchain->next_handler = vchain->next_handler;
+       }
+       else
+       {
+          /* first handler isn't malloc'ed, so just overwrite it.  Since
+          the contents of vchain are being struct copied, vchain itself
+          goes away */
+          rtems_hdl_tbl[irq->name]= *vchain;
+       }
+       free(vchain);
+    }
+
+    rtems_interrupt_enable(level);
+
+    return 1;
+}
+
+/*
+ * RTEMS Global Interrupt Handler Management Routines
+ */
+
+int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
+{
+    int                    i;
+    rtems_interrupt_level  level;
+
+    /*
+     * Store various code accelerators
+     */
+    internal_config 		= config;
+    default_rtems_entry 	= config->defaultEntry;
+    rtems_hdl_tbl 		= config->irqHdlTbl;
+
+printk(" BSP_rtems_irq_mngt_set\n");
+
+    rtems_interrupt_disable(level);
+    /*
+     * set up internal tables used by rtems interrupt prologue
+     */
+
+    /*
+     *  XXX - FIX ME !!!  
+     */
+    for (i=BSP_PCI_IRQ_LOWEST_OFFSET; i < BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER ; i++) {
+      if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
+         {
+            rtems_irq_connect_data* vchain;
+            for( vchain = &rtems_hdl_tbl[i];
+                 ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl);
+                 vchain = (rtems_irq_connect_data*)vchain->next_handler )
+            {
+			  if (vchain->on)
+               	vchain->on(vchain);
+            }
+         }
+
+      }
+      else {
+         /* if (rtems_hdl_tbl[i].off) rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); */
+         {
+            rtems_irq_connect_data* vchain;
+            for( vchain = &rtems_hdl_tbl[i];
+                 ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl);
+                 vchain = (rtems_irq_connect_data*)vchain->next_handler )
+            {
+			  if (vchain->off)
+               vchain->off(vchain);
+            }
+         }
+      }
+    }
+    /*
+     * finish with Processor exceptions handled like IRQ
+     */
+    for (i=BSP_PROCESSOR_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET+BSP_PROCESSOR_IRQ_NUMBER; i++){
+      if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
+         {
+            rtems_irq_connect_data* vchain;
+            for( vchain = &rtems_hdl_tbl[i];
+                 ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl);
+                 vchain = (rtems_irq_connect_data*)vchain->next_handler )
+            {
+			  if (vchain->on)
+               vchain->on(vchain);
+            }
+         }
+
+      }
+      else {
+         {
+            rtems_irq_connect_data* vchain;
+            for( vchain = &rtems_hdl_tbl[i];
+                 ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl);
+                 vchain = (rtems_irq_connect_data*)vchain->next_handler )
+            {
+			  if (vchain->off)
+               vchain->off(vchain);
+            }
+         }
+
+      }
+    }
+    rtems_interrupt_enable(level);
+    return 1;
+}
+
+int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config)
+{
+    *config = internal_config;
+    return 0;
+}
+
+unsigned BSP_spuriousIntr = 0;
+
+/*
+ * High level IRQ handler called from shared_raw_irq_code_entry
+ */
+int C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
+{
+  register unsigned int irq;
+  register unsigned msr;
+  register unsigned new_msr;
+
+  if (excNum == ASM_DEC_VECTOR) {
+    _CPU_MSR_GET(msr);
+    new_msr = msr | MSR_EE;
+    _CPU_MSR_SET(new_msr);
+
+    rtems_hdl_tbl[BSP_DECREMENTER].hdl(rtems_hdl_tbl[BSP_DECREMENTER].handle);
+
+    _CPU_MSR_SET(msr);
+    return 0;
+
+  }
+
+  irq = read_and_clear_irq();
+  _CPU_MSR_GET(msr);
+  new_msr = msr | MSR_EE;
+  _CPU_MSR_SET(new_msr);
+
+  /* rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle); */
+  {
+     rtems_irq_connect_data* vchain;
+     for( vchain = &rtems_hdl_tbl[irq];
+          ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl);
+          vchain = (rtems_irq_connect_data*)vchain->next_handler )
+     {
+        vchain->hdl(vchain->handle);
+     }
+  }
+
+  _CPU_MSR_SET(msr);
+
+  return 0;
+}
+
+void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx)
+{
+printk(" _ThreadProcessSignalsFromIrq \n");
+  /*
+   * Process pending signals that have not already been
+   * processed by _Thread_Displatch. This happens quite
+   * unfrequently : the ISR must have posted an action
+   * to the current running thread.
+   */
+  if ( _Thread_Do_post_task_switch_extension ||
+       _Thread_Executing->do_post_task_switch_extension ) {
+    _Thread_Executing->do_post_task_switch_extension = false;
+    _API_extensions_Run_postswitch();
+  }
+  /*
+   * I plan to process other thread related events here.
+   * This will include DEBUG session requested from keyboard...
+   */
+}
+
+rtems_status_code bsp_interrupt_facility_initialize( void)
+{
+  /* Install exception handler */
+  if (ppc_exc_set_handler( ASM_EXT_VECTOR, C_dispatch_irq_handler)) {
+    return RTEMS_IO_ERROR;
+  }
+  if (ppc_exc_set_handler( ASM_DEC_VECTOR, C_dispatch_irq_handler)) {
+    return RTEMS_IO_ERROR;
+  }
+  if (ppc_exc_set_handler( ASM_E300_SYSMGMT_VECTOR, C_dispatch_irq_handler)) {
+    return RTEMS_IO_ERROR;
+  }
+
+  return RTEMS_SUCCESSFUL;
+}
+
+
--- a/c/src/lib/libbsp/powerpc/score603e/irq/irq.h
+++ b/c/src/lib/libbsp/powerpc/score603e/irq/irq.h
@@ -3,17 +3,16 @@
 *  This include file describe the data structure and the functions implemented
 *  by RTEMS to write interrupt handlers.
 *
+ *  Copyright (C) 1999 valette@crf.canon.fr
+ *
 *  This code is heavilly inspired by the public specification of STREAM V2
 *  that can be found at :
 *
- *  <http://www.chorus.com/Documentation/index.html> by following
+ *      <http://www.chorus.com/Documentation/index.html> by following
 *  the STREAM API Specification Document link.
 *
- *  COPYRIGHT (c) 1989-2009.
- *  On-Line Applications Research Corporation (OAR).
- *
 *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
+ *  found in found in the file LICENSE in this distribution or at
 *  http://www.rtems.com/license/LICENSE.
 *
 *  $Id$
@@ -25,13 +24,46 @@
 #define BSP_SHARED_HANDLER_SUPPORT      1
 #include <rtems/irq.h>

+/*
+ * 8259 edge/level control definitions at VIA
+ */
+#define ISA8259_M_ELCR 		0x4d0
+#define ISA8259_S_ELCR 		0x4d1
+
+#define ELCRS_INT15_LVL         0x80
+#define ELCRS_INT14_LVL         0x40
+#define ELCRS_INT13_LVL         0x20
+#define ELCRS_INT12_LVL         0x10
+#define ELCRS_INT11_LVL         0x08
+#define ELCRS_INT10_LVL         0x04
+#define ELCRS_INT9_LVL          0x02
+#define ELCRS_INT8_LVL          0x01
+#define ELCRM_INT7_LVL          0x80
+#define ELCRM_INT6_LVL          0x40
+#define ELCRM_INT5_LVL          0x20
+#define ELCRM_INT4_LVL          0x10
+#define ELCRM_INT3_LVL          0x8
+#define ELCRM_INT2_LVL          0x4
+#define ELCRM_INT1_LVL          0x2
+#define ELCRM_INT0_LVL          0x1
+
+    /* PIC's command and mask registers */
+#define PIC_MASTER_COMMAND_IO_PORT		0x20	/* Master PIC command register */
+#define PIC_SLAVE_COMMAND_IO_PORT		0xa0	/* Slave PIC command register */
+#define PIC_MASTER_IMR_IO_PORT			0x21	/* Master PIC Interrupt Mask Register */
+#define PIC_SLAVE_IMR_IO_PORT		 	0xa1	/* Slave PIC Interrupt Mask Register */
+
+    /* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */
+#define PIC_EOSI	0x60	/* End of Specific Interrupt (EOSI) */
+#define	SLAVE_PIC_EOSI  0x62	/* End of Specific Interrupt (EOSI) for cascade */
+#define PIC_EOI		0x20	/* Generic End of Interrupt (EOI) */
+
 #ifndef ASM

 #ifdef __cplusplus
 extern "C" {
 #endif

-
 /*
 * rtems_irq_number Definitions
 */
@@ -42,30 +74,20 @@ extern "C" {
 #define BSP_ISA_IRQ_NUMBER		(16)
 #define BSP_ISA_IRQ_LOWEST_OFFSET	(0)
 #define BSP_ISA_IRQ_MAX_OFFSET		(BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1)
-
 /*
 * PCI IRQ handlers related definitions
+ * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE
 */
 #define BSP_PCI_IRQ_NUMBER		(16)
 #define BSP_PCI_IRQ_LOWEST_OFFSET	(BSP_ISA_IRQ_NUMBER)
 #define BSP_PCI_IRQ_MAX_OFFSET		(BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1)
-
-/*
- * PMC IRQ
- */
-#define BSP_PMC_IRQ_NUMBER              (4)
-#define BSP_PMC_IRQ_LOWEST_OFFSET	(BSP_PCI_IRQ_MAX_OFFSET + 1)
-#define BSP_PMC_IRQ_MAX_OFFSET		(BSP_PMC_IRQ_LOWEST_OFFSET + BSP_PMC_IRQ_NUMBER - 1)
-
-
 /*
 * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt
 * handler might be connected
 */
 #define BSP_PROCESSOR_IRQ_NUMBER	(1)
-#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PMC_IRQ_MAX_OFFSET + 1)
+#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1)
 #define BSP_PROCESSOR_IRQ_MAX_OFFSET	(BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
-
 /* Misc vectors for OPENPIC irqs (IPI, timers)
 */
 #define BSP_MISC_IRQ_NUMBER		(8)
@@ -77,76 +99,96 @@ extern "C" {
 #define BSP_IRQ_NUMBER			(BSP_MISC_IRQ_MAX_OFFSET + 1)
 #define BSP_LOWEST_OFFSET		(BSP_ISA_IRQ_LOWEST_OFFSET)
 #define BSP_MAX_OFFSET			(BSP_MISC_IRQ_MAX_OFFSET)
+/*
+ * Some ISA IRQ symbolic name definition
+ */
+#define BSP_ISA_PERIODIC_TIMER      	(0)
+#define BSP_ISA_KEYBOARD          	(1)
+#define BSP_ISA_UART_COM2_IRQ		(3)
+#define BSP_ISA_UART_COM1_IRQ		(4)
+#define BSP_ISA_RT_TIMER1	      	(8)
+#define BSP_ISA_RT_TIMER3		(10)
+/*
+ * Some PCI IRQ symbolic name definition
+ */
+#define BSP_PCI_IRQ0			(BSP_PCI_IRQ_LOWEST_OFFSET)
+#define BSP_PCI_ISA_BRIDGE_IRQ		(BSP_PCI_IRQ0)
+
+#if defined(mvme2100)
+#define BSP_DEC21143_IRQ                (BSP_PCI_IRQ_LOWEST_OFFSET + 1)
+#define BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ   (BSP_PCI_IRQ_LOWEST_OFFSET + 2)
+#define BSP_PCMIP_TYPE1_SLOT1_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 3)
+#define BSP_PCMIP_TYPE2_SLOT0_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 4)
+#define BSP_PCMIP_TYPE2_SLOT1_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 5)
+#define BSP_PCI_INTA_UNIVERSE_LINT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 7)
+#define BSP_PCI_INTB_UNIVERSE_LINT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 8)
+#define BSP_PCI_INTC_UNIVERSE_LINT2_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 9)
+#define BSP_PCI_INTD_UNIVERSE_LINT3_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 10)
+#define BSP_UART_COM1_IRQ               (BSP_PCI_IRQ_LOWEST_OFFSET + 13)
+#define BSP_FRONT_PANEL_ABORT_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 14)
+#define BSP_RTC_IRQ                     (BSP_PCI_IRQ_LOWEST_OFFSET + 15)
+#else
+#define BSP_UART_COM1_IRQ		BSP_ISA_UART_COM1_IRQ
+#define BSP_UART_COM2_IRQ		BSP_ISA_UART_COM2_IRQ
+#endif

 /*
 * Some Processor execption handled as RTEMS IRQ symbolic name definition
 */
 #define BSP_DECREMENTER			(BSP_PROCESSOR_IRQ_LOWEST_OFFSET)

-/*
- * First Score Unique IRQ
- */
-#define Score_IRQ_First ( BSP_PCI_IRQ_LOWEST_OFFSET )

 /*
- * The Following Are part of a Score603e FPGA.
+ * Type definition for RTEMS managed interrupts
 */
-#define SCORE603E_IRQ00   ( Score_IRQ_First +  0 )
-#define SCORE603E_IRQ01   ( Score_IRQ_First +  1 )
-#define SCORE603E_IRQ02   ( Score_IRQ_First +  2 )
-#define SCORE603E_IRQ03   ( Score_IRQ_First +  3 )
-#define SCORE603E_IRQ04   ( Score_IRQ_First +  4 )
-#define SCORE603E_IRQ05   ( Score_IRQ_First +  5 )
-#define SCORE603E_IRQ06   ( Score_IRQ_First +  6 )
-#define SCORE603E_IRQ07   ( Score_IRQ_First +  7 )
-#define SCORE603E_IRQ08   ( Score_IRQ_First +  8 )
-#define SCORE603E_IRQ09   ( Score_IRQ_First +  9 )
-#define SCORE603E_IRQ10   ( Score_IRQ_First + 10 )
-#define SCORE603E_IRQ11   ( Score_IRQ_First + 11 )
-#define SCORE603E_IRQ12   ( Score_IRQ_First + 12 )
-#define SCORE603E_IRQ13   ( Score_IRQ_First + 13 )
-#define SCORE603E_IRQ14   ( Score_IRQ_First + 14 )
-#define SCORE603E_IRQ15   ( Score_IRQ_First + 15 )
+typedef unsigned short rtems_i8259_masks;

-#define SCORE603E_TIMER1_IRQ           SCORE603E_IRQ00
-#define SCORE603E_TIMER2_IRQ           SCORE603E_IRQ01
-#define SCORE603E_TIMER3_IRQ           SCORE603E_IRQ02
-#define SCORE603E_85C30_1_IRQ          SCORE603E_IRQ03
-#define SCORE603E_85C30_0_IRQ          SCORE603E_IRQ04
-#define SCORE603E_RTC_IRQ              SCORE603E_IRQ05
-#define SCORE603E_PCI_IRQ_0            SCORE603E_IRQ06
-#define SCORE603E_PCI_IRQ_1            SCORE603E_IRQ07
-#define SCORE603E_PCI_IRQ_2            SCORE603E_IRQ08
-#define SCORE603E_PCI_IRQ_3            SCORE603E_IRQ09
-#define SCORE603E_UNIVERSE_IRQ         SCORE603E_IRQ10
-#define SCORE603E_1553_IRQ             SCORE603E_IRQ11
-#define SCORE603E_MAIL_BOX_IRQ_0       SCORE603E_IRQ12
-#define SCORE603E_MAIL_BOX_IRQ_1       SCORE603E_IRQ13
-#define SCORE603E_MAIL_BOX_IRQ_2       SCORE603E_IRQ14
-#define SCORE603E_MAIL_BOX_IRQ_3       SCORE603E_IRQ15
+extern  volatile rtems_i8259_masks i8259s_cache;
+
+/*-------------------------------------------------------------------------+
+| Function Prototypes.
+--------------------------------------------------------------------------*/
+/*
+ * ------------------------ Intel 8259 (or emulation) Mngt Routines -------
+ */
+void BSP_i8259s_init(void);

 /*
- * The Score FPGA maps all interrupts comming from the PMC card to
- * the FPGA interrupt SCORE603E_PCI_IRQ_0 the PMC status word must be
- * read to indicate which interrupt was chained to the FPGA.
+ * function to disable a particular irq at 8259 level. After calling
+ * this function, even if the device asserts the interrupt line it will
+ * not be propagated further to the processor
+ *
+ * RETURNS: 1/0 if the interrupt was enabled/disabled originally or
+ *          a value < 0 on error.
 */
-#define SCORE603E_IRQ16   ( Score_IRQ_First + 16 )
-#define SCORE603E_IRQ17   ( Score_IRQ_First + 17 )
-#define SCORE603E_IRQ18   ( Score_IRQ_First + 18 )
-#define SCORE603E_IRQ19   ( Score_IRQ_First + 19 )
-
+int BSP_irq_disable_at_i8259s        (const rtems_irq_number irqLine);
 /*
- * IRQ'a read from the PMC card
+ * function to enable a particular irq at 8259 level. After calling
+ * this function, if the device asserts the interrupt line it will
+ * be propagated further to the processor
 */
-#define SCORE603E_85C30_4_IRQ          SCORE603E_IRQ16    /* SCC 422-1 */
-#define SCORE603E_85C30_2_IRQ          SCORE603E_IRQ17    /* SCC 232-1 */
-#define SCORE603E_85C30_5_IRQ          SCORE603E_IRQ18    /* SCC 422-2 */
-#define SCORE603E_85C30_3_IRQ          SCORE603E_IRQ19    /* SCC 232-2 */
+int BSP_irq_enable_at_i8259s		(const rtems_irq_number irqLine);
+/*
+ * function to acknowledge a particular irq at 8259 level. After calling
+ * this function, if a device asserts an enabled interrupt line it will
+ * be propagated further to the processor. Mainly usefull for people
+ * writing raw handlers as this is automagically done for RTEMS managed
+ * handlers.
+ */
+int BSP_irq_ack_at_i8259s           	(const rtems_irq_number irqLine);
+/*
+ * function to check if a particular irq is enabled at 8259 level. After calling
+ */
+int BSP_irq_enabled_at_i8259s        	(const rtems_irq_number irqLine);

-#define MAX_BOARD_IRQS                 SCORE603E_IRQ19
+extern void BSP_rtems_irq_mng_init(unsigned cpuId);
+extern void BSP_i8259s_init(void);
+
+/* Stuff in irq_supp.h should eventually go into <rtems/irq.h> */
+/* #include <bsp/irq_supp.h> */

 #ifdef __cplusplus
-}
+};
 #endif

 #endif
--- a/c/src/lib/libbsp/powerpc/score603e/irq/irq_init.c
+++ b/c/src/lib/libbsp/powerpc/score603e/irq/irq_init.c
@@ -22,14 +22,16 @@
 #include <libcpu/spr.h>
 #include <bsp/pci.h>
 #include <bsp/residual.h>
+#include <bsp/openpic.h>
 #include <bsp/irq.h>
 #include <bsp.h>
 #include <libcpu/raw_exception.h>
+#include <bsp/motorola.h>
 #include <rtems/bspIo.h>

 #define SHOW_ISA_PCI_BRIDGE_SETTINGS 1
 #define SCAN_PCI_PRINT               1
-#define TRACE_IRQ_INIT               0 
+#define TRACE_IRQ_INIT               1

 typedef struct {
  unsigned char bus;	/* few chance the PCI/ISA bridge is not on first bus but ... */
@@ -38,26 +40,223 @@ typedef struct {
 } pci_isa_bridge_device;

 pci_isa_bridge_device* via_82c586 = 0;
+static pci_isa_bridge_device bridge;

 extern unsigned int external_exception_vector_prolog_code_size[];
 extern void external_exception_vector_prolog_code(void);
 extern unsigned int decrementer_exception_vector_prolog_code_size[];
 extern void decrementer_exception_vector_prolog_code(void);

-static void IRQ_Default_rtems_irq_hdl( rtems_irq_hdl_param ptr ) {}
-static void IRQ_Default_rtems_irq_enable (const struct __rtems_irq_connect_data__ *ptr){}
-static void IRQ_Default_rtems_irq_disable(const struct __rtems_irq_connect_data__ *ptr){}
-static int  IRQ_Default_rtems_irq_is_enabled(const struct __rtems_irq_connect_data__ *ptr){ return 1; }
+/*
+ * default on/off function
+ */
+static void nop_func(void){}
+/*
+ * default isOn function
+ */
+static int not_connected(void) {return 0;}
+/*
+ * default possible isOn function
+ */
+static int connected(void) {return 1;}

 static rtems_irq_connect_data     	rtemsIrq[BSP_IRQ_NUMBER];
 static rtems_irq_global_settings     	initial_config;
-
 static rtems_irq_connect_data     	defaultIrq = {
-/*name,	 hdl				handle	on				off				isOn */
-  0,	 IRQ_Default_rtems_irq_hdl,	NULL,	IRQ_Default_rtems_irq_enable,	IRQ_Default_rtems_irq_disable,	IRQ_Default_rtems_irq_is_enabled
+  /* vectorIdex,	 hdl		, handle	, on		, off		, isOn */
+  0, 			 nop_func	, NULL		, nop_func	, nop_func	, not_connected
+};
+static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={
+  /*
+   * actual priorities for interrupt :
+   *	0   means that only current interrupt is masked
+   *	255 means all other interrupts are masked
+   */
+  /*
+   * ISA interrupts.
+   * The second entry has a priority of 255 because
+   * it is the slave pic entry and should always remain
+   * unmasked.
+   */
+  0,0,
+  255,
+  0, 0, 0, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
+  /*
+   * PCI Interrupts
+   */
+  8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, /* for raven prio 0 means unactive... */
+  /*
+   * Processor exceptions handled as interrupts
+   */
+  0
 };

-static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER];
+#if defined(mvme2100)
+static unsigned char mvme2100_openpic_initpolarities[16] = {
+    0,  /* Not used - should be disabled */
+    0,	/* DEC21143 Controller */
+    0,  /* PMC/PC-MIP Type I Slot 0 */
+    0,  /* PC-MIP Type I Slot 1 */
+    0,  /* PC-MIP Type II Slot 0 */
+    0,  /* PC-MIP Type II Slot 1 */
+    0,  /* Not used - should be disabled */
+    0,  /* PCI Expansion Interrupt A/Universe II (LINT0) */
+    0,  /* PCI Expansion Interrupt B/Universe II (LINT1) */
+    0,  /* PCI Expansion Interrupt C/Universe II (LINT2) */
+    0,  /* PCI Expansion Interrupt D/Universe II (LINT3) */
+    0,  /* Not used - should be disabled */
+    0,  /* Not used - should be disabled */
+    1,  /* 16550 UART */
+    0,  /* Front panel Abort Switch */
+    0,  /* RTC IRQ */
+};
+
+static unsigned char mvme2100_openpic_initsenses[] = {
+    0,  /* Not used - should be disabled */
+    1,	/* DEC21143 Controller */
+    1,  /* PMC/PC-MIP Type I Slot 0 */
+    1,  /* PC-MIP Type I Slot 1 */
+    1,  /* PC-MIP Type II Slot 0 */
+    1,  /* PC-MIP Type II Slot 1 */
+    0,  /* Not used - should be disabled */
+    1,  /* PCI Expansion Interrupt A/Universe II (LINT0) */
+    1,  /* PCI Expansion Interrupt B/Universe II (LINT1) */
+    1,  /* PCI Expansion Interrupt C/Universe II (LINT2) */
+    1,  /* PCI Expansion Interrupt D/Universe II (LINT3) */
+    0,  /* Not used - should be disabled */
+    0,  /* Not used - should be disabled */
+    1,  /* 16550 UART */
+    0,  /* Front panel Abort Switch */
+    1,  /* RTC IRQ */
+};
+#else
+static unsigned char mcp750_openpic_initpolarities[16] = {
+    1,  /* 8259 cascade */
+    0,	/* all the rest of them */
+};
+
+static unsigned char mcp750_openpic_initsenses[] = {
+    1,	/* MCP750_INT_PCB(8259) */
+    0,	/* MCP750_INT_FALCON_ECC_ERR */
+    1,	/* MCP750_INT_PCI_ETHERNET */
+    1,	/* MCP750_INT_PCI_PMC */
+    1,	/* MCP750_INT_PCI_WATCHDOG_TIMER1 */
+    1,	/* MCP750_INT_PCI_PRST_SIGNAL */
+    1,	/* MCP750_INT_PCI_FALL_SIGNAL */
+    1,	/* MCP750_INT_PCI_DEG_SIGNAL */
+    1,	/* MCP750_INT_PCI_BUS1_INTA */
+    1,	/* MCP750_INT_PCI_BUS1_INTB */
+    1,	/* MCP750_INT_PCI_BUS1_INTC */
+    1,	/* MCP750_INT_PCI_BUS1_INTD */
+    1,	/* MCP750_INT_PCI_BUS2_INTA */
+    1,	/* MCP750_INT_PCI_BUS2_INTB */
+    1,	/* MCP750_INT_PCI_BUS2_INTC */
+    1,	/* MCP750_INT_PCI_BUS2_INTD */
+};
+#endif
+
+void VIA_isa_bridge_interrupts_setup(void)
+{
+  pci_isa_bridge_device pci_dev;
+  unsigned int temp;
+  unsigned char tmp;
+  unsigned char maxBus;
+  unsigned found = 0;
+
+  maxBus = pci_bus_count();
+  pci_dev.function 	= 0; /* Assumes the bidge is the first function */
+
+  for (pci_dev.bus = 0; pci_dev.bus < maxBus; pci_dev.bus++) {
+#ifdef SCAN_PCI_PRINT
+    printk("isa_bridge_interrupts_setup: Scanning bus %d\n", pci_dev.bus);
+#endif
+    for (pci_dev.device = 0; pci_dev.device < PCI_MAX_DEVICES; pci_dev.device++) {
+#ifdef SCAN_PCI_PRINT
+      printk("isa_bridge_interrupts_setup: Scanning device %d\n", pci_dev.device);
+#endif
+      pci_read_config_dword(pci_dev.bus, pci_dev.device,  pci_dev.function,
+			       PCI_VENDOR_ID, &temp);
+#ifdef SCAN_PCI_PRINT
+      printk("Vendor/device = %x\n", temp);
+#endif
+      if ((temp == (((unsigned short) PCI_VENDOR_ID_VIA) | (PCI_DEVICE_ID_VIA_82C586_0 << 16)))
+	 ) {
+	bridge = pci_dev;
+	via_82c586 = &bridge;
+#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
+	/*
+	 * Should print : bus = 0, device = 11, function = 0 on a MCP750.
+	 */
+	printk("Via PCI/ISA bridge found at bus = %d, device = %d, function = %d\n",
+	       via_82c586->bus,
+	       via_82c586->device,
+	       via_82c586->function);
+#endif
+	found = 1;
+	goto loop_exit;
+
+      }
+    }
+  }
+loop_exit:
+  if (!found) BSP_panic("VIA_82C586 PCI/ISA bridge not found!n");
+
+  tmp = inb(0x810);
+  if  ( !(tmp & 0x2)) {
+#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
+    printk("This is a second generation MCP750 board\n");
+    printk("We must reprogram the PCI/ISA bridge...\n");
+#endif
+    pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
+			 0x47,  &tmp);
+#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
+    printk(" PCI ISA bridge control2 = %x\n", (unsigned) tmp);
+#endif
+    /*
+     * Enable 4D0/4D1 ISA interrupt level/edge config registers
+     */
+    tmp |= 0x20;
+    pci_write_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
+			  0x47, tmp);
+    /*
+     * Now program the ISA interrupt edge/level
+     */
+    tmp = ELCRS_INT9_LVL | ELCRS_INT10_LVL | ELCRS_INT11_LVL;
+    outb(tmp, ISA8259_S_ELCR);
+    tmp = ELCRM_INT5_LVL;
+    outb(tmp, ISA8259_M_ELCR);;
+    /*
+     * Set the Interrupt inputs to non-inverting level interrupt
+     */
+    pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
+			    0x54, &tmp);
+#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
+    printk(" PCI ISA bridge PCI/IRQ Edge/Level Select = %x\n", (unsigned) tmp);
+#endif
+    tmp = 0;
+    pci_write_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
+			  0x54, tmp);
+  }
+  else {
+#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
+    printk("This is a first generation MCP750 board\n");
+    printk("We just show the actual value used by PCI/ISA bridge\n");
+#endif
+    pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
+			 0x47,  &tmp);
+#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
+    printk(" PCI ISA bridge control2 = %x\n", (unsigned) tmp);
+#endif
+    /*
+     * Show the Interrupt inputs inverting/non-inverting level status
+     */
+    pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
+			 0x54, &tmp);
+#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
+    printk(" PCI ISA bridge PCI/IRQ Edge/Level Select = %x\n", (unsigned) tmp);
+#endif
+  }
+}

  /*
   * This code assumes the exceptions management setup has already
@@ -67,11 +266,54 @@ static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER];
   */
 void BSP_rtems_irq_mng_init(unsigned cpuId)
 {
+#if !defined(mvme2100)
+  int known_cpi_isa_bridge = 0;
+#endif
+  rtems_raw_except_connect_data vectorDesc;
  int i;

  /*
   * First initialize the Interrupt management hardware
   */
+#if defined(mvme2100)
+#ifdef TRACE_IRQ_INIT 
+  printk("Going to initialize EPIC interrupt controller (openpic compliant)\n");
+#endif
+  openpic_init(1, mvme2100_openpic_initpolarities, mvme2100_openpic_initsenses);
+#else
+#ifdef TRACE_IRQ_INIT 
+  printk("Going to initialize raven interrupt controller (openpic compliant)\n");
+#endif
+  openpic_init(1, mcp750_openpic_initpolarities, mcp750_openpic_initsenses);
+#endif       
+
+#if !defined(mvme2100)
+#ifdef TRACE_IRQ_INIT  
+  printk("Going to initialize the PCI/ISA bridge IRQ related setting (VIA 82C586)\n");
+#endif
+  if ( currentBoard == MESQUITE ) {
+    VIA_isa_bridge_interrupts_setup();
+    known_cpi_isa_bridge = 1;
+  }
+  if ( currentBoard == MVME_2300 ) {
+    /* nothing to do for W83C553 bridge */
+    known_cpi_isa_bridge = 1;
+  }
+  if ( currentBoard == MTX_WO_PP || currentBoard == MTX_W_PP ) {
+     /* W83C554, don't to anything at the moment.  gregm 11/6/2002 */
+     known_cpi_isa_bridge = 1;
+  }
+
+  if (!known_cpi_isa_bridge) {
+    printk("Please add code for PCI/ISA bridge init to libbsp/powerpc/shared/irq/irq_init.c\n");
+    printk("If your card works correctly please add a test and set known_cpi_isa_bridge to true\n");
+    printk("currentBoard = %i\n", currentBoard);
+  }
+#ifdef TRACE_IRQ_INIT
+  printk("Going to initialize the ISA PC legacy IRQ management hardware\n");
+#endif
+  BSP_i8259s_init();
+#endif

  /*
   * Initialize RTEMS management interrupt table
@@ -80,14 +322,9 @@ void BSP_rtems_irq_mng_init(unsigned cpuId)
     * re-init the rtemsIrq table
     */
    for (i = 0; i < BSP_IRQ_NUMBER; i++) {
-      irqPrioTable[i]  = 8;
      rtemsIrq[i]      = defaultIrq;
      rtemsIrq[i].name = i;
-#ifdef BSP_SHARED_HANDLER_SUPPORT
-      rtemsIrq[i].next_handler = NULL;
-#endif
    }
-
    /*
     * Init initial Interrupt management config
     */
@@ -104,6 +341,27 @@ void BSP_rtems_irq_mng_init(unsigned cpuId)
      BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n");
    }

+  /*
+   * We must connect the raw irq handler for the two
+   * expected interrupt sources : decrementer and external interrupts.
+   */
+    vectorDesc.exceptIndex 	=	ASM_DEC_VECTOR;
+    vectorDesc.hdl.vector	=	ASM_DEC_VECTOR;
+    vectorDesc.hdl.raw_hdl	=	decrementer_exception_vector_prolog_code;
+    vectorDesc.hdl.raw_hdl_size	=	(unsigned) decrementer_exception_vector_prolog_code_size;
+    vectorDesc.on		=	nop_func;
+    vectorDesc.off		=	nop_func;
+    vectorDesc.isOn		=	connected;
+    if (!ppc_set_exception (&vectorDesc)) {
+      BSP_panic("Unable to initialize RTEMS decrementer raw exception\n");
+    }
+    vectorDesc.exceptIndex	=	ASM_EXT_VECTOR;
+    vectorDesc.hdl.vector	=	ASM_EXT_VECTOR;
+    vectorDesc.hdl.raw_hdl	=	external_exception_vector_prolog_code;
+    vectorDesc.hdl.raw_hdl_size	=	(unsigned) external_exception_vector_prolog_code_size;
+    if (!ppc_set_exception (&vectorDesc)) {
+      BSP_panic("Unable to initialize RTEMS external raw exception\n");
+    }
 #ifdef TRACE_IRQ_INIT
    printk("RTEMS IRQ management is now operational\n");
 #endif
--- a/c/src/lib/libbsp/powerpc/score603e/irq/no_pic.c
+++ b/c/src/lib/libbsp/powerpc/score603e/irq/no_pic.c
@@ -1,84 +0,0 @@
-/*
- *
- *  This file contains the implementation of the function described in irq.h
- *
- *  COPYRIGHT (c) 1989-2009.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.com/license/LICENSE.
- *
- *  $Id$
- */
-
-#include <rtems.h>
-#include <bsp.h>
-#include <bsp/irq.h>
-#include <bsp/irq_supp.h>
-#include <libcpu/raw_exception.h>
-
-static rtems_irq_connect_data *rtems_hdl_tbl;
-static rtems_irq_connect_data  dflt_entry;
-
-/*
- * High level IRQ handler called from shared_raw_irq_code_entry
- */
-int C_dispatch_irq_handler(
-  struct _BSP_Exception_frame *frame,
-  unsigned int excNum
-)
-{
-  register unsigned int irq;
-#if (HAS_PMC_PSC8)
-  uint16_t              check_irq;
-  uint16_t              status_word;
-#endif
-
-  if (excNum == ASM_DEC_VECTOR) {
-    bsp_irq_dispatch_list(rtems_hdl_tbl, BSP_DECREMENTER, dflt_entry.hdl);
-    return 0;
-  }
-
-  irq = read_and_clear_irq();
-
-#if (HAS_PMC_PSC8)
-   if (irq ==  SCORE603E_PCI_IRQ_0) {
-     status_word = read_and_clear_PMC_irq( irq );
-     for (check_irq=SCORE603E_IRQ16; check_irq<=SCORE603E_IRQ19; check_irq++) {
-       if ( Is_PMC_IRQ( check_irq, status_word )) {
-         bsp_irq_dispatch_list_base(rtems_hdl_tbl, check_irq, dflt_entry.hdl);
-       }
-     }
-   } else
-#endif
-   {
-    bsp_irq_dispatch_list_base(rtems_hdl_tbl, irq, dflt_entry.hdl);
-   }
-
-  return 0;
-}
-
-void
-BSP_enable_irq_at_pic(const rtems_irq_number irq)
-{
-  uint16_t  vec_idx  = irq - Score_IRQ_First;
-  unmask_irq( vec_idx );
-}
-
-int
-BSP_disable_irq_at_pic(const rtems_irq_number irq)
-{
-  uint16_t  vec_idx  = irq - Score_IRQ_First;
-  unmask_irq( vec_idx );
-  return 0;
-}
-
-int
-BSP_setup_the_pic(rtems_irq_global_settings *config)
-{
-  dflt_entry    = config->defaultEntry;
-  rtems_hdl_tbl = config->irqHdlTbl;
-  init_irq_data_register();
-  return 1;
-}
--- a/c/src/lib/libbsp/powerpc/score603e/preinstall.am
+++ b/c/src/lib/libbsp/powerpc/score603e/preinstall.am
@@ -85,6 +85,14 @@ $(PROJECT_INCLUDE)/bsp/consoleIo.h: ../../powerpc/shared/console/consoleIo.h $(P
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/consoleIo.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/consoleIo.h

+$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
+
+$(PROJECT_INCLUDE)/bsp/irq-config.h: include/irq-config.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-config.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-config.h
+
 $(PROJECT_INCLUDE)/bsp/irq.h: irq/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
@@ -101,6 +109,46 @@ $(PROJECT_INCLUDE)/bsp/irq_supp.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bsps
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq_supp.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq_supp.h

+$(PROJECT_INCLUDE)/bsp/vectors.h: ../../powerpc/shared/vectors/vectors.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vectors.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vectors.h
+
+$(PROJECT_INCLUDE)/bsp/vmeUniverse.h: ../../shared/vmeUniverse/vmeUniverse.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vmeUniverse.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vmeUniverse.h
+
+$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
+
+$(PROJECT_INCLUDE)/bsp/vme_am_defs.h: ../../shared/vmeUniverse/vme_am_defs.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vme_am_defs.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vme_am_defs.h
+
+$(PROJECT_INCLUDE)/bsp/VME.h: ../../shared/vmeUniverse/VME.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/VME.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/VME.h
+
+$(PROJECT_INCLUDE)/bsp/VMEConfig.h: vme/VMEConfig.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/VMEConfig.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/VMEConfig.h
+
+$(PROJECT_INCLUDE)/bsp/motorola.h: ../../powerpc/shared/motorola/motorola.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/motorola.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/motorola.h
+
+$(PROJECT_INCLUDE)/bsp/vmeUniverseDMA.h: ../../shared/vmeUniverse/vmeUniverseDMA.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vmeUniverseDMA.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vmeUniverseDMA.h
+
+$(PROJECT_INCLUDE)/bsp/bspVmeDmaList.h: ../../shared/vmeUniverse/bspVmeDmaList.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bspVmeDmaList.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bspVmeDmaList.h
+
+$(PROJECT_INCLUDE)/bsp/VMEDMA.h: ../../shared/vmeUniverse/VMEDMA.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/VMEDMA.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/VMEDMA.h
+
 $(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT)
 TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT)
--- a/c/src/lib/libbsp/powerpc/score603e/start/start.S
+++ b/c/src/lib/libbsp/powerpc/score603e/start/start.S
@@ -14,7 +14,7 @@
 * the new terms are clearly indicated on the first page of each file where
 * they apply.
 *
- * $Id$
+ *  $Id$
 */

 #include "ppc-asm.h"
--- a/c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c
+++ b/c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c
@@ -1,11 +1,4 @@
 /*  Hwr_init.c
- *
- *  COPYRIGHT (c) 1989-2009.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.com/license/LICENSE.
 *
 *  $Id$
 */
@@ -89,6 +82,8 @@ void init_PCI(void)
 {
  /* DINK Monitor setsup and uses all 4 BAT registers.  */
  /* The fourth BAT register can be modified to access this area */
+
+  printk("init_PCI:\n");
 }

 #define PPC_Get_HID0( _value ) \
--- a/c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c
+++ b/c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c
@@ -5,14 +5,14 @@
 *  The generic CPU dependent initialization has been performed
 *  before any of these are invoked.
 *
- *  COPYRIGHT (c) 1989-2009.
+ *  COPYRIGHT (c) 1989-2007.
 *  On-Line Applications Research Corporation (OAR).
 *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
+ *  The license and distribution terms for this file may in
+ *  the file LICENSE in this distribution or at
 *  http://www.rtems.com/license/LICENSE.
 *
- *  $Id$
+ *  $Id:
 */

 #include <string.h>
@@ -22,8 +22,7 @@
 #include <rtems/libcsupport.h>
 #include <rtems/bspIo.h>
 #include <libcpu/cpuIdent.h>
-
-#define DEBUG 0
+#define DEBUG 1

 /*
 * Where the heap starts; is used by bsp_pretasking_hook;
@@ -33,19 +32,17 @@ unsigned int BSP_heap_start;
 /*
 * PCI Bus Frequency
 */
-unsigned int BSP_bus_frequency;  
+unsigned int BSP_bus_frequency;  /* XXX - Set this based upon the Score board */

 /*
 * processor clock frequency
 */
-unsigned int BSP_processor_frequency; 
+unsigned int BSP_processor_frequency; /* XXX - Set this based upon the Score board */

 /*
 * Time base divisior (how many tick for 1 second).
- * Note: Calibrated with an application using a 20ms timer and
- * a scope.
 */
-unsigned int BSP_time_base_divisor = 3960;
+unsigned int BSP_time_base_divisor = 4000;

 /*
 * system init stack
@@ -93,15 +90,15 @@ void bsp_pretasking_hook(void)
  uint32_t         heap_start;
  uint32_t         heap_size;

-  heap_start = (BSP_heap_start + CPU_ALIGNMENT - 1) & ~(CPU_ALIGNMENT-1);
-  heap_size = (uint32_t) &RAM_END;
-  heap_size = heap_size - heap_start - Configuration.work_space_size;
-  heap_size &= 0xfffffff0;  /* keep it as a multiple of 16 bytes */
-  
-
  #if DEBUG
-    printk("bsp_pretasking_hook: Set Heap start 0x%x size 0x%x\n", heap_start, heap_size);
+    printk("bsp_pretasking_hook: Set Heap\n");
  #endif
+  heap_start = (uint32_t) &end;
+  if (heap_start & (CPU_ALIGNMENT-1))
+    heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1);
+
+  heap_size = Configuration.work_space_start - (void *)&end;
+  heap_size &= 0xfffffff0;  /* keep it as a multiple of 16 bytes */

  #if DEBUG
    printk("bsp_pretasking_hook: bsp_libc_init\n");
@@ -124,13 +121,6 @@ void initialize_PMC();

 void bsp_predriver_hook(void)
 {
-  init_PCI();
-  initialize_universe();
-
-  #if DEBUG
-    printk("bsp_predriver_hook: initialize_PCI_bridge\n");
-  #endif
-  initialize_PCI_bridge ();

 #if (HAS_PMC_PSC8)
  #if DEBUG
@@ -191,11 +181,17 @@ void initialize_PMC() {

 void bsp_postdriver_hook(void)
 {
+  extern void Init_EE_mask_init(void);
  extern void open_dev_console(void);
  #if DEBUG
    printk("bsp_postdriver_hook: open_dev_console\n");
  #endif
  open_dev_console();
+
+  #if DEBUG
+    printk("bsp_postdriver_hook: Init_EE_mask_init\n");
+  #endif
+  Init_EE_mask_init();
  #if DEBUG
    printk("bsp_postdriver_hook: Finished procedure\n");
  #endif
@@ -254,9 +250,6 @@ void bsp_start( void )
  intrStackStart = (uint32_t) __rtems_end + INIT_STACK_SIZE;
  intrStackSize = rtems_configuration_get_interrupt_stack_size();
  BSP_heap_start = intrStackStart + intrStackSize;
-  printk("Interrupt Stack Start: 0x%x Size: 0x%x  Heap Start: 0x%x\n",
-    intrStackStart, intrStackSize, BSP_heap_start
-  );

  /*
   * Initialize default raw exception handlers.
@@ -266,10 +259,23 @@ void bsp_start( void )
    intrStackStart,
    intrStackSize
  );
+  #if DEBUG
+    printk("bsp_predriver_hook: init_RTC\n");
+  #endif
+
+/*   init_RTC(); */
+  init_PCI();
+  initialize_universe();
+
+  #if DEBUG
+    printk("bsp_predriver_hook: initialize_PCI_bridge\n");
+  #endif
+  initialize_PCI_bridge ();

  msr_value = 0x2030;
  _CPU_MSR_SET( msr_value );

+
  _CPU_MSR_SET( msr_value );

  /*
@@ -277,9 +283,12 @@ void bsp_start( void )
   *  tell the RTEMS configuration where it is.  This memory is
   *  not malloc'ed.  It is just "pulled from the air".
   */
+
+  #if DEBUG
+    printk("bsp_start: Calculate Wrokspace\n");
+  #endif
  work_space_start =
    (unsigned char *)&RAM_END - rtems_configuration_get_work_space_size();
-  printk("Work Space Start: 0x%x\n", work_space_start );

  if ( work_space_start <= (unsigned char *)&end ) {
    printk( "bspstart: Not enough RAM!!!\n" );
@@ -296,27 +305,24 @@ void bsp_start( void )
  #endif
  bsp_clicks_per_usec = 66 / 4;  /* XXX get from linkcmds */

-  #if ( PPC_USE_DATA_CACHE )
-    #if DEBUG
-      printk("bsp_start: cache_enable\n");
-    #endif
-    instruction_cache_enable ();
-    data_cache_enable ();
-    #if DEBUG
-      printk("bsp_start: END PPC_USE_DATA_CACHE\n");
-    #endif
+#if ( PPC_USE_DATA_CACHE )
+  #if DEBUG
+    printk("bsp_start: cache_enable\n");
  #endif
+  instruction_cache_enable ();
+  data_cache_enable ();
+  #if DEBUG
+    printk("bsp_start: END PPC_USE_DATA_CACHE\n");
+  #endif
+#endif
+
+  /* Initalize interrupt support */
+  if (bsp_interrupt_initialize() != RTEMS_SUCCESSFUL) {
+    BSP_panic( "Cannot intitialize interrupt support\n");
+  }

-  /*
-   * Initalize RTEMS IRQ system
-   */
-  #if DEBUG  
-    printk("bspstart: Call BSP_rtems_irq_mng_init\n");
-  #endif
-  BSP_rtems_irq_mng_init(0);
-  
  #if DEBUG
    printk("bsp_start: end BSPSTART\n");
-    ShowBATS();
+  ShowBATS();
  #endif
 }
--- a/c/src/lib/libbsp/powerpc/score603e/startup/genpvec.c
+++ b/c/src/lib/libbsp/powerpc/score603e/startup/genpvec.c
@@ -0,0 +1,196 @@
+/*  genpvec.c
+ *
+ *  These routines handle the external exception.  Multiple ISRs occur off
+ *  of this one interrupt.
+ *
+ *  COPYRIGHT (c) 1989-1997.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may in
+ *  the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ */
+
+#include <bsp.h>
+#include <rtems/chain.h>
+#include <rtems/bspIo.h>
+#include <assert.h>
+
+#include <stdio.h> /* for sprintf */
+
+/*
+ * Proto types for this file
+ */
+
+rtems_isr external_exception_ISR (
+  rtems_vector_number   vector                                  /* IN  */
+);
+
+#define   NUM_LIRQ_HANDLERS   20
+#define   NUM_LIRQ            ( MAX_BOARD_IRQS - PPC_IRQ_LAST )
+
+/*
+ * Structure to for one of possible multiple interrupt handlers for
+ * a given interrupt.
+ */
+typedef struct
+{
+  rtems_chain_node    Node;
+  rtems_isr_entry     handler;                  /* isr routine        */
+  rtems_vector_number vector;                   /* vector number      */
+} EE_ISR_Type;
+
+/* Note:  The following will not work if we add a method to remove
+ *        handlers at a later time.
+ */
+  EE_ISR_Type         ISR_Nodes [NUM_LIRQ_HANDLERS];
+  uint16_t            Nodes_Used;
+  rtems_chain_control ISR_Array  [NUM_LIRQ];
+
+/* XXX */
+void init_irq_data_register(void);
+
+#if 0
+void initialize_external_exception_vector (void)
+{
+  int i;
+  rtems_isr_entry previous_isr;
+  rtems_status_code status;
+
+  Nodes_Used = 0;
+
+  /*
+   * Mask out all interupts until they have a handler installed.
+   */
+
+  for (i=0; i <NUM_LIRQ; i++)
+    rtems_chain_initialize_empty( &ISR_Array[i] );
+
+  init_irq_data_register();
+
+  /*
+   * Install external_exception_ISR () as the handler for
+   *  the General Purpose Interrupt.
+   */
+  status = rtems_interrupt_catch( external_exception_ISR,
+           PPC_IRQ_EXTERNAL, (rtems_isr_entry *) &previous_isr );
+}
+#endif
+
+void Init_EE_mask_init() {
+;
+}
+
+/*
+ *  This routine installs one of multiple ISRs for the general purpose
+ *  inerrupt.
+ */
+rtems_isr_entry  set_EE_vector(
+  rtems_isr_entry     handler,      /* isr routine        */
+  rtems_vector_number vector        /* vector number      */
+)
+{
+  uint16_t         vec_idx  = vector - Score_IRQ_First;
+  uint32_t         index;
+
+  assert  (Nodes_Used < NUM_LIRQ_HANDLERS);
+
+  /*
+   *  If we have already installed this handler for this vector, then
+   *  just reset it.
+   */
+
+  for ( index=0 ; index <= Nodes_Used ; index++ ) {
+    if ( ISR_Nodes[index].vector == vector &&
+         ISR_Nodes[index].handler == handler )
+      return NULL;
+  }
+
+  /*
+   *  Doing things in this order makes them more atomic
+   */
+
+  Nodes_Used++;
+
+  index = Nodes_Used - 1;
+
+  ISR_Nodes[index].handler = handler;
+  ISR_Nodes[index].vector  = vector;
+
+  /* printf( "Vector Index: %04x, Vector: %d (%x)\n",
+          vec_idx, vector, vector); */
+
+  rtems_chain_append( &ISR_Array[vec_idx], &ISR_Nodes[index].Node );
+
+  /*
+   * Unmask the interrupt.
+   */
+  unmask_irq( vec_idx );
+
+  return NULL;
+}
+
+/*
+ * This interrupt service routine is called for an External Exception.
+ */
+rtems_isr external_exception_ISR (
+  rtems_vector_number   vector             /* IN  */
+)
+{
+ uint16_t            index;
+ EE_ISR_Type         *node;
+ uint16_t            value;
+#if (HAS_PMC_PSC8)
+ uint16_t            PMC_irq;
+ uint16_t            check_irq;
+ uint16_t            status_word;
+#endif
+
+ index = read_and_clear_irq();
+ if ( index >= NUM_LIRQ ) {
+   printk( "ERROR:: Invalid interrupt number (%02x)\n", index );
+   return;
+ }
+
+#if (HAS_PMC_PSC8)
+  PMC_irq = SCORE603E_PCI_IRQ_0 - SCORE603E_IRQ00;
+
+  if (index ==  PMC_irq) {
+    status_word = read_and_clear_PMC_irq( index );
+
+    for (check_irq=SCORE603E_IRQ16; check_irq<=SCORE603E_IRQ19; check_irq++) {
+      if ( Is_PMC_IRQ( check_irq, status_word )) {
+        index = check_irq - SCORE603E_IRQ00;
+        node = (EE_ISR_Type *)(ISR_Array[ index ].first);
+
+        if ( rtems_chain_is_tail( &ISR_Array[ index ], (void *)node ) ) {
+          printk ("ERROR:: check %d interrupt %02d has no isr\n", check_irq, index);
+          value = get_irq_mask();
+          printk("        Mask = %02x\n", value);
+	}
+        while ( !rtems_chain_is_tail( &ISR_Array[ index ], (void *)node ) ) {
+          (*node->handler)( node->vector );
+          node = (EE_ISR_Type *) node->Node.next;
+        }
+      }
+    }
+  }
+  else
+#endif
+  {
+    node = (EE_ISR_Type *)(ISR_Array[ index ].first);
+    if ( rtems_chain_is_tail( &ISR_Array[ index ], (void *)node ) ) {
+      printk( "ERROR:: interrupt %02x has no isr\n", index);
+      value = get_irq_mask();
+      printk("        Mask = %02x\n", value);
+      return;
+    }
+    while ( !rtems_chain_is_tail( &ISR_Array[ index ], (void *)node ) ) {
+     (*node->handler)( node->vector );
+     node = (EE_ISR_Type *) node->Node.next;
+    }
+  }
+
+}
--- a/c/src/lib/libbsp/powerpc/score603e/startup/setvec.c
+++ b/c/src/lib/libbsp/powerpc/score603e/startup/setvec.c
@@ -0,0 +1,70 @@
+/*  set_vector
+ *
+ *  This routine installs an interrupt vector on the target Board/CPU.
+ *  This routine is allowed to be as board dependent as necessary.
+ *
+ *  INPUT:
+ *    handler - interrupt handler entry point
+ *    vector  - vector number
+ *    type    - 0 indicates raw hardware connect
+ *              1 indicates RTEMS interrupt connect
+ *
+ *  RETURNS:
+ *    address of previous interrupt handler
+ *
+ *  Author:	Andrew Bray <andy@i-cubed.co.uk>
+ *
+ *  COPYRIGHT (c) 1995 by i-cubed ltd.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of i-cubed limited not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      i-cubed limited makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Derived from c/src/lib/libbsp/no_cpu/no_bsp/startup/setvec.c:
+ *
+ *  COPYRIGHT (c) 1989-1997.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may in
+ *  the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id:
+ */
+
+#include <rtems.h>
+#include <bsp.h>
+
+/*
+ *  This routine installs vector number vector.
+ *
+ */
+rtems_isr_entry set_vector(                    /* returns old vector */
+  rtems_isr_entry     handler,                  /* isr routine        */
+  rtems_vector_number vector,                   /* vector number      */
+  int                 type                      /* RTEMS or RAW intr  */
+)
+{
+  rtems_isr_entry previous_isr;
+  rtems_status_code status;
+
+  /*
+   * vectors greater than PPC603e_IRQ_LAST are handled by the General purpose
+   * interupt handler.
+   */
+  if ( vector > PPC_IRQ_LAST )  {
+    set_EE_vector( handler, vector );
+  }
+  else  {
+    status = rtems_interrupt_catch(
+       handler, vector, (rtems_isr_entry *) &previous_isr );
+  }
+  return previous_isr;
+}
--- a/c/src/lib/libbsp/powerpc/score603e/startup/vmeintr.c
+++ b/c/src/lib/libbsp/powerpc/score603e/startup/vmeintr.c
@@ -0,0 +1,55 @@
+/*  vmeintr.c
+ *
+ *  VMEbus support routines for the Generation I board.
+ *
+ *  COPYRIGHT (c) 1989-1997.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may in
+ *  the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id:
+ */
+
+#include <rtems.h>
+#include <bsp.h>
+#include <rtems/vmeintr.h>
+
+/*PAGE
+ *
+ *  VME_interrupt_Disable
+ *
+ */
+
+void VME_interrupt_Disable (
+  VME_interrupt_Mask                mask                        /* IN  */
+)
+{
+  volatile uint8_t  *VME_interrupt_enable;
+  uint8_t           value;
+
+  VME_interrupt_enable = 0;
+  value = *VME_interrupt_enable;
+  value &= ~mask;  /* turn off interrupts for all levels in mask */
+  *VME_interrupt_enable = value;
+}
+
+/*PAGE
+ *
+ *  VME_interrupt_Enable
+ *
+ */
+
+void VME_interrupt_Enable (
+  VME_interrupt_Mask                mask                        /* IN  */
+)
+{
+  volatile uint8_t          *VME_interrupt_enable;
+  uint8_t          value;
+
+  VME_interrupt_enable = 0;
+  value = *VME_interrupt_enable;
+  value |= mask;  /* turn on interrupts for all levels in mask */
+  *VME_interrupt_enable = value;
+}
--- a/c/src/lib/libbsp/powerpc/score603e/timer/timer.c
+++ b/c/src/lib/libbsp/powerpc/score603e/timer/timer.c
@@ -7,11 +7,11 @@
 *  BSP_TIMER_AVG_OVERHEAD and BSP_TIMER_LEAST_VALID are required to be
 *  provided in bsp.h
 *
- *  COPYRIGHT (c) 1989-2009.
+ *  COPYRIGHT (c) 1989-1997.
 *  On-Line Applications Research Corporation (OAR).
 *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
+ *  The license and distribution terms for this file may in
+ *  the file LICENSE in this distribution or at
 *  http://www.rtems.com/license/LICENSE.
 *
 *  $Id$
--- a/c/src/lib/libbsp/powerpc/score603e/tod/tod.c
+++ b/c/src/lib/libbsp/powerpc/score603e/tod/tod.c
@@ -3,9 +3,6 @@
 *
 *  This part is found on the second generation of this board.
 *
- *  COPYRIGHT (c) 1989-2009.
- *  On-Line Applications Research Corporation (OAR).
- *
 *  The license and distribution terms for this file may be
 *  found in the file LICENSE in this distribution or at
 *  http://www.rtems.com/license/LICENSE.
--- a/c/src/lib/libbsp/shared/ChangeLog
+++ b/c/src/lib/libbsp/shared/ChangeLog
@@ -1,8 +1,3 @@
-2009-05-06	Michael Walle <michael@walle.cc>
-
-	PR 1409/bsps
-	* gdbstub/rtems-stub-glue.c: Print object names correctly.
-
 2009-03-05	Till Straumann <strauman@slac.stanford.edu>

 	* bootcard.c: use aligned heap_start (instead of
--- a/c/src/lib/libbsp/shared/gdbstub/rtems-stub-glue.c
+++ b/c/src/lib/libbsp/shared/gdbstub/rtems-stub-glue.c
@@ -335,7 +335,7 @@ int rtems_gdb_stub_get_thread_info(
      tmp_buf[8] = 0;

      strcat(info->display, tmp_buf);
-      rtems_object_get_name( ((Objects_Control*)th)->id, 5, info->name );
+      rtems_object_get_name( thread, 5, info->name );
      info->more_display[0] = 0; /* Nothing */

      return 1;
@@ -367,7 +367,7 @@ int rtems_gdb_stub_get_thread_info(
   tmp_buf[8] = 0;

   strcat(info->display, tmp_buf);
-   rtems_object_get_name( ((Objects_Control*)th)->id, 5, info->name );
+   rtems_object_get_name( thread, 5, info->name );
   info->more_display[0] = 0; /* Nothing */

   return 1;
--- a/c/src/lib/libcpu/m68k/ChangeLog
+++ b/c/src/lib/libcpu/m68k/ChangeLog
@@ -1,9 +1,3 @@
-2009-09-10	Till Straumann <strauman@slac.stanford.edu>
-
-	PR 1438/bsps
-	* shared/misc/m68kidle.c: added "cc" clobber to inline
-	asm; STOP instruction modifies CCR!
-
 2009-02-11	Till Straumann <strauman@slac.stanford.edu>

 	PR 1369/bsps
--- a/c/src/lib/libcpu/m68k/shared/misc/m68kidle.c
+++ b/c/src/lib/libcpu/m68k/shared/misc/m68kidle.c
@@ -38,6 +38,6 @@ void *_CPU_Thread_Idle_body( uint32_t ignored )
  }
 #else
  for( ; ; )
-    asm volatile( "stop #0x3000":::"cc" );  /* supervisor mode, all interrupts on */
+    asm volatile( "stop #0x3000" );  /* supervisor mode, all interrupts on */
 #endif
 }
--- a/c/src/lib/libcpu/powerpc/ChangeLog
+++ b/c/src/lib/libcpu/powerpc/ChangeLog
@@ -1,18 +1,3 @@
-2009-10-16	Jennifer Averett <jennifer.averett@OARcorp.com>
-
-	* mpc6xx/mmu/bat.c: Resolved bug: It is not an overlap if the batindex
-	being set is the batindex of the overlap.
-
-2009-10-16	Jennifer Averett <jennifer.averett@OARcorp.com>
-
-	* shared/include/io.h: Backport change from extern inline to static
-	inline from head to avoid multiple definitions.
-
-2009-05-05	Jennifer Averett <jennifer.averett@OARcorp.com>
-
-	* new-exceptions/bspsupport/irq_supp.h: Split routine to allow bsps
-	with nonstandard/non-existant pics to call with interrupts off.
-
 2009-03-12	Joel Sherrill <joel.sherrill@OARcorp.com>

 	PR 1385/cpukit
--- a/Show More
+++ b/Show More