forked from Imagelibrary/rtems
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1 Commits
| Author | SHA1 | Date | |
|---|---|---|---|
|
c5cea43cde |
@@ -21,10 +21,10 @@ The following persons/organizations have made contributions:
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||||
Research to port RTEMS to the Hewlett-Packard PA-RISC architecture (V1.1)
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and the addition of HP-UX as a development host. Tony Bennett
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(tbennett@divnc.com) was assisted in this effort by Joel Sherrill
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(joel@OARcorp.com). Tony also deserves a big pat on the back for
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contributing significantly to the overall organization of the development
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environment and directory structure. RTEMS is much easier to build
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because of Tony.
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(jsherril@redstone.army.mil). Tony also deserves a big pat on the
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back for contributing significantly to the overall organization
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of the development environment and directory structure. RTEMS
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is much easier to build because of Tony.
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+ Greg Allen of Division Inc. of Chapel Hill, NC for
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porting RTEMS to HP-UX. This port treats a UNIX computer as simply
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@@ -71,14 +71,6 @@ The following persons/organizations have made contributions:
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for developing and supporting the SPARC Instruction Simulator used to
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develop and test this port.
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+ Eric Norum (eric@skatter.usask.ca) of the Saskatchewan Accelerator
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Laboratory submitted the support for the Motorola MC68360 CPU
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including the `gen68360' BSP.
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+ Dominique le Campion (Dominique.LECAMPION@enst-bretagne.fr), for
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Telecom Bretagne and T.N.I. (Brest, France) submitted the BSP for
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the Motorola MVME147 board (68030 CPU + 68881 FPU).
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Finally, the RTEMS project would like to thank those who have contributed
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to the other free software efforts which RTEMS utilizes. The primary RTEMS
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development environment is from the Free Software Foundation (the GNU
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18
c/PROBLEMS
18
c/PROBLEMS
@@ -4,21 +4,23 @@
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This is the list of outstanding problems in this release.
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+ The POSIX threads and real time extensions code in this tree are
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not completely tested yet. Some of the POSIX tests do run but none
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of the POSIX code is in the normal build path.
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+ The POSIX threads and real time extensions code in this tree does
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not work yet and is intentionally not in the normal build path.
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+ The test spfatal is out of date and as a result will NOT execute
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correctly. The addition of POSIX and consequent ongoing initialization
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reorganization makes it pointless to fix this until the POSIX support
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is completely in place.
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+ The m68k family has become quite large and an understanding of the
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compatibility of the peripherals on the various members of the 683xx
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family would allow someone to designate some of the drivers submitted
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for the gen683xx BSPs as useful on other members.
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+ The m68000 support is nearly complete now. The missing piece
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inside the executive proper is support for the software interrupt
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stack. Also, the m68k family has become quite large and an
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understanding of the compatibility of the peripherals on the various
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members of the 683xx family would allow someone to designate some
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of the drivers submitted for the gen683xx BSPs as useful on other
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members.
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+ The only supported i960 family member is the CA. No support for the
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+ The only i960 family member tested is the CA. No support for the
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floating point support found in other family members is present.
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This also implies that RTEMS may "think" of something as generic
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across the i960 family when in fact it is specific to the CA.
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@@ -5,9 +5,9 @@
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1. The installation procedure assumes that "gcc" is installed
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and is in your path for the installation of local tools.
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2. gcc 2.7.2 with crossgcc patches (ftp.cygnus.com:/pub/embedded/crossgcc)
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2. gcc 2.6.3 with crossgcc patches (ftp.cygnus.com:/pub/embedded)
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3. binutils 2.6 with crossgcc patches.
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3. binutils 2.5.2
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4. newlib with RTEMS configurations.
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75
c/TESTED
75
c/TESTED
@@ -2,50 +2,55 @@
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# $Id$
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#
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This file is current as of the 3.5.17 snapshot.
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The RTEMS Project does not have all of the development computers or
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target boards included in the RTEMS distribution. Many of the BSPs
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are user supplied and we try to insure that they compile before each
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full release. This file describes the range of configurations the
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RTEMS project can internally test.
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The RTEMS project uses SparcStations running the Solaris 2.3 operating
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system internally for development. This release has been tested on the
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following Languages/CPUs/Targets using Solaris 2.3/SPARC as the host
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environment:
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Host Development Systems
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========================
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CPU CPU
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LANGUAGE FAMILY MODEL TARGET SUITES
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======== ====== ========= =================== ===============
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C m68k m68000 efi68k (note 1)
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C m68k m68020 Motorola MVME136 ALL TESTS
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C m68k m68020 Motorola MVME147 (note 1)
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C m68k m68lc040 Motorola MVME162 (note 1)
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C m68k m68ec040 Motorola IDP (note 1)
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C m68k m68020 DY-4 DMV152 (note 1)
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C m68k m68302 generic 68302 (note 1)
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C m68k m68332 efi332 (note 1)
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C m68k m68302 generic 68360 (note 1)
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C i386 i386_fp Force CPU-386 ALL TESTS
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C i386 i486 DJGPP/PC-AT ALL TESTS
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C i386 pentium DJGPP/PC-AT ALL TESTS
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C i960 i960ca Cyclone CVME961 (note 4)
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C hppa hppa7100 simhppa (note 1)
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C ppc 403 Papyrus (note 1)
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C UNIX NA Solaris 2 (SPARC) ALL TESTS (inlines)
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C UNIX NA Solaris 2 (SPARC) ALL TESTS (macros)
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C UNIX NA Linux (i386) NOT TESTED
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C UNIX NA HPUX (PA-RISC) (note 2)
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C no_cpu NA no_bsp (note 3)
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All RTEMS development is done on a Sun SPARCStation running Solaris 2.3 and
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all other host systems are not tested internally.
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NOTES:
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Target Systems
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==============
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"NOT TESTED" indicates that this was not tested in the testing cycle
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immediately preceding the snapshot.
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The following table describes the testability of each BSP by the RTEMS project:
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CPU CPU
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FAMILY MODEL TARGET STATUS
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====== ========= =================== =================
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m68k m68000 efi68k (note 1)
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m68k m68020 Motorola MVME136 TESTED INTERNALLY
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m68k m68lc040 Motorola MVME162 (note 1)
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m68k m68ec040 Motorola IDP (note 1)
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m68k m68020 DY-4 DMV152 (note 1)
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m68k m68302 generic 68302 (note 1)
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m68k m68332 efi332 (note 1)
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i386 i386_fp Force CPU-386 TESTED INTERNALLY
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i386 i486 DJGPP/PC-AT TESTED INTERNALLY
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i386 pentium DJGPP/PC-AT TESTED INTERNALLY
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i960 i960ca Cyclone CVME961 (note 4)
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hppa hppa7100 simhppa (note 2)
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ppc 403 Papyrus (note 2)
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UNIX NA Solaris 2 (SPARC) TESTED INTERNALLY (inlines)
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UNIX NA Solaris 2 (SPARC) TESTED INTERNALLY (macros)
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UNIX NA Linux (i386) (note 5)
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UNIX NA HPUX (PA-RISC) (note 2)
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no_cpu NA no_bsp (note 3)
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(1) Target board is not owned by RTEMS Project. The target is known
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to compile and link with all appropriate tests successfully.
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If the target does not support multiprocessor configurations, then
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"ALL TESTS" does not include the multiprocessor tests.
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(2) RTEMS Project cannot internally compile or test this target.
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(3) Target is not intended to be executed. It is only an example.
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(4) The RTEMS Project owns this board but it is broken at the moment.
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(4) The board owned by the RTEMS Project is broken. The BSP is known
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to compile and link with all appropriate tests successfully.
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(5) The RTEMS Project owns a Linux host but does not regularly test this BSP.
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@@ -88,12 +88,8 @@ void error(int errn, ...);
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#define ERR_ABORT (ERR_ERRNO / 4) /* error is fatal; abort */
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#define ERR_MASK (ERR_ERRNO | ERR_FATAL | ERR_ABORT) /* all */
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#if (defined(sparc) && (sunos < 500))
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#define stol(p) strtol(p, (char **) NULL, 0) /* Sunos */
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#else
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#define stol(p) strtoul(p, (char **) NULL, 0) /* Solaris */
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#endif
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#define stol(p) strtoul(p, (char **) NULL, 0)
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int unhex(FILE *ifp, char *inm, FILE *ofp, char *onm);
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int convert_Intel_records(FILE *ifp, char *inm, FILE *ofp, char *onm);
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int convert_S_records(FILE *ifp, char *inm, FILE *ofp, char *onm);
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@@ -100,9 +100,75 @@ typedef struct {
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#define RTEMS_SIGNAL_30 0x40000000
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#define RTEMS_SIGNAL_31 0x80000000
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#ifndef __RTEMS_APPLICATION__
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/*
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* _ASR_Initialize
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*
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* DESCRIPTION:
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*
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* This routine initializes the given RTEMS_ASR information record.
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*/
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STATIC INLINE void _ASR_Initialize (
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ASR_Information *information
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);
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/*
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* _ASR_Swap_signals
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*
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* DESCRIPTION:
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*
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* This routine atomically swaps the pending and posted signal
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* sets. This is done when the thread alters its mode in such a
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* way that the RTEMS_ASR disable/enable flag changes.
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*/
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STATIC INLINE void _ASR_Swap_signals (
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ASR_Information *information
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);
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/*
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* _ASR_Is_null_handler
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*
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* DESCRIPTION:
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*
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* This function returns TRUE if the given asr_handler is NULL and
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* FALSE otherwise.
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*/
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STATIC INLINE boolean _ASR_Is_null_handler (
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rtems_asr_entry asr_handler
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);
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/*
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* _ASR_Are_signals_pending
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*
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* DESCRIPTION:
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*
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* This function returns TRUE if there are signals pending in the
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* given RTEMS_ASR information record and FALSE otherwise.
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*/
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STATIC INLINE boolean _ASR_Are_signals_pending (
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ASR_Information *information
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);
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/*
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* _ASR_Post_signals
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*
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* DESCRIPTION:
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*
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* This routine posts the given signals into the signal_set
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* passed in. The result is returned to the user in signal_set.
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*
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* NOTE: This must be implemented as a macro.
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*/
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STATIC INLINE void _ASR_Post_signals(
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rtems_signal_set signals,
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rtems_signal_set *signal_set
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);
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#include <rtems/rtems/asr.inl>
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#endif
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#ifdef __cplusplus
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}
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@@ -72,10 +72,130 @@ typedef unsigned32 rtems_attribute;
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#define _Attributes_Handler_initialization()
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#ifndef __RTEMS_APPLICATION__
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#include <rtems/rtems/attr.inl>
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/*
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* _Attributes_Set
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*
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* DESCRIPTION:
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*
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* This function sets the requested new_attributes in the attribute_set
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* passed in. The result is returned to the user.
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*/
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STATIC INLINE rtems_attribute _Attributes_Set (
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rtems_attribute new_attributes,
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rtems_attribute attribute_set
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);
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/*
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* _Attributes_Clear
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*
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* DESCRIPTION:
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*
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* This function clears the requested new_attributes in the attribute_set
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* passed in. The result is returned to the user.
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*/
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STATIC INLINE rtems_attribute _Attributes_Clear (
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rtems_attribute attribute_set,
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rtems_attribute mask
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);
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/*
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* _Attributes_Is_floating_point
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*
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* DESCRIPTION:
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*
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* This function returns TRUE if the floating point attribute is
|
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* enabled in the attribute_set and FALSE otherwise.
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*/
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STATIC INLINE boolean _Attributes_Is_floating_point(
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rtems_attribute attribute_set
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);
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/*
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* _Attributes_Is_global
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*
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||||
* DESCRIPTION:
|
||||
*
|
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* This function returns TRUE if the global object attribute is
|
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* enabled in the attribute_set and FALSE otherwise.
|
||||
*/
|
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STATIC INLINE boolean _Attributes_Is_global(
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rtems_attribute attribute_set
|
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);
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/*
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* _Attributes_Is_priority
|
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*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the priority attribute is
|
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* enabled in the attribute_set and FALSE otherwise.
|
||||
*/
|
||||
|
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STATIC INLINE boolean _Attributes_Is_priority(
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rtems_attribute attribute_set
|
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);
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|
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#if 0
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/*
|
||||
* _Attributes_Is_limit
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the limited attribute is
|
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* enabled in the attribute_set and FALSE otherwise.
|
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*/
|
||||
|
||||
STATIC INLINE boolean _Attributes_Is_limit(
|
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rtems_attribute attribute_set
|
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);
|
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#endif
|
||||
|
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/*
|
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* _Attributes_Is_binary_semaphore
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the binary semaphore attribute is
|
||||
* enabled in the attribute_set and FALSE otherwise.
|
||||
*/
|
||||
|
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STATIC INLINE boolean _Attributes_Is_binary_semaphore(
|
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rtems_attribute attribute_set
|
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);
|
||||
|
||||
/*
|
||||
* _Attributes_Is_inherit_priority
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the priority inheritance attribute
|
||||
* is enabled in the attribute_set and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Attributes_Is_inherit_priority(
|
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rtems_attribute attribute_set
|
||||
);
|
||||
|
||||
/*
|
||||
* _Attributes_Is_priority_ceiling
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the priority ceiling attribute
|
||||
* is enabled in the attribute_set and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Attributes_Is_priority_ceiling(
|
||||
rtems_attribute attribute_set
|
||||
);
|
||||
|
||||
|
||||
#include <rtems/rtems/attr.inl>
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -1,54 +0,0 @@
|
||||
/* config.h
|
||||
*
|
||||
* This include file contains the table of user defined configuration
|
||||
* parameters specific for the RTEMS API.
|
||||
*
|
||||
* COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
* All rights assigned to U.S. Government, 1994.
|
||||
*
|
||||
* This material may be reproduced by or for the U.S. Government pursuant
|
||||
* to the copyright license under the clause at DFARS 252.227-7013. This
|
||||
* notice must appear in all copies of this file and its derivatives.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef __RTEMS_RTEMS_CONFIGURATION_h
|
||||
#define __RTEMS_RTEMS_CONFIGURATION_h
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <rtems/rtems/types.h>
|
||||
#include <rtems/rtems/tasks.h>
|
||||
|
||||
/*
|
||||
* The following records define the Configuration Table. The
|
||||
* information contained in this table is required in all
|
||||
* RTEMS systems, whether single or multiprocessor. This
|
||||
* table primarily defines the following:
|
||||
*
|
||||
* + required number of each object type
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
unsigned32 maximum_tasks;
|
||||
unsigned32 maximum_timers;
|
||||
unsigned32 maximum_semaphores;
|
||||
unsigned32 maximum_message_queues;
|
||||
unsigned32 maximum_partitions;
|
||||
unsigned32 maximum_regions;
|
||||
unsigned32 maximum_ports;
|
||||
unsigned32 maximum_periods;
|
||||
unsigned32 number_of_initialization_tasks;
|
||||
rtems_initialization_tasks_table *User_initialization_tasks_table;
|
||||
} rtems_api_configuration_table;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
/* end of include file */
|
||||
@@ -51,7 +51,7 @@ typedef struct {
|
||||
* The following define the internal Dual Ported Memory information.
|
||||
*/
|
||||
|
||||
RTEMS_EXTERN Objects_Information _Dual_ported_memory_Information;
|
||||
EXTERN Objects_Information _Dual_ported_memory_Information;
|
||||
|
||||
/*
|
||||
* _Dual_ported_memory_Manager_initialization
|
||||
@@ -145,9 +145,62 @@ rtems_status_code rtems_port_internal_to_external(
|
||||
void **external
|
||||
);
|
||||
|
||||
#ifndef __RTEMS_APPLICATION__
|
||||
/*
|
||||
* _Dual_ported_memory_Allocate
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine allocates a port control block from the inactive chain
|
||||
* of free port control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE Dual_ported_memory_Control
|
||||
*_Dual_ported_memory_Allocate ( void );
|
||||
|
||||
/*
|
||||
* _Dual_ported_memory_Free
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine frees a port control block to the inactive chain
|
||||
* of free port control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _Dual_ported_memory_Free (
|
||||
Dual_ported_memory_Control *the_port
|
||||
);
|
||||
|
||||
/*
|
||||
* _Dual_ported_memory_Get
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function maps port IDs to port control blocks. If ID
|
||||
* corresponds to a local port, then it returns the_port control
|
||||
* pointer which maps to ID and location is set to OBJECTS_LOCAL.
|
||||
* Global ports are not supported, thus if ID does not map to a
|
||||
* local port, location is set to OBJECTS_ERROR and the_port is
|
||||
* undefined.
|
||||
*/
|
||||
|
||||
STATIC INLINE Dual_ported_memory_Control *_Dual_ported_memory_Get (
|
||||
Objects_Id id,
|
||||
Objects_Locations *location
|
||||
);
|
||||
|
||||
/*
|
||||
* _Dual_ported_memory_Is_null
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_port is NULL and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Dual_ported_memory_Is_null(
|
||||
Dual_ported_memory_Control *the_port
|
||||
);
|
||||
|
||||
#include <rtems/rtems/dpmem.inl>
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -48,21 +48,20 @@ extern "C" {
|
||||
*/
|
||||
|
||||
typedef enum {
|
||||
EVENT_SYNC_SYNCHRONIZED,
|
||||
EVENT_SYNC_NOTHING_HAPPENED,
|
||||
EVENT_SYNC_TIMEOUT,
|
||||
EVENT_SYNC_SATISFIED
|
||||
} Event_Sync_states;
|
||||
|
||||
/*
|
||||
* Event_Manager_initialization
|
||||
* _Event_Manager_initialization
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine performs the initialization necessary for this manager.
|
||||
*/
|
||||
|
||||
void _Event_Manager_initialization( void );
|
||||
|
||||
STATIC INLINE void _Event_Manager_initialization( void );
|
||||
|
||||
/*
|
||||
* rtems_event_send
|
||||
@@ -154,17 +153,16 @@ void _Event_Timeout (
|
||||
);
|
||||
|
||||
/*
|
||||
* The following defines the synchronization flag used by the
|
||||
* The following defines the synchronization flags used by the
|
||||
* Event Manager to insure that signals sent to the currently
|
||||
* executing thread are received properly.
|
||||
*/
|
||||
|
||||
RTEMS_EXTERN volatile Event_Sync_states _Event_Sync_state;
|
||||
EXTERN volatile boolean _Event_Sync;
|
||||
EXTERN volatile Event_Sync_states _Event_Sync_state;
|
||||
|
||||
#include <rtems/rtems/eventmp.h>
|
||||
#ifndef __RTEMS_APPLICATION__
|
||||
#include <rtems/rtems/event.inl>
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -77,9 +77,62 @@ typedef unsigned32 rtems_event_set;
|
||||
|
||||
#define EVENT_SETS_NONE_PENDING 0
|
||||
|
||||
#ifndef __RTEMS_APPLICATION__
|
||||
/*
|
||||
* _Event_sets_Is_empty
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if on events are posted in the event_set,
|
||||
* and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Event_sets_Is_empty(
|
||||
rtems_event_set the_event_set
|
||||
);
|
||||
|
||||
/*
|
||||
* _Event_sets_Post
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine posts the given new_events into the event_set
|
||||
* passed in. The result is returned to the user in event_set.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _Event_sets_Post(
|
||||
rtems_event_set the_new_events,
|
||||
rtems_event_set *the_event_set
|
||||
);
|
||||
|
||||
/*
|
||||
* _Event_sets_Get
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns the events in event_condition which are
|
||||
* set in event_set.
|
||||
*/
|
||||
|
||||
STATIC INLINE rtems_event_set _Event_sets_Get(
|
||||
rtems_event_set the_event_set,
|
||||
rtems_event_set the_event_condition
|
||||
);
|
||||
|
||||
/*
|
||||
* _Event_sets_Clear
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function removes the events in mask from the event_set
|
||||
* passed in. The result is returned to the user in event_set.
|
||||
*/
|
||||
|
||||
STATIC INLINE rtems_event_set _Event_sets_Clear(
|
||||
rtems_event_set the_event_set,
|
||||
rtems_event_set the_mask
|
||||
);
|
||||
|
||||
#include <rtems/rtems/eventset.inl>
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -114,20 +114,6 @@ rtems_status_code rtems_interrupt_catch(
|
||||
#define rtems_interrupt_flash( _isr_cookie ) \
|
||||
_ISR_Flash(_isr_cookie)
|
||||
|
||||
/*
|
||||
* rtems_interrupt_is_in_progress
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the processor is currently servicing
|
||||
* and interrupt and FALSE otherwise. A return value of TRUE indicates
|
||||
* that the caller is an interrupt service routine, NOT a thread. The
|
||||
* directives available to an interrupt service routine are restricted.
|
||||
*/
|
||||
|
||||
#define rtems_interrupt_is_in_progress() \
|
||||
_ISR_Is_in_progress()
|
||||
|
||||
/*
|
||||
* rtems_interrupt_cause
|
||||
*
|
||||
|
||||
@@ -68,7 +68,7 @@ typedef struct {
|
||||
* manage this class of objects.
|
||||
*/
|
||||
|
||||
RTEMS_EXTERN Objects_Information _Message_queue_Information;
|
||||
EXTERN Objects_Information _Message_queue_Information;
|
||||
|
||||
/*
|
||||
* _Message_queue_Manager_initialization
|
||||
@@ -261,6 +261,19 @@ rtems_status_code _Message_queue_Submit(
|
||||
Message_queue_Submit_types submit_type
|
||||
);
|
||||
|
||||
/*
|
||||
* _Message_queue_Is_null
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function places the_message at the rear of the outstanding
|
||||
* messages on the_message_queue.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Message_queue_Is_null (
|
||||
Message_queue_Control *the_message_queue
|
||||
);
|
||||
|
||||
/*
|
||||
* _Message_queue_Allocate
|
||||
*
|
||||
@@ -275,6 +288,39 @@ Message_queue_Control *_Message_queue_Allocate (
|
||||
unsigned32 max_message_size
|
||||
);
|
||||
|
||||
/*
|
||||
* _Message_queue_Free
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine deallocates a message queue control block into
|
||||
* the inactive chain of free message queue control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _Message_queue_Free (
|
||||
Message_queue_Control *the_message_queue
|
||||
);
|
||||
|
||||
/*
|
||||
* _Message_queue_Get
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function maps message queue IDs to message queue control
|
||||
* blocks. If ID corresponds to a local message queue, then it
|
||||
* returns the_message_queue control pointer which maps to ID
|
||||
* and location is set to OBJECTS_LOCAL. If the message queue ID is
|
||||
* global and resides on a remote node, then location is set
|
||||
* to OBJECTS_REMOTE, and the_message_queue is undefined.
|
||||
* Otherwise, location is set to OBJECTS_ERROR and
|
||||
* the_message_queue is undefined.
|
||||
*/
|
||||
|
||||
STATIC INLINE Message_queue_Control *_Message_queue_Get (
|
||||
Objects_Id id,
|
||||
Objects_Locations *location
|
||||
);
|
||||
|
||||
/*
|
||||
* _Message_queue_Translate_core_message_queue_return_code
|
||||
*
|
||||
@@ -304,9 +350,7 @@ void _Message_queue_Core_message_queue_mp_support (
|
||||
Objects_Id id
|
||||
);
|
||||
|
||||
#ifndef __RTEMS_APPLICATION__
|
||||
#include <rtems/rtems/message.inl>
|
||||
#endif
|
||||
#include <rtems/rtems/msgmp.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -59,8 +59,7 @@ typedef unsigned32 Modes_Control;
|
||||
* RTEMS supports 0 to 256 levels in bits 0-7 of the mode.
|
||||
*/
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
/*
|
||||
* RTEMS_INTERRUPT_LEVEL
|
||||
*
|
||||
* DESCRIPTION:
|
||||
@@ -73,13 +72,108 @@ typedef unsigned32 Modes_Control;
|
||||
* particular CPU, fewer than 256 levels may be supported.
|
||||
*/
|
||||
|
||||
#define RTEMS_INTERRUPT_LEVEL( _mode_set ) \
|
||||
( (_mode_set) & RTEMS_INTERRUPT_MASK )
|
||||
|
||||
STATIC INLINE unsigned32 RTEMS_INTERRUPT_LEVEL (
|
||||
Modes_Control mode_set
|
||||
);
|
||||
|
||||
/*
|
||||
* _Modes_Mask_changed
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if any of the mode flags in mask
|
||||
* are set in mode_set, and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Modes_Mask_changed (
|
||||
Modes_Control mode_set,
|
||||
Modes_Control masks
|
||||
);
|
||||
|
||||
/*
|
||||
* _Modes_Is_asr_disabled
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if mode_set indicates that Asynchronous
|
||||
* Signal Processing is disabled, and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Modes_Is_asr_disabled (
|
||||
Modes_Control mode_set
|
||||
);
|
||||
|
||||
/*
|
||||
* _Modes_Is_preempt
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if mode_set indicates that preemption
|
||||
* is enabled, and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Modes_Is_preempt (
|
||||
Modes_Control mode_set
|
||||
);
|
||||
|
||||
/*
|
||||
* _Modes_Is_timeslice
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if mode_set indicates that timeslicing
|
||||
* is enabled, and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Modes_Is_timeslice (
|
||||
Modes_Control mode_set
|
||||
);
|
||||
|
||||
/*
|
||||
* _Modes_Get_interrupt_level
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns the interrupt level portion of the mode_set.
|
||||
*/
|
||||
|
||||
STATIC INLINE ISR_Level _Modes_Get_interrupt_level (
|
||||
Modes_Control mode_set
|
||||
);
|
||||
|
||||
/*
|
||||
* _Modes_Set_interrupt_level
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine sets the current interrupt level to that specified
|
||||
* in the mode_set.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _Modes_Set_interrupt_level (
|
||||
Modes_Control mode_set
|
||||
);
|
||||
|
||||
/*
|
||||
* _Modes_Change
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine changes the modes in old_mode_set indicated by
|
||||
* mask to the requested values in new_mode_set. The resulting
|
||||
* mode set is returned in out_mode_set and the modes that changed
|
||||
* is returned in changed.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _Modes_Change (
|
||||
Modes_Control old_mode_set,
|
||||
Modes_Control new_mode_set,
|
||||
Modes_Control mask,
|
||||
Modes_Control *out_mode_set,
|
||||
Modes_Control *changed
|
||||
);
|
||||
|
||||
#ifndef __RTEMS_APPLICATION__
|
||||
#include <rtems/rtems/modes.inl>
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -41,9 +41,35 @@ typedef unsigned32 rtems_option;
|
||||
#define RTEMS_EVENT_ALL 0x00000000 /* wait for all events */
|
||||
#define RTEMS_EVENT_ANY 0x00000002 /* wait on any event */
|
||||
|
||||
#ifndef __RTEMS_APPLICATION__
|
||||
/*
|
||||
* _Options_Is_no_wait
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the RTEMS_NO_WAIT option is enabled in
|
||||
* option_set, and FALSE otherwise.
|
||||
*
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Options_Is_no_wait (
|
||||
rtems_option option_set
|
||||
);
|
||||
|
||||
/*
|
||||
* _Options_Is_any
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the RTEMS_EVENT_ANY option is enabled in
|
||||
* OPTION_SET, and FALSE otherwise.
|
||||
*
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Options_Is_any (
|
||||
rtems_option option_set
|
||||
);
|
||||
|
||||
#include <rtems/rtems/options.inl>
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -55,7 +55,7 @@ typedef struct {
|
||||
* manage this class of objects.
|
||||
*/
|
||||
|
||||
RTEMS_EXTERN Objects_Information _Partition_Information;
|
||||
EXTERN Objects_Information _Partition_Information;
|
||||
|
||||
/*
|
||||
* _Partition_Manager_initialization
|
||||
@@ -155,9 +155,132 @@ rtems_status_code rtems_partition_return_buffer(
|
||||
void *buffer
|
||||
);
|
||||
|
||||
#ifndef __RTEMS_APPLICATION__
|
||||
/*
|
||||
* _Partition_Allocate_buffer
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function attempts to allocate a buffer from the_partition.
|
||||
* If successful, it returns the address of the allocated buffer.
|
||||
* Otherwise, it returns NULL.
|
||||
*/
|
||||
|
||||
STATIC INLINE void *_Partition_Allocate_buffer (
|
||||
Partition_Control *the_partition
|
||||
);
|
||||
|
||||
/*
|
||||
* _Partition_Free_buffer
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine frees the_buffer to the_partition.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _Partition_Free_buffer (
|
||||
Partition_Control *the_partition,
|
||||
Chain_Node *the_buffer
|
||||
);
|
||||
|
||||
/*
|
||||
* _Partition_Is_buffer_on_boundary
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_buffer is on a valid buffer
|
||||
* boundary for the_partition, and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Partition_Is_buffer_on_boundary (
|
||||
void *the_buffer,
|
||||
Partition_Control *the_partition
|
||||
);
|
||||
|
||||
/*
|
||||
* _Partition_Is_buffer_valid
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_buffer is a valid buffer from
|
||||
* the_partition, otherwise FALSE is returned.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Partition_Is_buffer_valid (
|
||||
Chain_Node *the_buffer,
|
||||
Partition_Control *the_partition
|
||||
);
|
||||
|
||||
/*
|
||||
* _Partition_Is_buffer_size_aligned
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the use of the specified buffer_size
|
||||
* will result in the allocation of buffers whose first byte is
|
||||
* properly aligned, and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Partition_Is_buffer_size_aligned (
|
||||
unsigned32 buffer_size
|
||||
);
|
||||
|
||||
/*
|
||||
* _Partition_Allocate
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function allocates a partition control block from
|
||||
* the inactive chain of free partition control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE Partition_Control *_Partition_Allocate ( void );
|
||||
|
||||
/*
|
||||
* _Partition_Free
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine frees a partition control block to the
|
||||
* inactive chain of free partition control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _Partition_Free (
|
||||
Partition_Control *the_partition
|
||||
);
|
||||
|
||||
/*
|
||||
* _Partition_Get
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function maps partition IDs to partition control blocks.
|
||||
* If ID corresponds to a local partition, then it returns
|
||||
* the_partition control pointer which maps to ID and location
|
||||
* is set to OBJECTS_LOCAL. If the partition ID is global and
|
||||
* resides on a remote node, then location is set to OBJECTS_REMOTE,
|
||||
* and the_partition is undefined. Otherwise, location is set
|
||||
* to OBJECTS_ERROR and the_partition is undefined.
|
||||
*/
|
||||
|
||||
STATIC INLINE Partition_Control *_Partition_Get (
|
||||
Objects_Id id,
|
||||
Objects_Locations *location
|
||||
);
|
||||
|
||||
/*
|
||||
* _Partition_Is_null
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_partition is NULL
|
||||
* and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Partition_Is_null (
|
||||
Partition_Control *the_partition
|
||||
);
|
||||
|
||||
#include <rtems/rtems/part.inl>
|
||||
#endif
|
||||
#include <rtems/rtems/partmp.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -67,7 +67,7 @@ typedef struct {
|
||||
Thread_Control *owner;
|
||||
} Rate_monotonic_Control;
|
||||
|
||||
RTEMS_EXTERN Objects_Information _Rate_monotonic_Information;
|
||||
EXTERN Objects_Information _Rate_monotonic_Information;
|
||||
|
||||
/*
|
||||
* _Rate_monotonic_Manager_initialization
|
||||
@@ -155,6 +155,47 @@ rtems_status_code rtems_rate_monotonic_period(
|
||||
rtems_interval length
|
||||
);
|
||||
|
||||
/*
|
||||
* _Rate_monotonic_Allocate
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function allocates a period control block from
|
||||
* the inactive chain of free period control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE Rate_monotonic_Control *_Rate_monotonic_Allocate( void );
|
||||
|
||||
/*
|
||||
* _Rate_monotonic_Free
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine allocates a period control block from
|
||||
* the inactive chain of free period control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _Rate_monotonic_Free (
|
||||
Rate_monotonic_Control *the_period
|
||||
);
|
||||
|
||||
/*
|
||||
* _Rate_monotonic_Get
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function maps period IDs to period control blocks.
|
||||
* If ID corresponds to a local period, then it returns
|
||||
* the_period control pointer which maps to ID and location
|
||||
* is set to OBJECTS_LOCAL. Otherwise, location is set
|
||||
* to OBJECTS_ERROR and the_period is undefined.
|
||||
*/
|
||||
|
||||
STATIC INLINE Rate_monotonic_Control *_Rate_monotonic_Get (
|
||||
Objects_Id id,
|
||||
Objects_Locations *location
|
||||
);
|
||||
|
||||
/*
|
||||
* _Rate_monotonic_Timeout
|
||||
*
|
||||
@@ -173,9 +214,58 @@ void _Rate_monotonic_Timeout (
|
||||
void *ignored
|
||||
);
|
||||
|
||||
#ifndef __RTEMS_APPLICATION__
|
||||
/*
|
||||
* _Rate_monotonic_Is_active
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_period is in the ACTIVE state,
|
||||
* and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Rate_monotonic_Is_active (
|
||||
Rate_monotonic_Control *the_period
|
||||
);
|
||||
|
||||
/*
|
||||
* _Rate_monotonic_Is_inactive
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_period is in the ACTIVE state,
|
||||
* and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Rate_monotonic_Is_inactive (
|
||||
Rate_monotonic_Control *the_period
|
||||
);
|
||||
|
||||
/*
|
||||
* _Rate_monotonic_Is_expired
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_period is in the EXPIRED state,
|
||||
* and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Rate_monotonic_Is_expired (
|
||||
Rate_monotonic_Control *the_period
|
||||
);
|
||||
|
||||
/*
|
||||
* _Rate_monotonic_Is_null
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_period is NULL and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Rate_monotonic_Is_null (
|
||||
Rate_monotonic_Control *the_period
|
||||
);
|
||||
|
||||
#include <rtems/rtems/ratemon.inl>
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -59,7 +59,7 @@ typedef struct {
|
||||
* manage this class of objects.
|
||||
*/
|
||||
|
||||
RTEMS_EXTERN Objects_Information _Region_Information;
|
||||
EXTERN Objects_Information _Region_Information;
|
||||
|
||||
/*
|
||||
* _Region_Manager_initialization
|
||||
@@ -198,9 +198,88 @@ rtems_status_code rtems_region_return_segment(
|
||||
void *segment
|
||||
);
|
||||
|
||||
#ifndef __RTEMS_APPLICATION__
|
||||
/*
|
||||
* _Region_Allocate
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function allocates a region control block from
|
||||
* the inactive chain of free region control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE Region_Control *_Region_Allocate( void );
|
||||
|
||||
/*
|
||||
* _Region_Free
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine frees a region control block to the
|
||||
* inactive chain of free region control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _Region_Free (
|
||||
Region_Control *the_region
|
||||
);
|
||||
|
||||
/*
|
||||
* _Region_Get
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function maps region IDs to region control blocks.
|
||||
* If ID corresponds to a local region, then it returns
|
||||
* the_region control pointer which maps to ID and location
|
||||
* is set to OBJECTS_LOCAL. Otherwise, location is set
|
||||
* to OBJECTS_ERROR and the_region is undefined.
|
||||
*/
|
||||
|
||||
STATIC INLINE Region_Control *_Region_Get (
|
||||
Objects_Id id,
|
||||
Objects_Locations *location
|
||||
);
|
||||
|
||||
/*
|
||||
* _Region_Allocate_segment
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function attempts to allocate a segment from the_region.
|
||||
* If successful, it returns the address of the allocated segment.
|
||||
* Otherwise, it returns NULL.
|
||||
*/
|
||||
|
||||
STATIC INLINE void *_Region_Allocate_segment (
|
||||
Region_Control *the_region,
|
||||
unsigned32 size
|
||||
);
|
||||
|
||||
/*
|
||||
* _Region_Free_segment
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function frees the_segment to the_region.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Region_Free_segment (
|
||||
Region_Control *the_region,
|
||||
void *the_segment
|
||||
);
|
||||
|
||||
/*
|
||||
* _Region_Is_null
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_region is NULL and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Region_Is_null (
|
||||
Region_Control *the_region
|
||||
);
|
||||
|
||||
#include <rtems/rtems/region.inl>
|
||||
#endif
|
||||
#include <rtems/rtems/regionmp.h>
|
||||
|
||||
/*
|
||||
|
||||
@@ -23,18 +23,6 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Unless told otherwise, the RTEMS include files will hide some stuff
|
||||
* from normal application code. Defining this crosses a boundary which
|
||||
* is undesirable since it means your application is using RTEMS features
|
||||
* which are not included in the formally defined and supported API.
|
||||
* Define this at your own risk.
|
||||
*/
|
||||
|
||||
#ifndef __RTEMS_VIOLATE_KERNEL_VISIBILITY__
|
||||
#define __RTEMS_APPLICATION__
|
||||
#endif
|
||||
|
||||
#include <rtems/system.h>
|
||||
#include <rtems/rtems/status.h>
|
||||
#include <rtems/rtems/types.h>
|
||||
|
||||
@@ -58,7 +58,7 @@ typedef struct {
|
||||
* this class of objects.
|
||||
*/
|
||||
|
||||
RTEMS_EXTERN Objects_Information _Semaphore_Information;
|
||||
EXTERN Objects_Information _Semaphore_Information;
|
||||
|
||||
/*
|
||||
* _Semaphore_Manager_initialization
|
||||
@@ -177,6 +177,61 @@ boolean _Semaphore_Seize(
|
||||
unsigned32 option_set
|
||||
);
|
||||
|
||||
/*
|
||||
* _Semaphore_Allocate
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function allocates a semaphore control block from
|
||||
* the inactive chain of free semaphore control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE Semaphore_Control *_Semaphore_Allocate( void );
|
||||
|
||||
/*
|
||||
* _Semaphore_Free
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine frees a semaphore control block to the
|
||||
* inactive chain of free semaphore control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _Semaphore_Free (
|
||||
Semaphore_Control *the_semaphore
|
||||
);
|
||||
|
||||
/*
|
||||
* _Semaphore_Get
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function maps semaphore IDs to semaphore control blocks.
|
||||
* If ID corresponds to a local semaphore, then it returns
|
||||
* the_semaphore control pointer which maps to ID and location
|
||||
* is set to OBJECTS_LOCAL. if the semaphore ID is global and
|
||||
* resides on a remote node, then location is set to OBJECTS_REMOTE,
|
||||
* and the_semaphore is undefined. Otherwise, location is set
|
||||
* to OBJECTS_ERROR and the_semaphore is undefined.
|
||||
*/
|
||||
|
||||
STATIC INLINE Semaphore_Control *_Semaphore_Get (
|
||||
rtems_id id,
|
||||
Objects_Locations *location
|
||||
);
|
||||
|
||||
/*
|
||||
* _Semaphore_Is_null
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_semaphore is NULL and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Semaphore_Is_null (
|
||||
Semaphore_Control *the_semaphore
|
||||
);
|
||||
|
||||
/*
|
||||
* _Semaphore_Translate_core_mutex_return_code
|
||||
*
|
||||
@@ -235,9 +290,7 @@ void _Semaphore_Core_semaphore_mp_support (
|
||||
rtems_id id
|
||||
);
|
||||
|
||||
#ifndef __RTEMS_APPLICATION__
|
||||
#include <rtems/rtems/sem.inl>
|
||||
#endif
|
||||
#include <rtems/rtems/semmp.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -60,7 +60,7 @@ typedef enum {
|
||||
|
||||
extern rtems_status_code _Status_Object_name_errors_to_status[];
|
||||
|
||||
#ifdef RTEMS_API_INIT
|
||||
#ifdef INIT
|
||||
rtems_status_code _Status_Object_name_errors_to_status[] = {
|
||||
RTEMS_SUCCESSFUL, /* OBJECTS_SUCCESSFUL */
|
||||
RTEMS_INVALID_NAME, /* OBJECTS_INVALID_NAME */
|
||||
@@ -69,9 +69,32 @@ rtems_status_code _Status_Object_name_errors_to_status[] = {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Applications are allowed to use the macros to compare status codes.
|
||||
* rtems_is_status_successful
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the status code is equal to RTEMS_SUCCESSFUL,
|
||||
* and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean rtems_is_status_successful (
|
||||
rtems_status_code code
|
||||
);
|
||||
|
||||
/*
|
||||
* rtems_are_statuses_equal
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the status code1 is equal to code2,
|
||||
* and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean rtems_are_statuses_equal (
|
||||
rtems_status_code code1,
|
||||
rtems_status_code code2
|
||||
);
|
||||
|
||||
#include <rtems/rtems/status.inl>
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -23,6 +23,18 @@ extern "C" {
|
||||
|
||||
#include <rtems/rtems/types.h>
|
||||
|
||||
/*
|
||||
* rtems_is_name_valid
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the name is valid, and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE rtems_boolean rtems_is_name_valid (
|
||||
rtems_name name
|
||||
);
|
||||
|
||||
/*
|
||||
* rtems_build_name
|
||||
*
|
||||
@@ -40,6 +52,24 @@ extern "C" {
|
||||
#define rtems_build_name( _C1, _C2, _C3, _C4 ) \
|
||||
( (_C1) << 24 | (_C2) << 16 | (_C3) << 8 | (_C4) )
|
||||
|
||||
/*
|
||||
* rtems_name_to_characters
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function breaks the object name into the four component
|
||||
* characters C1, C2, C3, and C4.
|
||||
*
|
||||
*/
|
||||
|
||||
STATIC INLINE void rtems_name_to_characters(
|
||||
rtems_name name,
|
||||
char *c1,
|
||||
char *c2,
|
||||
char *c3,
|
||||
char *c4
|
||||
);
|
||||
|
||||
/*
|
||||
* rtems_get_class
|
||||
*
|
||||
@@ -85,9 +115,7 @@ extern "C" {
|
||||
#define RTEMS_MILLISECONDS_TO_TICKS(_ms) \
|
||||
TOD_MILLISECONDS_TO_TICKS(_ms)
|
||||
|
||||
#ifndef __RTEMS_APPLICATION__
|
||||
#include <rtems/rtems/support.inl>
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -45,7 +45,6 @@ extern "C" {
|
||||
#include <rtems/rtems/eventset.h>
|
||||
#include <rtems/rtems/asr.h>
|
||||
#include <rtems/rtems/attr.h>
|
||||
#include <rtems/rtems/status.h>
|
||||
|
||||
/*
|
||||
* Constant to be used as the ID of current task
|
||||
@@ -164,15 +163,14 @@ typedef struct {
|
||||
* manage this class of objects.
|
||||
*/
|
||||
|
||||
RTEMS_EXTERN Objects_Information _RTEMS_tasks_Information;
|
||||
EXTERN Objects_Information _RTEMS_tasks_Information;
|
||||
|
||||
/*
|
||||
* These are used to manage the user initialization tasks.
|
||||
*/
|
||||
|
||||
RTEMS_EXTERN rtems_initialization_tasks_table
|
||||
*_RTEMS_tasks_User_initialization_tasks;
|
||||
RTEMS_EXTERN unsigned32 _RTEMS_tasks_Number_of_initialization_tasks;
|
||||
EXTERN rtems_initialization_tasks_table *_RTEMS_tasks_User_initialization_tasks;
|
||||
EXTERN unsigned32 _RTEMS_tasks_Number_of_initialization_tasks;
|
||||
|
||||
/*
|
||||
* _RTEMS_tasks_Manager_initialization
|
||||
@@ -394,6 +392,43 @@ rtems_status_code rtems_task_wake_after(
|
||||
rtems_interval ticks
|
||||
);
|
||||
|
||||
/*
|
||||
* _RTEMS_tasks_Allocate
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function allocates a task control block from
|
||||
* the inactive chain of free task control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE Thread_Control *_RTEMS_tasks_Allocate( void );
|
||||
|
||||
/*
|
||||
* _RTEMS_tasks_Free
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine frees a task control block to the
|
||||
* inactive chain of free task control blocks.
|
||||
|
||||
*/
|
||||
|
||||
STATIC INLINE void _RTEMS_tasks_Free (
|
||||
Thread_Control *the_task
|
||||
);
|
||||
|
||||
/*
|
||||
* _RTEMS_tasks_Priority_to_Core
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function converts an RTEMS API priority into a core priority.
|
||||
*/
|
||||
|
||||
STATIC INLINE Priority_Control _RTEMS_tasks_Priority_to_Core(
|
||||
rtems_task_priority priority
|
||||
);
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* _RTEMS_tasks_Initialize_user_tasks
|
||||
@@ -408,9 +443,17 @@ rtems_status_code rtems_task_wake_after(
|
||||
|
||||
void _RTEMS_tasks_Initialize_user_tasks( void );
|
||||
|
||||
#ifndef __RTEMS_APPLICATION__
|
||||
/*PAGE
|
||||
*
|
||||
* _RTEMS_tasks_Priority_is_valid
|
||||
*
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _RTEMS_tasks_Priority_is_valid (
|
||||
rtems_task_priority the_priority
|
||||
);
|
||||
|
||||
#include <rtems/rtems/tasks.inl>
|
||||
#endif
|
||||
#include <rtems/rtems/taskmp.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -64,7 +64,7 @@ typedef rtems_timer_service_routine ( *rtems_timer_service_routine_entry )(
|
||||
* this class of objects.
|
||||
*/
|
||||
|
||||
RTEMS_EXTERN Objects_Information _Timer_Information;
|
||||
EXTERN Objects_Information _Timer_Information;
|
||||
|
||||
/*
|
||||
* The following records define the control block used to manage
|
||||
@@ -195,9 +195,99 @@ rtems_status_code rtems_timer_reset(
|
||||
Objects_Id id
|
||||
);
|
||||
|
||||
#ifndef __RTEMS_APPLICATION__
|
||||
/*
|
||||
* _Timer_Allocate
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function allocates a timer control block from
|
||||
* the inactive chain of free timer control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE Timer_Control *_Timer_Allocate( void );
|
||||
|
||||
/*
|
||||
* _Timer_Free
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine frees a timer control block to the
|
||||
* inactive chain of free timer control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _Timer_Free (
|
||||
Timer_Control *the_timer
|
||||
);
|
||||
|
||||
/*
|
||||
* _Timer_Get
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function maps timer IDs to timer control blocks.
|
||||
* If ID corresponds to a local timer, then it returns
|
||||
* the timer control pointer which maps to ID and location
|
||||
* is set to OBJECTS_LOCAL. Otherwise, location is set
|
||||
* to OBJECTS_ERROR and the returned value is undefined.
|
||||
*/
|
||||
|
||||
STATIC INLINE Timer_Control *_Timer_Get (
|
||||
Objects_Id id,
|
||||
Objects_Locations *location
|
||||
);
|
||||
|
||||
/*
|
||||
* _Timer_Is_interval_class
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the class is that of an INTERVAL
|
||||
* timer, and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Timer_Is_interval_class (
|
||||
Timer_Classes the_class
|
||||
);
|
||||
|
||||
/*
|
||||
* _Timer_Is_time_of_day_class
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the class is that of an INTERVAL
|
||||
* timer, and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Timer_Is_timer_of_day_class (
|
||||
Timer_Classes the_class
|
||||
);
|
||||
|
||||
/*
|
||||
* _Timer_Is_dormant_class
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the class is that of a DORMANT
|
||||
* timer, and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Timer_Is_dormant_class (
|
||||
Timer_Classes the_class
|
||||
);
|
||||
|
||||
/*
|
||||
* _Timer_Is_null
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_timer is NULL and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Timer_Is_null (
|
||||
Timer_Control *the_timer
|
||||
);
|
||||
|
||||
#include <rtems/rtems/timer.inl>
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -23,9 +23,6 @@
|
||||
*
|
||||
* _ASR_Initialize
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine initializes the given RTEMS_ASR information record.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _ASR_Initialize (
|
||||
@@ -44,11 +41,6 @@ STATIC INLINE void _ASR_Initialize (
|
||||
*
|
||||
* _ASR_Swap_signals
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine atomically swaps the pending and posted signal
|
||||
* sets. This is done when the thread alters its mode in such a
|
||||
* way that the RTEMS_ASR disable/enable flag changes.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _ASR_Swap_signals (
|
||||
@@ -69,10 +61,6 @@ STATIC INLINE void _ASR_Swap_signals (
|
||||
*
|
||||
* _ASR_Is_null_handler
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the given asr_handler is NULL and
|
||||
* FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _ASR_Is_null_handler (
|
||||
@@ -86,10 +74,6 @@ STATIC INLINE boolean _ASR_Is_null_handler (
|
||||
*
|
||||
* _ASR_Are_signals_pending
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if there are signals pending in the
|
||||
* given RTEMS_ASR information record and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _ASR_Are_signals_pending (
|
||||
@@ -103,12 +87,6 @@ STATIC INLINE boolean _ASR_Are_signals_pending (
|
||||
*
|
||||
* _ASR_Post_signals
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine posts the given signals into the signal_set
|
||||
* passed in. The result is returned to the user in signal_set.
|
||||
*
|
||||
* NOTE: This must be implemented as a macro.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _ASR_Post_signals(
|
||||
|
||||
@@ -20,11 +20,6 @@
|
||||
/*PAGE
|
||||
*
|
||||
* _Attributes_Set
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function sets the requested new_attributes in the attribute_set
|
||||
* passed in. The result is returned to the user.
|
||||
*/
|
||||
|
||||
STATIC INLINE rtems_attribute _Attributes_Set (
|
||||
@@ -38,11 +33,6 @@ STATIC INLINE rtems_attribute _Attributes_Set (
|
||||
/*PAGE
|
||||
*
|
||||
* _Attributes_Clear
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function clears the requested new_attributes in the attribute_set
|
||||
* passed in. The result is returned to the user.
|
||||
*/
|
||||
|
||||
STATIC INLINE rtems_attribute _Attributes_Clear (
|
||||
@@ -57,10 +47,6 @@ STATIC INLINE rtems_attribute _Attributes_Clear (
|
||||
*
|
||||
* _Attributes_Is_floating_point
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the floating point attribute is
|
||||
* enabled in the attribute_set and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Attributes_Is_floating_point(
|
||||
@@ -74,10 +60,6 @@ STATIC INLINE boolean _Attributes_Is_floating_point(
|
||||
*
|
||||
* _Attributes_Is_global
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the global object attribute is
|
||||
* enabled in the attribute_set and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Attributes_Is_global(
|
||||
@@ -91,10 +73,6 @@ STATIC INLINE boolean _Attributes_Is_global(
|
||||
*
|
||||
* _Attributes_Is_priority
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the priority attribute is
|
||||
* enabled in the attribute_set and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Attributes_Is_priority(
|
||||
@@ -108,10 +86,6 @@ STATIC INLINE boolean _Attributes_Is_priority(
|
||||
*
|
||||
* _Attributes_Is_binary_semaphore
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the binary semaphore attribute is
|
||||
* enabled in the attribute_set and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Attributes_Is_binary_semaphore(
|
||||
@@ -125,10 +99,6 @@ STATIC INLINE boolean _Attributes_Is_binary_semaphore(
|
||||
*
|
||||
* _Attributes_Is_inherit_priority
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the priority inheritance attribute
|
||||
* is enabled in the attribute_set and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Attributes_Is_inherit_priority(
|
||||
@@ -142,10 +112,6 @@ STATIC INLINE boolean _Attributes_Is_inherit_priority(
|
||||
*
|
||||
* _Attributes_Is_priority_ceiling
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the priority ceiling attribute
|
||||
* is enabled in the attribute_set and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Attributes_Is_priority_ceiling(
|
||||
|
||||
@@ -22,10 +22,6 @@
|
||||
*
|
||||
* _Dual_ported_memory_Allocate
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine allocates a port control block from the inactive chain
|
||||
* of free port control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE Dual_ported_memory_Control
|
||||
@@ -39,10 +35,6 @@ STATIC INLINE Dual_ported_memory_Control
|
||||
*
|
||||
* _Dual_ported_memory_Free
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine frees a port control block to the inactive chain
|
||||
* of free port control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _Dual_ported_memory_Free (
|
||||
@@ -56,14 +48,6 @@ STATIC INLINE void _Dual_ported_memory_Free (
|
||||
*
|
||||
* _Dual_ported_memory_Get
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function maps port IDs to port control blocks. If ID
|
||||
* corresponds to a local port, then it returns the_port control
|
||||
* pointer which maps to ID and location is set to OBJECTS_LOCAL.
|
||||
* Global ports are not supported, thus if ID does not map to a
|
||||
* local port, location is set to OBJECTS_ERROR and the_port is
|
||||
* undefined.
|
||||
*/
|
||||
|
||||
STATIC INLINE Dual_ported_memory_Control *_Dual_ported_memory_Get (
|
||||
@@ -78,10 +62,6 @@ STATIC INLINE Dual_ported_memory_Control *_Dual_ported_memory_Get (
|
||||
/*PAGE
|
||||
*
|
||||
* _Dual_ported_memory_Is_null
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_port is NULL and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Dual_ported_memory_Is_null(
|
||||
|
||||
@@ -17,5 +17,20 @@
|
||||
#ifndef __MACROS_EVENT_inl
|
||||
#define __MACROS_EVENT_inl
|
||||
|
||||
/*
|
||||
* Event_Manager_initialization
|
||||
*/
|
||||
|
||||
STATIC INLINE void _Event_Manager_initialization( void )
|
||||
{
|
||||
_Event_Sync = FALSE;
|
||||
|
||||
/*
|
||||
* Register the MP Process Packet routine.
|
||||
*/
|
||||
|
||||
_MPCI_Register_packet_processor( MP_PACKET_EVENT, _Event_MP_Process_packet );
|
||||
}
|
||||
|
||||
#endif
|
||||
/* end of include file */
|
||||
|
||||
@@ -19,11 +19,6 @@
|
||||
/*PAGE
|
||||
*
|
||||
* _Event_sets_Is_empty
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if on events are posted in the event_set,
|
||||
* and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Event_sets_Is_empty(
|
||||
@@ -36,11 +31,6 @@ STATIC INLINE boolean _Event_sets_Is_empty(
|
||||
/*PAGE
|
||||
*
|
||||
* _Event_sets_Post
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine posts the given new_events into the event_set
|
||||
* passed in. The result is returned to the user in event_set.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _Event_sets_Post(
|
||||
@@ -54,11 +44,6 @@ STATIC INLINE void _Event_sets_Post(
|
||||
/*PAGE
|
||||
*
|
||||
* _Event_sets_Get
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns the events in event_condition which are
|
||||
* set in event_set.
|
||||
*/
|
||||
|
||||
STATIC INLINE rtems_event_set _Event_sets_Get(
|
||||
@@ -72,11 +57,6 @@ STATIC INLINE rtems_event_set _Event_sets_Get(
|
||||
/*PAGE
|
||||
*
|
||||
* _Event_sets_Clear
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function removes the events in mask from the event_set
|
||||
* passed in. The result is returned to the user in event_set.
|
||||
*/
|
||||
|
||||
STATIC INLINE rtems_event_set _Event_sets_Clear(
|
||||
|
||||
@@ -23,10 +23,6 @@
|
||||
*
|
||||
* _Message_queue_Is_null
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function places the_message at the rear of the outstanding
|
||||
* messages on the_message_queue.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Message_queue_Is_null (
|
||||
@@ -41,10 +37,6 @@ STATIC INLINE boolean _Message_queue_Is_null (
|
||||
*
|
||||
* _Message_queue_Free
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine deallocates a message queue control block into
|
||||
* the inactive chain of free message queue control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _Message_queue_Free (
|
||||
@@ -58,16 +50,6 @@ STATIC INLINE void _Message_queue_Free (
|
||||
*
|
||||
* _Message_queue_Get
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function maps message queue IDs to message queue control
|
||||
* blocks. If ID corresponds to a local message queue, then it
|
||||
* returns the_message_queue control pointer which maps to ID
|
||||
* and location is set to OBJECTS_LOCAL. If the message queue ID is
|
||||
* global and resides on a remote node, then location is set
|
||||
* to OBJECTS_REMOTE, and the_message_queue is undefined.
|
||||
* Otherwise, location is set to OBJECTS_ERROR and
|
||||
* the_message_queue is undefined.
|
||||
*/
|
||||
|
||||
STATIC INLINE Message_queue_Control *_Message_queue_Get (
|
||||
|
||||
@@ -17,14 +17,22 @@
|
||||
#ifndef __MODES_inl
|
||||
#define __MODES_inl
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* RTEMS_INTERRUPT_LEVEL
|
||||
*/
|
||||
|
||||
STATIC INLINE unsigned32 RTEMS_INTERRUPT_LEVEL (
|
||||
Modes_Control mode_set
|
||||
)
|
||||
{
|
||||
return mode_set & RTEMS_INTERRUPT_MASK;
|
||||
}
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* _Modes_Mask_changed
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if any of the mode flags in mask
|
||||
* are set in mode_set, and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Modes_Mask_changed (
|
||||
@@ -39,10 +47,6 @@ STATIC INLINE boolean _Modes_Mask_changed (
|
||||
*
|
||||
* _Modes_Is_asr_disabled
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if mode_set indicates that Asynchronous
|
||||
* Signal Processing is disabled, and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Modes_Is_asr_disabled (
|
||||
@@ -56,10 +60,6 @@ STATIC INLINE boolean _Modes_Is_asr_disabled (
|
||||
*
|
||||
* _Modes_Is_preempt
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if mode_set indicates that preemption
|
||||
* is enabled, and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Modes_Is_preempt (
|
||||
@@ -73,10 +73,6 @@ STATIC INLINE boolean _Modes_Is_preempt (
|
||||
*
|
||||
* _Modes_Is_timeslice
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if mode_set indicates that timeslicing
|
||||
* is enabled, and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Modes_Is_timeslice (
|
||||
@@ -90,9 +86,6 @@ STATIC INLINE boolean _Modes_Is_timeslice (
|
||||
*
|
||||
* _Modes_Get_interrupt_level
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns the interrupt level portion of the mode_set.
|
||||
*/
|
||||
|
||||
STATIC INLINE ISR_Level _Modes_Get_interrupt_level (
|
||||
@@ -106,10 +99,6 @@ STATIC INLINE ISR_Level _Modes_Get_interrupt_level (
|
||||
*
|
||||
* _Modes_Set_interrupt_level
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine sets the current interrupt level to that specified
|
||||
* in the mode_set.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _Modes_Set_interrupt_level (
|
||||
@@ -123,12 +112,6 @@ STATIC INLINE void _Modes_Set_interrupt_level (
|
||||
*
|
||||
* _Modes_Change
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine changes the modes in old_mode_set indicated by
|
||||
* mask to the requested values in new_mode_set. The resulting
|
||||
* mode set is returned in out_mode_set and the modes that changed
|
||||
* is returned in changed.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _Modes_Change (
|
||||
|
||||
@@ -21,10 +21,6 @@
|
||||
*
|
||||
* _Options_Is_no_wait
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the RTEMS_NO_WAIT option is enabled in
|
||||
* option_set, and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Options_Is_no_wait (
|
||||
@@ -38,10 +34,6 @@ STATIC INLINE boolean _Options_Is_no_wait (
|
||||
*
|
||||
* _Options_Is_any
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the RTEMS_EVENT_ANY option is enabled in
|
||||
* OPTION_SET, and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Options_Is_any (
|
||||
|
||||
@@ -21,11 +21,6 @@
|
||||
*
|
||||
* _Partition_Allocate_buffer
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function attempts to allocate a buffer from the_partition.
|
||||
* If successful, it returns the address of the allocated buffer.
|
||||
* Otherwise, it returns NULL.
|
||||
*/
|
||||
|
||||
STATIC INLINE void *_Partition_Allocate_buffer (
|
||||
@@ -39,9 +34,6 @@ STATIC INLINE void *_Partition_Allocate_buffer (
|
||||
*
|
||||
* _Partition_Free_buffer
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine frees the_buffer to the_partition.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _Partition_Free_buffer (
|
||||
@@ -56,10 +48,6 @@ STATIC INLINE void _Partition_Free_buffer (
|
||||
*
|
||||
* _Partition_Is_buffer_on_boundary
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_buffer is on a valid buffer
|
||||
* boundary for the_partition, and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Partition_Is_buffer_on_boundary (
|
||||
@@ -81,10 +69,6 @@ STATIC INLINE boolean _Partition_Is_buffer_on_boundary (
|
||||
*
|
||||
* _Partition_Is_buffer_valid
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_buffer is a valid buffer from
|
||||
* the_partition, otherwise FALSE is returned.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Partition_Is_buffer_valid (
|
||||
@@ -108,11 +92,6 @@ STATIC INLINE boolean _Partition_Is_buffer_valid (
|
||||
*
|
||||
* _Partition_Is_buffer_size_aligned
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the use of the specified buffer_size
|
||||
* will result in the allocation of buffers whose first byte is
|
||||
* properly aligned, and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Partition_Is_buffer_size_aligned (
|
||||
@@ -126,10 +105,6 @@ STATIC INLINE boolean _Partition_Is_buffer_size_aligned (
|
||||
*
|
||||
* _Partition_Allocate
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function allocates a partition control block from
|
||||
* the inactive chain of free partition control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE Partition_Control *_Partition_Allocate ( void )
|
||||
@@ -141,10 +116,6 @@ STATIC INLINE Partition_Control *_Partition_Allocate ( void )
|
||||
*
|
||||
* _Partition_Free
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine frees a partition control block to the
|
||||
* inactive chain of free partition control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _Partition_Free (
|
||||
@@ -158,15 +129,6 @@ STATIC INLINE void _Partition_Free (
|
||||
*
|
||||
* _Partition_Get
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function maps partition IDs to partition control blocks.
|
||||
* If ID corresponds to a local partition, then it returns
|
||||
* the_partition control pointer which maps to ID and location
|
||||
* is set to OBJECTS_LOCAL. If the partition ID is global and
|
||||
* resides on a remote node, then location is set to OBJECTS_REMOTE,
|
||||
* and the_partition is undefined. Otherwise, location is set
|
||||
* to OBJECTS_ERROR and the_partition is undefined.
|
||||
*/
|
||||
|
||||
STATIC INLINE Partition_Control *_Partition_Get (
|
||||
@@ -182,10 +144,6 @@ STATIC INLINE Partition_Control *_Partition_Get (
|
||||
*
|
||||
* _Partition_Is_null
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_partition is NULL
|
||||
* and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Partition_Is_null (
|
||||
|
||||
@@ -21,10 +21,6 @@
|
||||
*
|
||||
* _Rate_monotonic_Allocate
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function allocates a period control block from
|
||||
* the inactive chain of free period control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE Rate_monotonic_Control *_Rate_monotonic_Allocate( void )
|
||||
@@ -37,10 +33,6 @@ STATIC INLINE Rate_monotonic_Control *_Rate_monotonic_Allocate( void )
|
||||
*
|
||||
* _Rate_monotonic_Free
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine allocates a period control block from
|
||||
* the inactive chain of free period control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _Rate_monotonic_Free (
|
||||
@@ -54,13 +46,6 @@ STATIC INLINE void _Rate_monotonic_Free (
|
||||
*
|
||||
* _Rate_monotonic_Get
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function maps period IDs to period control blocks.
|
||||
* If ID corresponds to a local period, then it returns
|
||||
* the_period control pointer which maps to ID and location
|
||||
* is set to OBJECTS_LOCAL. Otherwise, location is set
|
||||
* to OBJECTS_ERROR and the_period is undefined.
|
||||
*/
|
||||
|
||||
STATIC INLINE Rate_monotonic_Control *_Rate_monotonic_Get (
|
||||
@@ -76,10 +61,6 @@ STATIC INLINE Rate_monotonic_Control *_Rate_monotonic_Get (
|
||||
*
|
||||
* _Rate_monotonic_Is_active
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_period is in the ACTIVE state,
|
||||
* and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Rate_monotonic_Is_active (
|
||||
@@ -93,10 +74,6 @@ STATIC INLINE boolean _Rate_monotonic_Is_active (
|
||||
*
|
||||
* _Rate_monotonic_Is_inactive
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_period is in the ACTIVE state,
|
||||
* and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Rate_monotonic_Is_inactive (
|
||||
@@ -110,10 +87,6 @@ STATIC INLINE boolean _Rate_monotonic_Is_inactive (
|
||||
*
|
||||
* _Rate_monotonic_Is_expired
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_period is in the EXPIRED state,
|
||||
* and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Rate_monotonic_Is_expired (
|
||||
@@ -127,9 +100,6 @@ STATIC INLINE boolean _Rate_monotonic_Is_expired (
|
||||
*
|
||||
* _Rate_monotonic_Is_null
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_period is NULL and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Rate_monotonic_Is_null (
|
||||
|
||||
@@ -21,10 +21,6 @@
|
||||
*
|
||||
* _Region_Allocate
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function allocates a region control block from
|
||||
* the inactive chain of free region control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE Region_Control *_Region_Allocate( void )
|
||||
@@ -36,10 +32,6 @@ STATIC INLINE Region_Control *_Region_Allocate( void )
|
||||
*
|
||||
* _Region_Free
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine frees a region control block to the
|
||||
* inactive chain of free region control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _Region_Free (
|
||||
@@ -53,13 +45,6 @@ STATIC INLINE void _Region_Free (
|
||||
*
|
||||
* _Region_Get
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function maps region IDs to region control blocks.
|
||||
* If ID corresponds to a local region, then it returns
|
||||
* the_region control pointer which maps to ID and location
|
||||
* is set to OBJECTS_LOCAL. Otherwise, location is set
|
||||
* to OBJECTS_ERROR and the_region is undefined.
|
||||
*/
|
||||
|
||||
STATIC INLINE Region_Control *_Region_Get (
|
||||
@@ -75,11 +60,6 @@ STATIC INLINE Region_Control *_Region_Get (
|
||||
*
|
||||
* _Region_Allocate_segment
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function attempts to allocate a segment from the_region.
|
||||
* If successful, it returns the address of the allocated segment.
|
||||
* Otherwise, it returns NULL.
|
||||
*/
|
||||
|
||||
STATIC INLINE void *_Region_Allocate_segment (
|
||||
@@ -94,9 +74,6 @@ STATIC INLINE void *_Region_Allocate_segment (
|
||||
*
|
||||
* _Region_Free_segment
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function frees the_segment to the_region.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Region_Free_segment (
|
||||
@@ -111,9 +88,6 @@ STATIC INLINE boolean _Region_Free_segment (
|
||||
*
|
||||
* _Region_Is_null
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_region is NULL and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Region_Is_null (
|
||||
|
||||
@@ -21,10 +21,6 @@
|
||||
*
|
||||
* _Semaphore_Allocate
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function allocates a semaphore control block from
|
||||
* the inactive chain of free semaphore control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE Semaphore_Control *_Semaphore_Allocate( void )
|
||||
@@ -36,10 +32,6 @@ STATIC INLINE Semaphore_Control *_Semaphore_Allocate( void )
|
||||
*
|
||||
* _Semaphore_Free
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine frees a semaphore control block to the
|
||||
* inactive chain of free semaphore control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _Semaphore_Free (
|
||||
@@ -53,15 +45,6 @@ STATIC INLINE void _Semaphore_Free (
|
||||
*
|
||||
* _Semaphore_Get
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function maps semaphore IDs to semaphore control blocks.
|
||||
* If ID corresponds to a local semaphore, then it returns
|
||||
* the_semaphore control pointer which maps to ID and location
|
||||
* is set to OBJECTS_LOCAL. if the semaphore ID is global and
|
||||
* resides on a remote node, then location is set to OBJECTS_REMOTE,
|
||||
* and the_semaphore is undefined. Otherwise, location is set
|
||||
* to OBJECTS_ERROR and the_semaphore is undefined.
|
||||
*/
|
||||
|
||||
STATIC INLINE Semaphore_Control *_Semaphore_Get (
|
||||
@@ -77,9 +60,6 @@ STATIC INLINE Semaphore_Control *_Semaphore_Get (
|
||||
*
|
||||
* _Semaphore_Is_null
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_semaphore is NULL and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Semaphore_Is_null (
|
||||
|
||||
@@ -21,10 +21,6 @@
|
||||
*
|
||||
* rtems_is_status_successful
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the status code is equal to RTEMS_SUCCESSFUL,
|
||||
* and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean rtems_is_status_successful(
|
||||
@@ -38,10 +34,6 @@ STATIC INLINE boolean rtems_is_status_successful(
|
||||
*
|
||||
* rtems_are_statuses_equal
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the status code1 is equal to code2,
|
||||
* and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean rtems_are_statuses_equal(
|
||||
|
||||
@@ -21,9 +21,6 @@
|
||||
*
|
||||
* rtems_is_name_valid
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the name is valid, and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE rtems_boolean rtems_is_name_valid (
|
||||
@@ -37,10 +34,6 @@ STATIC INLINE rtems_boolean rtems_is_name_valid (
|
||||
*
|
||||
* rtems_name_to_characters
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function breaks the object name into the four component
|
||||
* characters C1, C2, C3, and C4.
|
||||
*/
|
||||
|
||||
STATIC INLINE void rtems_name_to_characters(
|
||||
|
||||
@@ -21,10 +21,6 @@
|
||||
*
|
||||
* _RTEMS_tasks_Allocate
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function allocates a task control block from
|
||||
* the inactive chain of free task control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE Thread_Control *_RTEMS_tasks_Allocate( void )
|
||||
@@ -36,10 +32,6 @@ STATIC INLINE Thread_Control *_RTEMS_tasks_Allocate( void )
|
||||
*
|
||||
* _RTEMS_tasks_Free
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine frees a task control block to the
|
||||
* inactive chain of free task control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _RTEMS_tasks_Free (
|
||||
@@ -55,10 +47,6 @@ STATIC INLINE void _RTEMS_tasks_Free (
|
||||
/*PAGE
|
||||
*
|
||||
* _RTEMS_tasks_Priority_to_Core
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function converts an RTEMS API priority into a core priority.
|
||||
*/
|
||||
|
||||
STATIC INLINE Priority_Control _RTEMS_tasks_Priority_to_Core(
|
||||
@@ -72,10 +60,6 @@ STATIC INLINE Priority_Control _RTEMS_tasks_Priority_to_Core(
|
||||
*
|
||||
* _RTEMS_tasks_Priority_is_valid
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_priority is a valid user task priority
|
||||
* and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _RTEMS_tasks_Priority_is_valid (
|
||||
|
||||
@@ -21,10 +21,6 @@
|
||||
*
|
||||
* _Timer_Allocate
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function allocates a timer control block from
|
||||
* the inactive chain of free timer control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE Timer_Control *_Timer_Allocate( void )
|
||||
@@ -36,10 +32,6 @@ STATIC INLINE Timer_Control *_Timer_Allocate( void )
|
||||
*
|
||||
* _Timer_Free
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine frees a timer control block to the
|
||||
* inactive chain of free timer control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _Timer_Free (
|
||||
@@ -53,13 +45,6 @@ STATIC INLINE void _Timer_Free (
|
||||
*
|
||||
* _Timer_Get
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function maps timer IDs to timer control blocks.
|
||||
* If ID corresponds to a local timer, then it returns
|
||||
* the timer control pointer which maps to ID and location
|
||||
* is set to OBJECTS_LOCAL. Otherwise, location is set
|
||||
* to OBJECTS_ERROR and the returned value is undefined.
|
||||
*/
|
||||
|
||||
STATIC INLINE Timer_Control *_Timer_Get (
|
||||
@@ -75,10 +60,6 @@ STATIC INLINE Timer_Control *_Timer_Get (
|
||||
*
|
||||
* _Timer_Is_interval_class
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the class is that of an INTERVAL
|
||||
* timer, and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Timer_Is_interval_class (
|
||||
@@ -92,10 +73,6 @@ STATIC INLINE boolean _Timer_Is_interval_class (
|
||||
*
|
||||
* _Timer_Is_time_of_day_class
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the class is that of an INTERVAL
|
||||
* timer, and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Timer_Is_timer_of_day_class (
|
||||
@@ -109,10 +86,6 @@ STATIC INLINE boolean _Timer_Is_timer_of_day_class (
|
||||
*
|
||||
* _Timer_Is_dormant_class
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the class is that of a DORMANT
|
||||
* timer, and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Timer_Is_dormant_class (
|
||||
@@ -126,9 +99,6 @@ STATIC INLINE boolean _Timer_Is_dormant_class (
|
||||
*
|
||||
* _Timer_Is_null
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_timer is NULL and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Timer_Is_null (
|
||||
|
||||
@@ -17,5 +17,24 @@
|
||||
#ifndef __MACROS_EVENT_h
|
||||
#define __MACROS_EVENT_h
|
||||
|
||||
/*
|
||||
* Event_Manager_initialization
|
||||
*/
|
||||
|
||||
#define _Event_Manager_initialization() \
|
||||
do { \
|
||||
\
|
||||
_Event_Sync = FALSE; \
|
||||
\
|
||||
/* \
|
||||
* Register the MP Process Packet routine. \
|
||||
*/ \
|
||||
\
|
||||
_MPCI_Register_packet_processor( \
|
||||
MP_PACKET_EVENT, \
|
||||
_Event_MP_Process_packet \
|
||||
); \
|
||||
} while ( 0 )
|
||||
|
||||
#endif
|
||||
/* end of include file */
|
||||
|
||||
@@ -17,6 +17,14 @@
|
||||
#ifndef __MODES_inl
|
||||
#define __MODES_inl
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* RTEMS_INTERRUPT_LEVEL
|
||||
*/
|
||||
|
||||
#define RTEMS_INTERRUPT_LEVEL( _mode_set ) \
|
||||
( (_mode_set) & RTEMS_INTERRUPT_MASK )
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* _Modes_Mask_changed
|
||||
|
||||
@@ -16,7 +16,6 @@
|
||||
#include <rtems/score/address.h>
|
||||
#include <rtems/score/object.h>
|
||||
#include <rtems/score/thread.h>
|
||||
#include <rtems/score/interr.h>
|
||||
|
||||
#include <rtems/rtems/status.h>
|
||||
#include <rtems/rtems/types.h>
|
||||
@@ -36,11 +35,6 @@ rtems_status_code rtems_port_create(
|
||||
Objects_Id *id
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -49,11 +43,6 @@ rtems_status_code rtems_port_ident(
|
||||
Objects_Id *id
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -61,11 +50,6 @@ rtems_status_code rtems_port_delete(
|
||||
Objects_Id id
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -75,11 +59,6 @@ rtems_status_code rtems_port_internal_to_external(
|
||||
void **external
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -89,10 +68,5 @@ rtems_status_code rtems_port_external_to_internal(
|
||||
void **internal
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -20,22 +20,12 @@
|
||||
#include <rtems/rtems/options.h>
|
||||
#include <rtems/score/states.h>
|
||||
#include <rtems/score/thread.h>
|
||||
#include <rtems/score/interr.h>
|
||||
|
||||
void _Event_Manager_initialization( void )
|
||||
{
|
||||
}
|
||||
|
||||
rtems_status_code rtems_event_send(
|
||||
Objects_Id id,
|
||||
rtems_event_set event_in
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -46,11 +36,6 @@ rtems_status_code rtems_event_receive(
|
||||
rtems_event_set *event_out
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
|
||||
@@ -26,7 +26,6 @@
|
||||
#include <rtems/score/tqdata.h>
|
||||
#include <rtems/score/watchdog.h>
|
||||
#include <rtems/score/sysstate.h>
|
||||
#include <rtems/score/interr.h>
|
||||
|
||||
void _Multiprocessing_Manager_initialization ( void )
|
||||
{
|
||||
@@ -34,11 +33,6 @@ void _Multiprocessing_Manager_initialization ( void )
|
||||
|
||||
void rtems_multiprocessing_announce ( void )
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
}
|
||||
|
||||
void _MPCI_Handler_initialization(
|
||||
@@ -48,10 +42,6 @@ void _MPCI_Handler_initialization(
|
||||
{
|
||||
}
|
||||
|
||||
void _MPCI_Create_server( void )
|
||||
{
|
||||
}
|
||||
|
||||
void _MPCI_Initialization ( void )
|
||||
{
|
||||
}
|
||||
@@ -66,11 +56,6 @@ void _MPCI_Register_packet_processor(
|
||||
|
||||
MP_packet_Prefix *_MPCI_Get_packet ( void )
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
@@ -78,11 +63,6 @@ void _MPCI_Return_packet (
|
||||
MP_packet_Prefix *the_packet
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
}
|
||||
|
||||
void _MPCI_Send_process_packet (
|
||||
@@ -90,11 +70,6 @@ void _MPCI_Send_process_packet (
|
||||
MP_packet_Prefix *the_packet
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
}
|
||||
|
||||
unsigned32 _MPCI_Send_request_packet (
|
||||
@@ -103,11 +78,6 @@ unsigned32 _MPCI_Send_request_packet (
|
||||
States_Control extra_state
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -116,20 +86,10 @@ void _MPCI_Send_response_packet (
|
||||
MP_packet_Prefix *the_packet
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
}
|
||||
|
||||
MP_packet_Prefix *_MPCI_Receive_packet ( void )
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
@@ -137,65 +97,15 @@ Thread_Control *_MPCI_Process_response (
|
||||
MP_packet_Prefix *the_packet
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
Thread _MPCI_Receive_server(
|
||||
unsigned32 ignore
|
||||
)
|
||||
void _MPCI_Receive_server( void )
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
}
|
||||
|
||||
void _MPCI_Announce ( void )
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
void _MPCI_Internal_packets_Send_process_packet (
|
||||
MPCI_Internal_Remote_operations operation
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
}
|
||||
|
||||
void _MPCI_Internal_packets_Process_packet (
|
||||
MP_packet_Prefix *the_packet_prefix
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
}
|
||||
|
||||
MPCI_Internal_packet *_MPCI_Internal_packets_Get_packet ( void )
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* end of file */
|
||||
|
||||
@@ -24,7 +24,6 @@
|
||||
#include <rtems/score/states.h>
|
||||
#include <rtems/score/thread.h>
|
||||
#include <rtems/score/wkspace.h>
|
||||
#include <rtems/score/interr.h>
|
||||
|
||||
void _Message_queue_Manager_initialization(
|
||||
unsigned32 maximum_message_queues
|
||||
@@ -40,11 +39,6 @@ rtems_status_code rtems_message_queue_create(
|
||||
Objects_Id *id
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -54,11 +48,6 @@ rtems_status_code rtems_message_queue_ident(
|
||||
Objects_Id *id
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -66,11 +55,6 @@ rtems_status_code rtems_message_queue_delete(
|
||||
Objects_Id id
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -80,11 +64,6 @@ rtems_status_code rtems_message_queue_send(
|
||||
unsigned32 size
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -94,11 +73,6 @@ rtems_status_code rtems_message_queue_urgent(
|
||||
unsigned32 size
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -109,11 +83,6 @@ rtems_status_code rtems_message_queue_broadcast(
|
||||
unsigned32 *count
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -125,11 +94,6 @@ rtems_status_code rtems_message_queue_receive(
|
||||
rtems_interval timeout
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -138,11 +102,6 @@ rtems_status_code rtems_message_queue_flush(
|
||||
unsigned32 *count
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -150,12 +109,6 @@ unsigned32 _Message_queue_Flush_support(
|
||||
Message_queue_Control *the_message_queue
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -166,12 +119,6 @@ boolean _Message_queue_Seize(
|
||||
unsigned32 *size_p
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
_Thread_Executing->Wait.return_code = RTEMS_UNSATISFIED;
|
||||
return TRUE;
|
||||
}
|
||||
@@ -183,10 +130,5 @@ rtems_status_code _Message_queue_Submit(
|
||||
Message_queue_Submit_types submit_type
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -19,7 +19,6 @@
|
||||
#include <rtems/score/object.h>
|
||||
#include <rtems/rtems/part.h>
|
||||
#include <rtems/score/thread.h>
|
||||
#include <rtems/score/interr.h>
|
||||
|
||||
void _Partition_Manager_initialization(
|
||||
unsigned32 maximum_partitions
|
||||
@@ -36,11 +35,6 @@ rtems_status_code rtems_partition_create(
|
||||
Objects_Id *id
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -50,11 +44,6 @@ rtems_status_code rtems_partition_ident(
|
||||
Objects_Id *id
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -62,11 +51,6 @@ rtems_status_code rtems_partition_delete(
|
||||
Objects_Id id
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -75,11 +59,6 @@ rtems_status_code rtems_partition_get_buffer(
|
||||
void **buffer
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -88,10 +67,5 @@ rtems_status_code rtems_partition_return_buffer(
|
||||
void *buffer
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -20,7 +20,6 @@
|
||||
#include <rtems/rtems/region.h>
|
||||
#include <rtems/score/states.h>
|
||||
#include <rtems/score/thread.h>
|
||||
#include <rtems/score/interr.h>
|
||||
|
||||
void _Region_Manager_initialization(
|
||||
unsigned32 maximum_regions
|
||||
@@ -37,11 +36,6 @@ rtems_status_code rtems_region_create(
|
||||
Objects_Id *id
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -50,11 +44,6 @@ rtems_status_code rtems_region_ident(
|
||||
Objects_Id *id
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -62,11 +51,6 @@ rtems_status_code rtems_region_delete(
|
||||
Objects_Id id
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -78,11 +62,6 @@ rtems_status_code rtems_region_get_segment(
|
||||
void **segment
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -92,11 +71,6 @@ rtems_status_code rtems_region_get_segment_size(
|
||||
unsigned32 *size
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -105,10 +79,5 @@ rtems_status_code rtems_region_return_segment(
|
||||
void *segment
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -18,7 +18,6 @@
|
||||
#include <rtems/score/isr.h>
|
||||
#include <rtems/score/object.h>
|
||||
#include <rtems/score/thread.h>
|
||||
#include <rtems/score/interr.h>
|
||||
|
||||
#include <rtems/rtems/types.h>
|
||||
#include <rtems/rtems/ratemon.h>
|
||||
@@ -34,11 +33,6 @@ rtems_status_code rtems_rate_monotonic_create(
|
||||
Objects_Id *id
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -47,11 +41,6 @@ rtems_status_code rtems_rate_monotonic_ident(
|
||||
Objects_Id *id
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -59,11 +48,6 @@ rtems_status_code rtems_rate_monotonic_cancel(
|
||||
Objects_Id id
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -71,11 +55,6 @@ rtems_status_code rtems_rate_monotonic_delete(
|
||||
Objects_Id id
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -84,11 +63,6 @@ rtems_status_code rtems_rate_monotonic_period(
|
||||
rtems_interval length
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -97,21 +71,11 @@ void _Rate_monotonic_Timeout(
|
||||
void *ignored
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
}
|
||||
|
||||
boolean _Rate_monotonic_Set_state(
|
||||
Rate_monotonic_Control *the_period
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return FALSE;
|
||||
return( FALSE );
|
||||
}
|
||||
|
||||
@@ -23,7 +23,6 @@
|
||||
#include <rtems/score/states.h>
|
||||
#include <rtems/score/thread.h>
|
||||
#include <rtems/score/threadq.h>
|
||||
#include <rtems/score/interr.h>
|
||||
|
||||
void _Semaphore_Manager_initialization(
|
||||
unsigned32 maximum_semaphores
|
||||
@@ -39,11 +38,6 @@ rtems_status_code rtems_semaphore_create(
|
||||
Objects_Id *id
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -53,11 +47,6 @@ rtems_status_code rtems_semaphore_ident(
|
||||
Objects_Id *id
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -65,11 +54,6 @@ rtems_status_code rtems_semaphore_delete(
|
||||
Objects_Id id
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -79,11 +63,6 @@ rtems_status_code rtems_semaphore_obtain(
|
||||
rtems_interval timeout
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -91,11 +70,6 @@ rtems_status_code rtems_semaphore_release(
|
||||
Objects_Id id
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -104,11 +78,6 @@ boolean _Semaphore_Seize(
|
||||
rtems_option option_set
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
_Thread_Executing->Wait.return_code = RTEMS_UNSATISFIED;
|
||||
return TRUE;
|
||||
return( TRUE );
|
||||
}
|
||||
|
||||
@@ -17,7 +17,6 @@
|
||||
#include <rtems/rtems/status.h>
|
||||
#include <rtems/score/isr.h>
|
||||
#include <rtems/score/thread.h>
|
||||
#include <rtems/score/interr.h>
|
||||
|
||||
#include <rtems/rtems/asr.h>
|
||||
#include <rtems/rtems/modes.h>
|
||||
@@ -32,11 +31,6 @@ rtems_status_code rtems_signal_catch(
|
||||
rtems_mode mode_set
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -45,11 +39,6 @@ rtems_status_code rtems_signal_send(
|
||||
rtems_signal_set signal_set
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
|
||||
@@ -19,7 +19,6 @@
|
||||
#include <rtems/score/thread.h>
|
||||
#include <rtems/score/tod.h>
|
||||
#include <rtems/score/watchdog.h>
|
||||
#include <rtems/score/interr.h>
|
||||
|
||||
#include <rtems/rtems/types.h>
|
||||
#include <rtems/rtems/timer.h>
|
||||
@@ -35,11 +34,6 @@ rtems_status_code rtems_timer_create(
|
||||
Objects_Id *id
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -48,11 +42,6 @@ rtems_status_code rtems_timer_ident(
|
||||
Objects_Id *id
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -60,11 +49,6 @@ rtems_status_code rtems_timer_cancel(
|
||||
Objects_Id id
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -72,11 +56,6 @@ rtems_status_code rtems_timer_delete(
|
||||
Objects_Id id
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -87,11 +66,6 @@ rtems_status_code rtems_timer_fire_after(
|
||||
void *user_data
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -102,11 +76,6 @@ rtems_status_code rtems_timer_fire_when(
|
||||
void *user_data
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -114,10 +83,5 @@ rtems_status_code rtems_timer_reset(
|
||||
Objects_Id id
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -62,7 +62,7 @@ rtems_status_code rtems_clock_get(
|
||||
return RTEMS_SUCCESSFUL;
|
||||
|
||||
case RTEMS_CLOCK_GET_TICKS_SINCE_BOOT:
|
||||
*(rtems_interval *)time_buffer = _Watchdog_Ticks_since_boot;
|
||||
*(rtems_interval *)time_buffer = _TOD_Ticks_since_boot;
|
||||
return RTEMS_SUCCESSFUL;
|
||||
|
||||
case RTEMS_CLOCK_GET_TICKS_PER_SECOND:
|
||||
|
||||
@@ -22,26 +22,6 @@
|
||||
#include <rtems/score/thread.h>
|
||||
#include <rtems/rtems/tasks.h>
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* _Event_Manager_initialization
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine performs the initialization necessary for this manager.
|
||||
*/
|
||||
|
||||
void _Event_Manager_initialization( void )
|
||||
{
|
||||
_Event_Sync_state = EVENT_SYNC_SYNCHRONIZED;
|
||||
|
||||
/*
|
||||
* Register the MP Process Packet routine.
|
||||
*/
|
||||
|
||||
_MPCI_Register_packet_processor( MP_PACKET_EVENT, _Event_MP_Process_packet );
|
||||
}
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* rtems_event_send
|
||||
@@ -164,7 +144,6 @@ void _Event_Seize(
|
||||
rtems_event_set pending_events;
|
||||
ISR_Level level;
|
||||
RTEMS_API_Control *api;
|
||||
Event_Sync_states sync_state;
|
||||
|
||||
executing = _Thread_Executing;
|
||||
executing->Wait.return_code = RTEMS_SUCCESSFUL;
|
||||
@@ -191,6 +170,7 @@ void _Event_Seize(
|
||||
return;
|
||||
}
|
||||
|
||||
_Event_Sync = TRUE;
|
||||
_Event_Sync_state = EVENT_SYNC_NOTHING_HAPPENED;
|
||||
|
||||
executing->Wait.option = (unsigned32) option_set;
|
||||
@@ -212,28 +192,16 @@ void _Event_Seize(
|
||||
_Thread_Set_state( executing, STATES_WAITING_FOR_EVENT );
|
||||
|
||||
_ISR_Disable( level );
|
||||
|
||||
sync_state = _Event_Sync_state;
|
||||
_Event_Sync_state = EVENT_SYNC_SYNCHRONIZED;
|
||||
|
||||
switch ( sync_state ) {
|
||||
case EVENT_SYNC_SYNCHRONIZED:
|
||||
/*
|
||||
* This cannot happen. It indicates that this routine did not
|
||||
* enter the synchronization states above.
|
||||
*/
|
||||
return;
|
||||
|
||||
switch ( _Event_Sync_state ) {
|
||||
case EVENT_SYNC_NOTHING_HAPPENED:
|
||||
_Event_Sync = FALSE;
|
||||
_ISR_Enable( level );
|
||||
return;
|
||||
|
||||
case EVENT_SYNC_TIMEOUT:
|
||||
executing->Wait.return_code = RTEMS_TIMEOUT;
|
||||
_ISR_Enable( level );
|
||||
_Thread_Unblock( executing );
|
||||
return;
|
||||
|
||||
case EVENT_SYNC_SATISFIED:
|
||||
if ( _Watchdog_Is_active( &executing->Timer ) ) {
|
||||
_Watchdog_Deactivate( &executing->Timer );
|
||||
@@ -306,24 +274,12 @@ void _Event_Surrender(
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
switch ( _Event_Sync_state ) {
|
||||
case EVENT_SYNC_SYNCHRONIZED:
|
||||
case EVENT_SYNC_SATISFIED:
|
||||
break;
|
||||
|
||||
case EVENT_SYNC_NOTHING_HAPPENED:
|
||||
case EVENT_SYNC_TIMEOUT:
|
||||
if ( !_Thread_Is_executing( the_thread ) )
|
||||
break;
|
||||
|
||||
if ( seized_events == event_condition || _Options_Is_any(option_set) ) {
|
||||
api->pending_events =
|
||||
_Event_sets_Clear( pending_events,seized_events );
|
||||
*(rtems_event_set *)the_thread->Wait.return_argument = seized_events;
|
||||
_Event_Sync_state = EVENT_SYNC_SATISFIED;
|
||||
}
|
||||
break;
|
||||
else if ( _Event_Sync == TRUE && _Thread_Is_executing( the_thread ) ) {
|
||||
if ( seized_events == event_condition || _Options_Is_any( option_set ) ) {
|
||||
api->pending_events = _Event_sets_Clear( pending_events,seized_events );
|
||||
*(rtems_event_set *)the_thread->Wait.return_argument = seized_events;
|
||||
_Event_Sync_state = EVENT_SYNC_SATISFIED;
|
||||
}
|
||||
}
|
||||
}
|
||||
_ISR_Enable( level );
|
||||
@@ -356,21 +312,7 @@ void _Event_Timeout(
|
||||
case OBJECTS_REMOTE: /* impossible */
|
||||
break;
|
||||
case OBJECTS_LOCAL:
|
||||
|
||||
/*
|
||||
* If the event manager is not synchronized, then it is either
|
||||
* "nothing happened", "timeout", or "satisfied". If the_thread
|
||||
* is the executing thread, then it is in the process of blocking
|
||||
* and it is the thread which is responsible for the synchronization
|
||||
* process.
|
||||
*
|
||||
* If it is not satisfied, then it is "nothing happened" and
|
||||
* this is the "timeout" transition. After a request is satisfied,
|
||||
* a timeout is not allowed to occur.
|
||||
*/
|
||||
|
||||
if ( _Event_Sync_state != EVENT_SYNC_SYNCHRONIZED &&
|
||||
_Thread_Is_executing( the_thread ) ) {
|
||||
if ( _Event_Sync == TRUE && _Thread_Is_executing( the_thread ) ) {
|
||||
if ( _Event_Sync_state != EVENT_SYNC_SATISFIED )
|
||||
_Event_Sync_state = EVENT_SYNC_TIMEOUT;
|
||||
} else {
|
||||
|
||||
@@ -126,8 +126,7 @@ rtems_status_code rtems_semaphore_create(
|
||||
if ( _Attributes_Is_inherit_priority( attribute_set ) )
|
||||
return RTEMS_NOT_DEFINED;
|
||||
|
||||
} else if ( _Attributes_Is_inherit_priority( attribute_set ) ||
|
||||
_Attributes_Is_priority_ceiling( attribute_set ) ) {
|
||||
} else if ( _Attributes_Is_inherit_priority( attribute_set ) ) {
|
||||
|
||||
if ( ! ( _Attributes_Is_binary_semaphore( attribute_set ) &&
|
||||
_Attributes_Is_priority( attribute_set ) ) )
|
||||
@@ -171,8 +170,6 @@ rtems_status_code rtems_semaphore_create(
|
||||
|
||||
/* Add priority ceiling code here ????? */
|
||||
|
||||
the_mutex_attributes.priority_ceiling = priority_ceiling;
|
||||
|
||||
if ( count == 1 )
|
||||
lock = CORE_MUTEX_UNLOCKED;
|
||||
else
|
||||
@@ -192,13 +189,6 @@ rtems_status_code rtems_semaphore_create(
|
||||
else
|
||||
the_semaphore_attributes.discipline = CORE_SEMAPHORE_DISCIPLINES_FIFO;
|
||||
|
||||
/*
|
||||
* The following are just to make Purify happy.
|
||||
*/
|
||||
|
||||
the_mutex_attributes.allow_nesting = TRUE;
|
||||
the_mutex_attributes.priority_ceiling = PRIORITY_MINIMUM;
|
||||
|
||||
_CORE_semaphore_Initialize(
|
||||
&the_semaphore->Core_control.semaphore,
|
||||
OBJECTS_RTEMS_SEMAPHORES,
|
||||
|
||||
@@ -130,9 +130,6 @@ rtems_status_code rtems_signal_send(
|
||||
if ( ! _ASR_Is_null_handler( asr->handler ) ) {
|
||||
if ( asr->is_enabled ) {
|
||||
_ASR_Post_signals( signal_set, &asr->signals_posted );
|
||||
|
||||
the_thread->do_post_task_switch_extension = TRUE;
|
||||
|
||||
if ( _ISR_Is_in_progress() && _Thread_Is_executing( the_thread ) )
|
||||
_ISR_Signals_to_thread_executing = TRUE;
|
||||
} else {
|
||||
|
||||
@@ -100,7 +100,7 @@ User_extensions_routine _RTEMS_tasks_Delete_extension(
|
||||
* XXX
|
||||
*/
|
||||
|
||||
void _RTEMS_tasks_Switch_extension(
|
||||
User_extensions_routine _RTEMS_tasks_Switch_extension(
|
||||
Thread_Control *executing
|
||||
)
|
||||
{
|
||||
@@ -135,8 +135,7 @@ void _RTEMS_tasks_Switch_extension(
|
||||
API_extensions_Control _RTEMS_tasks_API_extensions = {
|
||||
{ NULL, NULL },
|
||||
NULL, /* predriver */
|
||||
_RTEMS_tasks_Initialize_user_tasks, /* postdriver */
|
||||
_RTEMS_tasks_Switch_extension /* post switch */
|
||||
_RTEMS_tasks_Initialize_user_tasks /* postdriver */
|
||||
};
|
||||
|
||||
User_extensions_Control _RTEMS_tasks_User_extensions = {
|
||||
@@ -146,6 +145,7 @@ User_extensions_Control _RTEMS_tasks_User_extensions = {
|
||||
_RTEMS_tasks_Start_extension, /* restart */
|
||||
_RTEMS_tasks_Delete_extension, /* delete */
|
||||
NULL, /* switch */
|
||||
_RTEMS_tasks_Switch_extension, /* post switch */
|
||||
NULL, /* begin */
|
||||
NULL, /* exitted */
|
||||
NULL /* fatal */
|
||||
@@ -174,14 +174,8 @@ void _RTEMS_tasks_Manager_initialization(
|
||||
_RTEMS_tasks_Number_of_initialization_tasks = number_of_initialization_tasks;
|
||||
_RTEMS_tasks_User_initialization_tasks = user_tasks;
|
||||
|
||||
/*
|
||||
* There may not be any RTEMS initialization tasks configured.
|
||||
*/
|
||||
|
||||
#if 0
|
||||
if ( user_tasks == NULL || number_of_initialization_tasks == 0 )
|
||||
_Internal_error_Occurred( INTERNAL_ERROR_RTEMS_API, TRUE, RTEMS_TOO_MANY );
|
||||
#endif
|
||||
|
||||
_Objects_Initialize_information(
|
||||
&_RTEMS_tasks_Information,
|
||||
@@ -354,10 +348,7 @@ rtems_status_code rtems_task_create(
|
||||
is_fp,
|
||||
core_priority,
|
||||
_Modes_Is_preempt(initial_modes) ? TRUE : FALSE,
|
||||
_Modes_Is_timeslice(initial_modes) ?
|
||||
THREAD_CPU_BUDGET_ALGORITHM_RESET_TIMESLICE :
|
||||
THREAD_CPU_BUDGET_ALGORITHM_NONE,
|
||||
NULL, /* no budget algorithm callout */
|
||||
_Modes_Is_timeslice(initial_modes) ? TRUE : FALSE,
|
||||
_Modes_Get_interrupt_level(initial_modes),
|
||||
&name
|
||||
);
|
||||
@@ -780,12 +771,7 @@ rtems_status_code rtems_task_mode(
|
||||
asr = &api->Signal;
|
||||
|
||||
old_mode = (executing->is_preemptible) ? RTEMS_PREEMPT : RTEMS_NO_PREEMPT;
|
||||
|
||||
if ( executing->budget_algorithm == THREAD_CPU_BUDGET_ALGORITHM_NONE )
|
||||
old_mode |= RTEMS_NO_TIMESLICE;
|
||||
else
|
||||
old_mode |= RTEMS_TIMESLICE;
|
||||
|
||||
old_mode |= (executing->is_timeslice) ? RTEMS_TIMESLICE : RTEMS_NO_TIMESLICE;
|
||||
old_mode |= (asr->is_enabled) ? RTEMS_ASR : RTEMS_NO_ASR;
|
||||
old_mode |= _ISR_Get_level();
|
||||
|
||||
@@ -798,12 +784,8 @@ rtems_status_code rtems_task_mode(
|
||||
if ( mask & RTEMS_PREEMPT_MASK )
|
||||
executing->is_preemptible = _Modes_Is_preempt(mode_set) ? TRUE : FALSE;
|
||||
|
||||
if ( mask & RTEMS_TIMESLICE_MASK ) {
|
||||
if ( _Modes_Is_timeslice(mode_set) )
|
||||
executing->budget_algorithm = THREAD_CPU_BUDGET_ALGORITHM_RESET_TIMESLICE;
|
||||
else
|
||||
executing->budget_algorithm = THREAD_CPU_BUDGET_ALGORITHM_NONE;
|
||||
}
|
||||
if ( mask & RTEMS_TIMESLICE_MASK )
|
||||
executing->is_timeslice = _Modes_Is_timeslice(mode_set) ? TRUE : FALSE;
|
||||
|
||||
/*
|
||||
* Set the new interrupt level
|
||||
@@ -824,10 +806,8 @@ rtems_status_code rtems_task_mode(
|
||||
if ( is_asr_enabled != asr->is_enabled ) {
|
||||
asr->is_enabled = is_asr_enabled;
|
||||
_ASR_Swap_signals( asr );
|
||||
if ( _ASR_Are_signals_pending( asr ) ) {
|
||||
if ( _ASR_Are_signals_pending( asr ) )
|
||||
needs_asr_dispatching = TRUE;
|
||||
executing->do_post_task_switch_extension = TRUE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1090,9 +1070,6 @@ void _RTEMS_tasks_Initialize_user_tasks( void )
|
||||
user_tasks = _RTEMS_tasks_User_initialization_tasks;
|
||||
maximum = _RTEMS_tasks_Number_of_initialization_tasks;
|
||||
|
||||
if ( !user_tasks || maximum == 0 )
|
||||
return;
|
||||
|
||||
for ( index=0 ; index < maximum ; index++ ) {
|
||||
return_value = rtems_task_create(
|
||||
user_tasks[ index ].name,
|
||||
|
||||
@@ -21,29 +21,12 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* This is kind of kludgy but it allows targets to totally ignore the
|
||||
* POSIX API safely.
|
||||
*/
|
||||
|
||||
#ifdef RTEMS_POSIX_API
|
||||
#include <rtems/posix/config.h>
|
||||
#else
|
||||
|
||||
typedef void *posix_api_configuration_table;
|
||||
#endif
|
||||
|
||||
#include <rtems/rtems/config.h>
|
||||
|
||||
/* XXX <rtems/rtems/config.h> should cover these
|
||||
#include <rtems/rtems/status.h>
|
||||
#include <rtems/rtems/types.h>
|
||||
#include <rtems/rtems/tasks.h>
|
||||
*/
|
||||
|
||||
#include <rtems/extension.h>
|
||||
#include <rtems/io.h>
|
||||
#include <rtems/score/mpci.h>
|
||||
#include <rtems/rtems/types.h>
|
||||
#include <rtems/rtems/tasks.h>
|
||||
|
||||
/*
|
||||
* The following records define the Multiprocessor Configuration
|
||||
@@ -67,24 +50,32 @@ typedef struct {
|
||||
* table primarily defines the following:
|
||||
*
|
||||
* + location and size of the RTEMS Workspace
|
||||
* + required number of each object type
|
||||
* + microseconds per clock tick
|
||||
* + clock ticks per task timeslice
|
||||
* + required number of each object type for each API configured
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
void *work_space_start;
|
||||
unsigned32 work_space_size;
|
||||
unsigned32 maximum_tasks;
|
||||
unsigned32 maximum_timers;
|
||||
unsigned32 maximum_semaphores;
|
||||
unsigned32 maximum_message_queues;
|
||||
unsigned32 maximum_partitions;
|
||||
unsigned32 maximum_regions;
|
||||
unsigned32 maximum_ports;
|
||||
unsigned32 maximum_periods;
|
||||
unsigned32 maximum_extensions;
|
||||
unsigned32 microseconds_per_tick;
|
||||
unsigned32 ticks_per_timeslice;
|
||||
unsigned32 maximum_devices;
|
||||
unsigned32 number_of_initialization_tasks;
|
||||
rtems_initialization_tasks_table *User_initialization_tasks_table;
|
||||
unsigned32 number_of_device_drivers;
|
||||
unsigned32 maximum_devices;
|
||||
rtems_driver_address_table *Device_driver_table;
|
||||
rtems_extensions_table *User_extension_table;
|
||||
rtems_multiprocessing_table *User_multiprocessing_table;
|
||||
rtems_api_configuration_table *RTEMS_api_configuration;
|
||||
posix_api_configuration_table *POSIX_api_configuration;
|
||||
} rtems_configuration_table;
|
||||
|
||||
/*
|
||||
@@ -92,8 +83,8 @@ typedef struct {
|
||||
* the user. They are not used in RTEMS itself.
|
||||
*/
|
||||
|
||||
SAPI_EXTERN rtems_configuration_table *_Configuration_Table;
|
||||
SAPI_EXTERN rtems_multiprocessing_table *_Configuration_MP_table;
|
||||
EXTERN rtems_configuration_table *_Configuration_Table;
|
||||
EXTERN rtems_multiprocessing_table *_Configuration_MP_table;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -43,6 +43,8 @@ typedef User_extensions_thread_delete_extension rtems_task_delete_extension;
|
||||
typedef User_extensions_thread_start_extension rtems_task_start_extension;
|
||||
typedef User_extensions_thread_restart_extension rtems_task_restart_extension;
|
||||
typedef User_extensions_thread_switch_extension rtems_task_switch_extension;
|
||||
typedef User_extensions_thread_post_switch_extension
|
||||
rtems_task_post_switch_extension;
|
||||
typedef User_extensions_thread_begin_extension rtems_task_begin_extension;
|
||||
typedef User_extensions_thread_exitted_extension rtems_task_exitted_extension;
|
||||
typedef User_extensions_fatal_extension rtems_fatal_extension;
|
||||
@@ -54,7 +56,7 @@ typedef User_extensions_Table rtems_extensions_table;
|
||||
* this class of objects.
|
||||
*/
|
||||
|
||||
SAPI_EXTERN Objects_Information _Extension_Information;
|
||||
EXTERN Objects_Information _Extension_Information;
|
||||
|
||||
/*
|
||||
* The following records define the control block used to manage
|
||||
@@ -124,9 +126,60 @@ rtems_status_code rtems_extension_delete(
|
||||
Objects_Id id
|
||||
);
|
||||
|
||||
#ifndef __RTEMS_APPLICATION__
|
||||
/*
|
||||
* _Extension_Allocate
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function allocates a extension control block from
|
||||
* the inactive chain of free extension control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE Extension_Control *_Extension_Allocate( void );
|
||||
|
||||
/*
|
||||
* _Extension_Free
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine frees a extension control block to the
|
||||
* inactive chain of free extension control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _Extension_Free (
|
||||
Extension_Control *the_extension
|
||||
);
|
||||
|
||||
/*
|
||||
* _Extension_Get
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function maps extension IDs to extension control blocks.
|
||||
* If ID corresponds to a local extension, then it returns
|
||||
* the extension control pointer which maps to ID and location
|
||||
* is set to OBJECTS_LOCAL. Otherwise, location is set
|
||||
* to OBJECTS_ERROR and the returned value is undefined.
|
||||
*/
|
||||
|
||||
STATIC INLINE Extension_Control *_Extension_Get (
|
||||
Objects_Id id,
|
||||
Objects_Locations *location
|
||||
);
|
||||
|
||||
/*
|
||||
* _Extension_Is_null
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_extension is NULL and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Extension_Is_null(
|
||||
Extension_Control *the_extension
|
||||
);
|
||||
|
||||
#include <rtems/extension.inl>
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -86,10 +86,10 @@ typedef struct {
|
||||
* Address Table and Device Name Table.
|
||||
*/
|
||||
|
||||
SAPI_EXTERN unsigned32 _IO_Number_of_drivers;
|
||||
SAPI_EXTERN rtems_driver_address_table *_IO_Driver_address_table;
|
||||
SAPI_EXTERN unsigned32 _IO_Number_of_devices;
|
||||
SAPI_EXTERN rtems_driver_name_t *_IO_Driver_name_table;
|
||||
EXTERN unsigned32 _IO_Number_of_drivers;
|
||||
EXTERN rtems_driver_address_table *_IO_Driver_address_table;
|
||||
EXTERN unsigned32 _IO_Number_of_devices;
|
||||
EXTERN rtems_driver_name_t *_IO_Driver_name_table;
|
||||
|
||||
/*
|
||||
* _IO_Manager_initialization
|
||||
@@ -99,7 +99,7 @@ SAPI_EXTERN rtems_driver_name_t *_IO_Driver_name_table;
|
||||
* This routine performs the initialization necessary for this manager.
|
||||
*/
|
||||
|
||||
void _IO_Manager_initialization(
|
||||
STATIC INLINE void _IO_Manager_initialization(
|
||||
rtems_driver_address_table *driver_table,
|
||||
unsigned32 number_of_drivers,
|
||||
unsigned32 number_of_devices
|
||||
@@ -236,6 +236,8 @@ rtems_status_code rtems_io_control(
|
||||
|
||||
void _IO_Initialize_all_drivers( void );
|
||||
|
||||
#include <rtems/io.inl>
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -62,7 +62,7 @@ const rtems_multiprocessing_table
|
||||
*/
|
||||
|
||||
const char _RTEMS_version[] =
|
||||
"RTEMS RELEASE V3.5.17 snapshot (" CPU_NAME "/" CPU_MODEL_NAME ")";
|
||||
"RTEMS RELEASE V3.5.1 (" CPU_NAME "/" CPU_MODEL_NAME ")";
|
||||
|
||||
|
||||
/*
|
||||
|
||||
@@ -21,10 +21,6 @@
|
||||
*
|
||||
* _Extension_Allocate
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function allocates a extension control block from
|
||||
* the inactive chain of free extension control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE Extension_Control *_Extension_Allocate( void )
|
||||
@@ -36,10 +32,6 @@ STATIC INLINE Extension_Control *_Extension_Allocate( void )
|
||||
*
|
||||
* _Extension_Free
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine frees a extension control block to the
|
||||
* inactive chain of free extension control blocks.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _Extension_Free (
|
||||
@@ -53,13 +45,6 @@ STATIC INLINE void _Extension_Free (
|
||||
*
|
||||
* _Extension_Get
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function maps extension IDs to extension control blocks.
|
||||
* If ID corresponds to a local extension, then it returns
|
||||
* the extension control pointer which maps to ID and location
|
||||
* is set to OBJECTS_LOCAL. Otherwise, location is set
|
||||
* to OBJECTS_ERROR and the returned value is undefined.
|
||||
*/
|
||||
|
||||
STATIC INLINE Extension_Control *_Extension_Get (
|
||||
@@ -75,9 +60,6 @@ STATIC INLINE Extension_Control *_Extension_Get (
|
||||
*
|
||||
* _Extension_Is_null
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_extension is NULL and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Extension_Is_null (
|
||||
|
||||
@@ -19,7 +19,6 @@
|
||||
#include <rtems/score/object.h>
|
||||
#include <rtems/score/thread.h>
|
||||
#include <rtems/extension.h>
|
||||
#include <rtems/score/interr.h>
|
||||
|
||||
void _Extension_Manager_initialization(
|
||||
unsigned32 maximum_extensions
|
||||
@@ -33,11 +32,6 @@ rtems_status_code rtems_extension_create(
|
||||
Objects_Id *id
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -46,11 +40,6 @@ rtems_status_code rtems_extension_ident(
|
||||
Objects_Id *id
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -58,10 +47,5 @@ rtems_status_code rtems_extension_delete(
|
||||
Objects_Id id
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -19,15 +19,6 @@
|
||||
#include <rtems/io.h>
|
||||
#include <rtems/score/isr.h>
|
||||
#include <rtems/score/thread.h>
|
||||
#include <rtems/score/interr.h>
|
||||
|
||||
void _IO_Manager_initialization(
|
||||
rtems_driver_address_table *driver_table,
|
||||
unsigned32 number_of_drivers,
|
||||
unsigned32 number_of_devices
|
||||
)
|
||||
{
|
||||
}
|
||||
|
||||
void _IO_Initialize_all_drivers( void )
|
||||
{
|
||||
@@ -37,26 +28,16 @@ rtems_status_code rtems_io_register_name(
|
||||
char *device_name,
|
||||
rtems_device_major_number major,
|
||||
rtems_device_minor_number minor
|
||||
)
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
rtems_status_code rtems_io_lookup_name(
|
||||
const char *pathname,
|
||||
rtems_driver_name_t **rnp
|
||||
)
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -66,11 +47,6 @@ rtems_status_code rtems_io_initialize(
|
||||
void *argument
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -80,11 +56,6 @@ rtems_status_code rtems_io_open(
|
||||
void *argument
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -94,11 +65,6 @@ rtems_status_code rtems_io_close(
|
||||
void *argument
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -108,11 +74,6 @@ rtems_status_code rtems_io_read(
|
||||
void *argument
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -122,11 +83,6 @@ rtems_status_code rtems_io_write(
|
||||
void *argument
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -136,10 +92,5 @@ rtems_status_code rtems_io_control(
|
||||
void *argument
|
||||
)
|
||||
{
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
FALSE,
|
||||
RTEMS_NOT_CONFIGURED
|
||||
);
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
@@ -17,46 +17,9 @@
|
||||
#include <rtems/io.h>
|
||||
#include <rtems/score/isr.h>
|
||||
#include <rtems/score/thread.h>
|
||||
#include <rtems/score/wkspace.h>
|
||||
|
||||
#include <string.h>
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* _IO_Manager_initialization
|
||||
*
|
||||
*/
|
||||
|
||||
void _IO_Manager_initialization(
|
||||
rtems_driver_address_table *driver_table,
|
||||
unsigned32 number_of_drivers,
|
||||
unsigned32 number_of_devices
|
||||
)
|
||||
{
|
||||
void *tmp;
|
||||
unsigned32 index;
|
||||
rtems_driver_name_t *np;
|
||||
|
||||
_IO_Driver_address_table = driver_table;
|
||||
_IO_Number_of_drivers = number_of_drivers;
|
||||
_IO_Number_of_devices = number_of_devices;
|
||||
|
||||
tmp = _Workspace_Allocate_or_fatal_error(
|
||||
sizeof( rtems_driver_name_t ) * ( number_of_devices + 1 )
|
||||
);
|
||||
|
||||
_IO_Driver_name_table = (rtems_driver_name_t *) tmp;
|
||||
|
||||
for( index=0, np = _IO_Driver_name_table ;
|
||||
index < _IO_Number_of_devices ;
|
||||
index++, np++ ) {
|
||||
np->device_name = 0;
|
||||
np->device_name_length = 0;
|
||||
np->major = 0;
|
||||
np->minor = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* _IO_Initialize_all_drivers
|
||||
|
||||
@@ -1,76 +0,0 @@
|
||||
/*
|
||||
* RTEMS API Initialization Support
|
||||
*
|
||||
* NOTE:
|
||||
*
|
||||
* COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
* All rights assigned to U.S. Government, 1994.
|
||||
*
|
||||
* This material may be reproduced by or for the U.S. Government pursuant
|
||||
* to the copyright license under the clause at DFARS 252.227-7013. This
|
||||
* notice must appear in all copies of this file and its derivatives.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifdef RTEMS_POSIX_API
|
||||
|
||||
#include <assert.h>
|
||||
|
||||
/*
|
||||
* POSIX_API_INIT is defined so all of the POSIX API
|
||||
* data will be included in this object file.
|
||||
*/
|
||||
|
||||
#define POSIX_API_INIT
|
||||
|
||||
#include <rtems/system.h>
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <rtems/config.h>
|
||||
#include <rtems/posix/cond.h>
|
||||
#include <rtems/posix/config.h>
|
||||
#include <rtems/posix/key.h>
|
||||
#include <rtems/posix/mutex.h>
|
||||
#include <rtems/posix/priority.h>
|
||||
#include <rtems/posix/pthread.h>
|
||||
#include <rtems/posix/time.h>
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* _POSIX_API_Initialize
|
||||
*
|
||||
* XXX
|
||||
*/
|
||||
|
||||
void _POSIX_API_Initialize(
|
||||
rtems_configuration_table *configuration_table
|
||||
)
|
||||
{
|
||||
posix_api_configuration_table *api_configuration;
|
||||
|
||||
api_configuration = configuration_table->POSIX_api_configuration;
|
||||
|
||||
assert( api_configuration );
|
||||
|
||||
_POSIX_Threads_Manager_initialization(
|
||||
api_configuration->maximum_threads,
|
||||
api_configuration->number_of_initialization_tasks,
|
||||
api_configuration->User_initialization_tasks_table
|
||||
);
|
||||
|
||||
_POSIX_Condition_variables_Manager_initialization(
|
||||
api_configuration->maximum_condition_variables
|
||||
);
|
||||
|
||||
_POSIX_Key_Manager_initialization( api_configuration->maximum_keys );
|
||||
|
||||
_POSIX_Mutex_Manager_initialization(
|
||||
api_configuration->maximum_mutexes
|
||||
);
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
/* end of file */
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* POSIX API Initialization Support
|
||||
* RTEMS API Support
|
||||
*
|
||||
* NOTE:
|
||||
*
|
||||
@@ -14,17 +14,12 @@
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
/*
|
||||
* RTEMS_API_INIT is defined so all of the RTEMS API
|
||||
* data will be included in this object file.
|
||||
*/
|
||||
|
||||
#define RTEMS_API_INIT
|
||||
|
||||
#include <rtems/system.h>
|
||||
#include <rtems/rtems/status.h>
|
||||
#include <rtems/rtems/rtemsapi.h>
|
||||
|
||||
#define INIT
|
||||
|
||||
#include <rtems/rtems/intr.h>
|
||||
#include <rtems/rtems/clock.h>
|
||||
#include <rtems/rtems/tasks.h>
|
||||
@@ -50,10 +45,6 @@ void _RTEMS_API_Initialize(
|
||||
rtems_configuration_table *configuration_table
|
||||
)
|
||||
{
|
||||
rtems_api_configuration_table *api_configuration;
|
||||
|
||||
api_configuration = configuration_table->RTEMS_api_configuration;
|
||||
|
||||
_Attributes_Handler_initialization();
|
||||
|
||||
_Interrupt_Manager_initialization();
|
||||
@@ -61,30 +52,38 @@ void _RTEMS_API_Initialize(
|
||||
_Multiprocessing_Manager_initialization();
|
||||
|
||||
_RTEMS_tasks_Manager_initialization(
|
||||
api_configuration->maximum_tasks,
|
||||
api_configuration->number_of_initialization_tasks,
|
||||
api_configuration->User_initialization_tasks_table
|
||||
configuration_table->maximum_tasks,
|
||||
configuration_table->number_of_initialization_tasks,
|
||||
configuration_table->User_initialization_tasks_table
|
||||
);
|
||||
|
||||
_Timer_Manager_initialization( api_configuration->maximum_timers );
|
||||
_Timer_Manager_initialization( configuration_table->maximum_timers );
|
||||
|
||||
_Signal_Manager_initialization();
|
||||
|
||||
_Event_Manager_initialization();
|
||||
|
||||
_Message_queue_Manager_initialization(
|
||||
api_configuration->maximum_message_queues
|
||||
configuration_table->maximum_message_queues
|
||||
);
|
||||
|
||||
_Semaphore_Manager_initialization( api_configuration->maximum_semaphores );
|
||||
_Semaphore_Manager_initialization(
|
||||
configuration_table->maximum_semaphores
|
||||
);
|
||||
|
||||
_Partition_Manager_initialization( api_configuration->maximum_partitions );
|
||||
_Partition_Manager_initialization(
|
||||
configuration_table->maximum_partitions
|
||||
);
|
||||
|
||||
_Region_Manager_initialization( api_configuration->maximum_regions );
|
||||
_Region_Manager_initialization( configuration_table->maximum_regions );
|
||||
|
||||
_Dual_ported_memory_Manager_initialization( api_configuration->maximum_ports);
|
||||
_Dual_ported_memory_Manager_initialization(
|
||||
configuration_table->maximum_ports
|
||||
);
|
||||
|
||||
_Rate_monotonic_Manager_initialization( api_configuration->maximum_periods );
|
||||
_Rate_monotonic_Manager_initialization(
|
||||
configuration_table->maximum_periods
|
||||
);
|
||||
}
|
||||
|
||||
/* end of file */
|
||||
|
||||
@@ -103,10 +103,7 @@ typedef struct {
|
||||
void (*idle_task)( void );
|
||||
boolean do_zero_of_workspace;
|
||||
unsigned32 interrupt_stack_size;
|
||||
unsigned32 extra_mpci_receive_server_stack;
|
||||
void * (*stack_allocate_hook)( unsigned32 );
|
||||
void (*stack_free_hook)( void* );
|
||||
/* end of fields required on all CPUs */
|
||||
unsigned32 extra_system_initialization_stack;
|
||||
|
||||
unsigned32 interrupt_table_segment;
|
||||
void *interrupt_table_offset;
|
||||
@@ -122,9 +119,9 @@ typedef struct {
|
||||
|
||||
/* variables */
|
||||
|
||||
SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
|
||||
SCORE_EXTERN void *_CPU_Interrupt_stack_low;
|
||||
SCORE_EXTERN void *_CPU_Interrupt_stack_high;
|
||||
EXTERN Context_Control_fp _CPU_Null_fp_context;
|
||||
EXTERN void *_CPU_Interrupt_stack_low;
|
||||
EXTERN void *_CPU_Interrupt_stack_high;
|
||||
|
||||
/* constants */
|
||||
|
||||
@@ -137,10 +134,10 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high;
|
||||
#define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */
|
||||
|
||||
/*
|
||||
* extra stack required by the MPCI receive server thread
|
||||
* extra stack required by system initialization thread
|
||||
*/
|
||||
|
||||
#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
|
||||
#define CPU_SYSTEM_INITIALIZATION_THREAD_EXTRA_STACK 1024
|
||||
|
||||
/*
|
||||
* i386 family supports 256 distinct vectors.
|
||||
|
||||
@@ -145,11 +145,7 @@ typedef struct {
|
||||
void (*idle_task)( void );
|
||||
boolean do_zero_of_workspace;
|
||||
unsigned32 interrupt_stack_size;
|
||||
unsigned32 extra_mpci_receive_server_stack;
|
||||
void * (*stack_allocate_hook)( unsigned32 );
|
||||
void (*stack_free_hook)( void* );
|
||||
/* end of fields required on all CPUs */
|
||||
|
||||
unsigned32 extra_system_initialization_stack;
|
||||
#if defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
|
||||
i960ca_PRCB *Prcb;
|
||||
#endif
|
||||
@@ -157,8 +153,8 @@ typedef struct {
|
||||
|
||||
/* variables */
|
||||
|
||||
SCORE_EXTERN void *_CPU_Interrupt_stack_low;
|
||||
SCORE_EXTERN void *_CPU_Interrupt_stack_high;
|
||||
EXTERN void *_CPU_Interrupt_stack_low;
|
||||
EXTERN void *_CPU_Interrupt_stack_high;
|
||||
|
||||
/* constants */
|
||||
|
||||
@@ -177,10 +173,13 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high;
|
||||
#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
|
||||
|
||||
/*
|
||||
* extra stack required by the MPCI receive server thread
|
||||
* extra stack required by system initialization thread
|
||||
*
|
||||
* NOTE: Make sure this stays positive ...
|
||||
*/
|
||||
|
||||
#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK (CPU_STACK_MINIMUM_SIZE)
|
||||
#define CPU_SYSTEM_INITIALIZATION_THREAD_EXTRA_STACK \
|
||||
(CPU_STACK_MINIMUM_SIZE)
|
||||
|
||||
/*
|
||||
* i960 family supports 256 distinct vectors.
|
||||
@@ -192,7 +191,7 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high;
|
||||
/*
|
||||
* Minimum size of a thread's stack.
|
||||
*
|
||||
* NOTE: See CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK
|
||||
* NOTE: See CPU_SYSTEM_INITIALIZATION_THREAD_EXTRA_STACK
|
||||
*/
|
||||
|
||||
#define CPU_STACK_MINIMUM_SIZE 2048
|
||||
|
||||
@@ -81,9 +81,7 @@
|
||||
#define msp REG (msp)
|
||||
#define usp REG (usp)
|
||||
#define isp REG (isp)
|
||||
#define sr REG (sr)
|
||||
#define vbr REG (vbr)
|
||||
#define dfc REG (dfc)
|
||||
#define sr REG (sr)
|
||||
|
||||
#define fp0 REG (fp0)
|
||||
#define fp1 REG (fp1)
|
||||
|
||||
@@ -28,6 +28,8 @@ extern "C" {
|
||||
* in some time critical routines.
|
||||
*/
|
||||
|
||||
#define NO_UNINITIALIZED_WARNINGS
|
||||
|
||||
#include <rtems/score/m68k.h>
|
||||
#ifndef ASM
|
||||
#include <rtems/score/m68ktypes.h>
|
||||
@@ -136,20 +138,16 @@ typedef struct {
|
||||
void (*idle_task)( void );
|
||||
boolean do_zero_of_workspace;
|
||||
unsigned32 interrupt_stack_size;
|
||||
unsigned32 extra_mpci_receive_server_stack;
|
||||
void * (*stack_allocate_hook)( unsigned32 );
|
||||
void (*stack_free_hook)( void* );
|
||||
/* end of fields required on all CPUs */
|
||||
|
||||
unsigned32 extra_system_initialization_stack;
|
||||
m68k_isr *interrupt_vector_table;
|
||||
} rtems_cpu_table;
|
||||
|
||||
/* variables */
|
||||
|
||||
SCORE_EXTERN void *_CPU_Interrupt_stack_low;
|
||||
SCORE_EXTERN void *_CPU_Interrupt_stack_high;
|
||||
EXTERN void *_CPU_Interrupt_stack_low;
|
||||
EXTERN void *_CPU_Interrupt_stack_high;
|
||||
/* points to jsr-exception-table in targets wo/ VBR register */
|
||||
extern char _VBR[];
|
||||
extern char _VBR[];
|
||||
|
||||
/* constants */
|
||||
|
||||
@@ -168,10 +166,10 @@ extern char _VBR[];
|
||||
#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
|
||||
|
||||
/*
|
||||
* extra stack required by the MPCI receive server thread
|
||||
* extra stack required by system initialization thread
|
||||
*/
|
||||
|
||||
#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
|
||||
#define CPU_SYSTEM_INITIALIZATION_THREAD_EXTRA_STACK 1024
|
||||
|
||||
/*
|
||||
* m68k family supports 256 distinct vectors.
|
||||
@@ -184,7 +182,7 @@ extern char _VBR[];
|
||||
* Minimum size of a thread's stack.
|
||||
*/
|
||||
|
||||
#define CPU_STACK_MINIMUM_SIZE 2048
|
||||
#define CPU_STACK_MINIMUM_SIZE 1024
|
||||
|
||||
/*
|
||||
* m68k is pretty tolerant of alignment. Just put things on 4 byte boundaries.
|
||||
@@ -308,15 +306,34 @@ unsigned32 _CPU_ISR_Get_level( void );
|
||||
#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
|
||||
|
||||
#if ( M68K_HAS_BFFFO == 1 )
|
||||
#ifdef NO_UNINITIALIZED_WARNINGS
|
||||
|
||||
#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
|
||||
asm volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value));
|
||||
{ \
|
||||
register void *__base = (void *)&(_value); \
|
||||
\
|
||||
(_output) = 0; /* avoids warnings */ \
|
||||
asm volatile( "bfffo (%0),#0,#16,%1" \
|
||||
: "=a" (__base), "=d" ((_output)) \
|
||||
: "0" (__base), "1" ((_output)) ) ; \
|
||||
}
|
||||
#else
|
||||
#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
|
||||
{ \
|
||||
register void *__base = (void *)&(_value); \
|
||||
\
|
||||
asm volatile( "bfffo (%0),#0,#16,%1" \
|
||||
: "=a" (__base), "=d" ((_output)) \
|
||||
: "0" (__base), "1" ((_output)) ) ; \
|
||||
}
|
||||
#endif
|
||||
|
||||
#else
|
||||
|
||||
/* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in
|
||||
_CPU_Priority_bits_index is not needed), handles the 0 case, and
|
||||
does not molest _value -- jsg */
|
||||
#if ( M68K_HAS_EXTB_L == 1 )
|
||||
#ifndef m68000
|
||||
#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
|
||||
{ \
|
||||
extern const unsigned char __BFFFOtable[256]; \
|
||||
@@ -354,7 +371,7 @@ unsigned32 _CPU_ISR_Get_level( void );
|
||||
: "d" ((_value)), "ao" ((__BFFFOtable)) \
|
||||
: "cc" ) ; \
|
||||
}
|
||||
#endif /* M68K_HAS_EXTB_L */
|
||||
#endif /* m68000 */
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@@ -1,880 +0,0 @@
|
||||
/*
|
||||
**************************************************************************
|
||||
**************************************************************************
|
||||
** **
|
||||
** MOTOROLA MC68360 QUAD INTEGRATED COMMUNICATIONS CONTROLLER (QUICC) **
|
||||
** **
|
||||
** HARDWARE DECLARATIONS **
|
||||
** **
|
||||
** **
|
||||
** Submitted By: **
|
||||
** **
|
||||
** W. Eric Norum **
|
||||
** Saskatchewan Accelerator Laboratory **
|
||||
** University of Saskatchewan **
|
||||
** 107 North Road **
|
||||
** Saskatoon, Saskatchewan, CANADA **
|
||||
** S7N 5C6 **
|
||||
** **
|
||||
** eric@skatter.usask.ca **
|
||||
** **
|
||||
** $Id$ **
|
||||
** **
|
||||
**************************************************************************
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __MC68360_h
|
||||
#define __MC68360_h
|
||||
|
||||
/*
|
||||
*************************************************************************
|
||||
* REGISTER SUBBLOCKS *
|
||||
*************************************************************************
|
||||
*/
|
||||
|
||||
/*
|
||||
* Memory controller registers
|
||||
*/
|
||||
typedef struct m360MEMCRegisters_ {
|
||||
rtems_unsigned32 br;
|
||||
rtems_unsigned32 or;
|
||||
rtems_unsigned32 _pad[2];
|
||||
} m360MEMCRegisters_t;
|
||||
|
||||
/*
|
||||
* Serial Communications Controller registers
|
||||
*/
|
||||
typedef struct m360SCCRegisters_ {
|
||||
rtems_unsigned32 gsmr_l;
|
||||
rtems_unsigned32 gsmr_h;
|
||||
rtems_unsigned16 psmr;
|
||||
rtems_unsigned16 _pad0;
|
||||
rtems_unsigned16 todr;
|
||||
rtems_unsigned16 dsr;
|
||||
rtems_unsigned16 scce;
|
||||
rtems_unsigned16 _pad1;
|
||||
rtems_unsigned16 sccm;
|
||||
rtems_unsigned8 _pad2;
|
||||
rtems_unsigned8 sccs;
|
||||
rtems_unsigned32 _pad3[2];
|
||||
} m360SCCRegisters_t;
|
||||
|
||||
/*
|
||||
* Serial Management Controller registers
|
||||
*/
|
||||
typedef struct m360SMCRegisters_ {
|
||||
rtems_unsigned16 _pad0;
|
||||
rtems_unsigned16 smcmr;
|
||||
rtems_unsigned16 _pad1;
|
||||
rtems_unsigned8 smce;
|
||||
rtems_unsigned8 _pad2;
|
||||
rtems_unsigned16 _pad3;
|
||||
rtems_unsigned8 smcm;
|
||||
rtems_unsigned8 _pad4;
|
||||
rtems_unsigned32 _pad5;
|
||||
} m360SMCRegisters_t;
|
||||
|
||||
|
||||
/*
|
||||
*************************************************************************
|
||||
* Miscellaneous Parameters *
|
||||
*************************************************************************
|
||||
*/
|
||||
typedef struct m360MiscParms_ {
|
||||
rtems_unsigned16 rev_num;
|
||||
rtems_unsigned16 _res1;
|
||||
rtems_unsigned32 _res2;
|
||||
rtems_unsigned32 _res3;
|
||||
} m360MiscParms_t;
|
||||
|
||||
/*
|
||||
*************************************************************************
|
||||
* RISC Timers *
|
||||
*************************************************************************
|
||||
*/
|
||||
typedef struct m360TimerParms_ {
|
||||
rtems_unsigned16 tm_base;
|
||||
rtems_unsigned16 _tm_ptr;
|
||||
rtems_unsigned16 _r_tmr;
|
||||
rtems_unsigned16 _r_tmv;
|
||||
rtems_unsigned32 tm_cmd;
|
||||
rtems_unsigned32 tm_cnt;
|
||||
} m360TimerParms_t;
|
||||
|
||||
/*
|
||||
* RISC Controller Configuration Register (RCCR)
|
||||
* All other bits in this register are either reserved or
|
||||
* used only with a Motorola-supplied RAM microcode packge.
|
||||
*/
|
||||
#define M360_RCCR_TIME (1<<15) /* Enable timer */
|
||||
#define M360_RCCR_TIMEP(x) ((x)<<8) /* Timer period */
|
||||
|
||||
/*
|
||||
* Command register
|
||||
* Set up this register before issuing a M360_CR_OP_SET_TIMER command.
|
||||
*/
|
||||
#define M360_TM_CMD_V (1<<31) /* Set to enable timer */
|
||||
#define M360_TM_CMD_R (1<<30) /* Set for automatic restart */
|
||||
#define M360_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */
|
||||
#define M360_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */
|
||||
|
||||
/*
|
||||
*************************************************************************
|
||||
* DMA Controllers *
|
||||
*************************************************************************
|
||||
*/
|
||||
typedef struct m360IDMAparms_ {
|
||||
rtems_unsigned16 ibase;
|
||||
rtems_unsigned16 ibptr;
|
||||
rtems_unsigned32 _istate;
|
||||
rtems_unsigned32 _itemp;
|
||||
} m360IDMAparms_t;
|
||||
|
||||
/*
|
||||
*************************************************************************
|
||||
* Serial Communication Controllers *
|
||||
*************************************************************************
|
||||
*/
|
||||
typedef struct m360SCCparms_ {
|
||||
rtems_unsigned16 rbase;
|
||||
rtems_unsigned16 tbase;
|
||||
rtems_unsigned8 rfcr;
|
||||
rtems_unsigned8 tfcr;
|
||||
rtems_unsigned16 mrblr;
|
||||
rtems_unsigned32 _rstate;
|
||||
rtems_unsigned32 _pad0;
|
||||
rtems_unsigned16 _rbptr;
|
||||
rtems_unsigned16 _pad1;
|
||||
rtems_unsigned32 _pad2;
|
||||
rtems_unsigned32 _tstate;
|
||||
rtems_unsigned32 _pad3;
|
||||
rtems_unsigned16 _tbptr;
|
||||
rtems_unsigned16 _pad4;
|
||||
rtems_unsigned32 _pad5;
|
||||
rtems_unsigned32 _rcrc;
|
||||
rtems_unsigned32 _tcrc;
|
||||
union {
|
||||
struct {
|
||||
rtems_unsigned32 _res0;
|
||||
rtems_unsigned32 _res1;
|
||||
rtems_unsigned16 max_idl;
|
||||
rtems_unsigned16 _idlc;
|
||||
rtems_unsigned16 brkcr;
|
||||
rtems_unsigned16 parec;
|
||||
rtems_unsigned16 frmec;
|
||||
rtems_unsigned16 nosec;
|
||||
rtems_unsigned16 brkec;
|
||||
rtems_unsigned16 brklen;
|
||||
rtems_unsigned16 uaddr[2];
|
||||
rtems_unsigned16 _rtemp;
|
||||
rtems_unsigned16 toseq;
|
||||
rtems_unsigned16 character[8];
|
||||
rtems_unsigned16 rccm;
|
||||
rtems_unsigned16 rccr;
|
||||
rtems_unsigned16 rlbc;
|
||||
} uart;
|
||||
} un;
|
||||
} m360SCCparms_t;
|
||||
|
||||
typedef struct m360SCCENparms_ {
|
||||
rtems_unsigned16 rbase;
|
||||
rtems_unsigned16 tbase;
|
||||
rtems_unsigned8 rfcr;
|
||||
rtems_unsigned8 tfcr;
|
||||
rtems_unsigned16 mrblr;
|
||||
rtems_unsigned32 _rstate;
|
||||
rtems_unsigned32 _pad0;
|
||||
rtems_unsigned16 _rbptr;
|
||||
rtems_unsigned16 _pad1;
|
||||
rtems_unsigned32 _pad2;
|
||||
rtems_unsigned32 _tstate;
|
||||
rtems_unsigned32 _pad3;
|
||||
rtems_unsigned16 _tbptr;
|
||||
rtems_unsigned16 _pad4;
|
||||
rtems_unsigned32 _pad5;
|
||||
rtems_unsigned32 _rcrc;
|
||||
rtems_unsigned32 _tcrc;
|
||||
union {
|
||||
struct {
|
||||
rtems_unsigned32 _res0;
|
||||
rtems_unsigned32 _res1;
|
||||
rtems_unsigned16 max_idl;
|
||||
rtems_unsigned16 _idlc;
|
||||
rtems_unsigned16 brkcr;
|
||||
rtems_unsigned16 parec;
|
||||
rtems_unsigned16 frmec;
|
||||
rtems_unsigned16 nosec;
|
||||
rtems_unsigned16 brkec;
|
||||
rtems_unsigned16 brklen;
|
||||
rtems_unsigned16 uaddr[2];
|
||||
rtems_unsigned16 _rtemp;
|
||||
rtems_unsigned16 toseq;
|
||||
rtems_unsigned16 character[8];
|
||||
rtems_unsigned16 rccm;
|
||||
rtems_unsigned16 rccr;
|
||||
rtems_unsigned16 rlbc;
|
||||
} uart;
|
||||
struct {
|
||||
rtems_unsigned32 c_pres;
|
||||
rtems_unsigned32 c_mask;
|
||||
rtems_unsigned32 crcec;
|
||||
rtems_unsigned32 alec;
|
||||
rtems_unsigned32 disfc;
|
||||
rtems_unsigned16 pads;
|
||||
rtems_unsigned16 ret_lim;
|
||||
rtems_unsigned16 _ret_cnt;
|
||||
rtems_unsigned16 mflr;
|
||||
rtems_unsigned16 minflr;
|
||||
rtems_unsigned16 maxd1;
|
||||
rtems_unsigned16 maxd2;
|
||||
rtems_unsigned16 _maxd;
|
||||
rtems_unsigned16 dma_cnt;
|
||||
rtems_unsigned16 _max_b;
|
||||
rtems_unsigned16 gaddr1;
|
||||
rtems_unsigned16 gaddr2;
|
||||
rtems_unsigned16 gaddr3;
|
||||
rtems_unsigned16 gaddr4;
|
||||
rtems_unsigned32 _tbuf0data0;
|
||||
rtems_unsigned32 _tbuf0data1;
|
||||
rtems_unsigned32 _tbuf0rba0;
|
||||
rtems_unsigned32 _tbuf0crc;
|
||||
rtems_unsigned16 _tbuf0bcnt;
|
||||
rtems_unsigned16 paddr_h;
|
||||
rtems_unsigned16 paddr_m;
|
||||
rtems_unsigned16 paddr_l;
|
||||
rtems_unsigned16 p_per;
|
||||
rtems_unsigned16 _rfbd_ptr;
|
||||
rtems_unsigned16 _tfbd_ptr;
|
||||
rtems_unsigned16 _tlbd_ptr;
|
||||
rtems_unsigned32 _tbuf1data0;
|
||||
rtems_unsigned32 _tbuf1data1;
|
||||
rtems_unsigned32 _tbuf1rba0;
|
||||
rtems_unsigned32 _tbuf1crc;
|
||||
rtems_unsigned16 _tbuf1bcnt;
|
||||
rtems_unsigned16 _tx_len;
|
||||
rtems_unsigned16 iaddr1;
|
||||
rtems_unsigned16 iaddr2;
|
||||
rtems_unsigned16 iaddr3;
|
||||
rtems_unsigned16 iaddr4;
|
||||
rtems_unsigned16 _boff_cnt;
|
||||
rtems_unsigned16 taddr_l;
|
||||
rtems_unsigned16 taddr_m;
|
||||
rtems_unsigned16 taddr_h;
|
||||
} ethernet;
|
||||
} un;
|
||||
} m360SCCENparms_t;
|
||||
|
||||
/*
|
||||
* Receive and transmit function code register bits
|
||||
* These apply to the function code registers of all devices, not just SCC.
|
||||
*/
|
||||
#define M360_RFCR_MOT (1<<4)
|
||||
#define M360_RFCR_DMA_SPACE 0x8
|
||||
#define M360_TFCR_MOT (1<<4)
|
||||
#define M360_TFCR_DMA_SPACE 0x8
|
||||
|
||||
/*
|
||||
*************************************************************************
|
||||
* Serial Management Controllers *
|
||||
*************************************************************************
|
||||
*/
|
||||
typedef struct m360SMCparms_ {
|
||||
rtems_unsigned16 rbase;
|
||||
rtems_unsigned16 tbase;
|
||||
rtems_unsigned8 rfcr;
|
||||
rtems_unsigned8 tfcr;
|
||||
rtems_unsigned16 mrblr;
|
||||
rtems_unsigned32 _rstate;
|
||||
rtems_unsigned32 _pad0;
|
||||
rtems_unsigned16 _rbptr;
|
||||
rtems_unsigned16 _pad1;
|
||||
rtems_unsigned32 _pad2;
|
||||
rtems_unsigned32 _tstate;
|
||||
rtems_unsigned32 _pad3;
|
||||
rtems_unsigned16 _tbptr;
|
||||
rtems_unsigned16 _pad4;
|
||||
rtems_unsigned32 _pad5;
|
||||
union {
|
||||
struct {
|
||||
rtems_unsigned16 max_idl;
|
||||
rtems_unsigned16 _pad0;
|
||||
rtems_unsigned16 brklen;
|
||||
rtems_unsigned16 brkec;
|
||||
rtems_unsigned16 brkcr;
|
||||
rtems_unsigned16 _r_mask;
|
||||
} uart;
|
||||
struct {
|
||||
rtems_unsigned16 _pad0[5];
|
||||
} transparent;
|
||||
} un;
|
||||
} m360SMCparms_t;
|
||||
|
||||
/*
|
||||
* Mode register
|
||||
*/
|
||||
#define M360_SMCMR_CLEN(x) ((x)<<11) /* Character length */
|
||||
#define M360_SMCMR_2STOP (1<<10) /* 2 stop bits */
|
||||
#define M360_SMCMR_PARITY (1<<9) /* Enable parity */
|
||||
#define M360_SMCMR_EVEN (1<<8) /* Even parity */
|
||||
#define M360_SMCMR_SM_GCI (0<<4) /* GCI Mode */
|
||||
#define M360_SMCMR_SM_UART (2<<4) /* UART Mode */
|
||||
#define M360_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */
|
||||
#define M360_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */
|
||||
#define M360_SMCMR_DM_ECHO (2<<2) /* Echo mode */
|
||||
#define M360_SMCMR_TEN (1<<1) /* Enable transmitter */
|
||||
#define M360_SMCMR_REN (1<<0) /* Enable receiver */
|
||||
|
||||
/*
|
||||
* Event and mask registers (SMCE, SMCM)
|
||||
*/
|
||||
#define M360_SMCE_BRK (1<<4)
|
||||
#define M360_SMCE_BSY (1<<2)
|
||||
#define M360_SMCE_TX (1<<1)
|
||||
#define M360_SMCE_RX (1<<0)
|
||||
|
||||
/*
|
||||
*************************************************************************
|
||||
* Serial Peripheral Interface *
|
||||
*************************************************************************
|
||||
*/
|
||||
typedef struct m360SPIparms_ {
|
||||
rtems_unsigned16 rbase;
|
||||
rtems_unsigned16 tbase;
|
||||
rtems_unsigned8 rfcr;
|
||||
rtems_unsigned8 tfcr;
|
||||
rtems_unsigned16 mrblr;
|
||||
rtems_unsigned32 _rstate;
|
||||
rtems_unsigned32 _pad0;
|
||||
rtems_unsigned16 _rbptr;
|
||||
rtems_unsigned16 _pad1;
|
||||
rtems_unsigned32 _pad2;
|
||||
rtems_unsigned32 _tstate;
|
||||
rtems_unsigned32 _pad3;
|
||||
rtems_unsigned16 _tbptr;
|
||||
rtems_unsigned16 _pad4;
|
||||
rtems_unsigned32 _pad5;
|
||||
} m360SPIparms_t;
|
||||
|
||||
/*
|
||||
* Mode register (SPMODE)
|
||||
*/
|
||||
#define M360_SPMODE_LOOP (1<<14) /* Local loopback mode */
|
||||
#define M360_SPMODE_CI (1<<13) /* Clock invert */
|
||||
#define M360_SPMODE_CP (1<<12) /* Clock phase */
|
||||
#define M360_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */
|
||||
#define M360_SPMODE_REV (1<<10) /* Reverse data */
|
||||
#define M360_SPMODE_MASTER (1<<9) /* SPI is master */
|
||||
#define M360_SPMODE_EN (1<<8) /* Enable SPI */
|
||||
#define M360_SPMODE_CLEN(x) ((x)<<4) /* Character length */
|
||||
#define M360_SPMODE_PM(x) (x) /* Prescaler modulus */
|
||||
|
||||
/*
|
||||
* Mode register (SPCOM)
|
||||
*/
|
||||
#define M360_SPCOM_STR (1<<7) /* Start transmit */
|
||||
|
||||
/*
|
||||
* Event and mask registers (SPIE, SPIM)
|
||||
*/
|
||||
#define M360_SPIE_MME (1<<5) /* Multi-master error */
|
||||
#define M360_SPIE_TXE (1<<4) /* Tx error */
|
||||
#define M360_SPIE_BSY (1<<2) /* Busy condition*/
|
||||
#define M360_SPIE_TXB (1<<1) /* Tx buffer */
|
||||
#define M360_SPIE_RXB (1<<0) /* Rx buffer */
|
||||
|
||||
/*
|
||||
*************************************************************************
|
||||
* SDMA (SCC, SMC, SPI) Buffer Descriptors *
|
||||
*************************************************************************
|
||||
*/
|
||||
typedef struct m360BufferDescriptor_ {
|
||||
rtems_unsigned16 status;
|
||||
rtems_unsigned16 length;
|
||||
volatile void *buffer;
|
||||
} m360BufferDescriptor_t;
|
||||
|
||||
/*
|
||||
* Bits in receive buffer descriptor status word
|
||||
*/
|
||||
#define M360_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
|
||||
#define M360_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */
|
||||
#define M360_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */
|
||||
#define M360_BD_LAST (1<<11) /* Ethernet, SPI */
|
||||
#define M360_BD_CONTROL_CHAR (1<<11) /* SCC UART */
|
||||
#define M360_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */
|
||||
#define M360_BD_ADDRESS (1<<10) /* SCC UART */
|
||||
#define M360_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */
|
||||
#define M360_BD_MISS (1<<8) /* Ethernet */
|
||||
#define M360_BD_IDLE (1<<8) /* SCC UART, SMC UART */
|
||||
#define M360_BD_ADDRSS_MATCH (1<<7) /* SCC UART */
|
||||
#define M360_BD_LONG (1<<5) /* Ethernet */
|
||||
#define M360_BD_BREAK (1<<5) /* SCC UART, SMC UART */
|
||||
#define M360_BD_NONALIGNED (1<<4) /* Ethernet */
|
||||
#define M360_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */
|
||||
#define M360_BD_SHORT (1<<3) /* Ethernet */
|
||||
#define M360_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */
|
||||
#define M360_BD_CRC_ERROR (1<<2) /* Ethernet */
|
||||
#define M360_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */
|
||||
#define M360_BD_COLLISION (1<<0) /* Ethernet */
|
||||
#define M360_BD_CARRIER_LOST (1<<0) /* SCC UART */
|
||||
#define M360_BD_MASTER_ERROR (1<<0) /* SPI */
|
||||
|
||||
/*
|
||||
* Bits in transmit buffer descriptor status word
|
||||
* Many bits have the same meaning as those in receiver buffer descriptors.
|
||||
*/
|
||||
#define M360_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
|
||||
#define M360_BD_PAD (1<<14) /* Ethernet */
|
||||
#define M360_BD_CTS_REPORT (1<<11) /* SCC UART */
|
||||
#define M360_BD_TX_CRC (1<<10) /* Ethernet */
|
||||
#define M360_BD_DEFER (1<<9) /* Ethernet */
|
||||
#define M360_BD_HEARTBEAT (1<<8) /* Ethernet */
|
||||
#define M360_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */
|
||||
#define M360_BD_LATE_COLLISION (1<<7) /* Ethernet */
|
||||
#define M360_BD_NO_STOP_BIT (1<<7) /* SCC UART */
|
||||
#define M360_BD_RETRY_LIMIT (1<<6) /* Ethernet */
|
||||
#define M360_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */
|
||||
#define M360_BD_UNDERRUN (1<<1) /* Ethernet, SPI */
|
||||
#define M360_BD_CARRIER_LOST (1<<0) /* Ethernet */
|
||||
#define M360_BD_CTS_LOST (1<<0) /* SCC UART */
|
||||
|
||||
/*
|
||||
*************************************************************************
|
||||
* IDMA Buffer Descriptors *
|
||||
*************************************************************************
|
||||
*/
|
||||
typedef struct m360IDMABufferDescriptor_ {
|
||||
rtems_unsigned16 status;
|
||||
rtems_unsigned16 _pad;
|
||||
rtems_unsigned32 length;
|
||||
void *source;
|
||||
void *destination;
|
||||
} m360IDMABufferDescriptor_t;
|
||||
|
||||
/*
|
||||
*************************************************************************
|
||||
* RISC Communication Processor Module Command Register (CR) *
|
||||
*************************************************************************
|
||||
*/
|
||||
#define M360_CR_RST (1<<15) /* Reset communication processor */
|
||||
#define M360_CR_OP_INIT_RX_TX (0<<8) /* SCC, SMC UART, SMC GCI, SPI */
|
||||
#define M360_CR_OP_INIT_RX (1<<8) /* SCC, SMC UART, SPI */
|
||||
#define M360_CR_OP_INIT_TX (2<<8) /* SCC, SMC UART, SPI */
|
||||
#define M360_CR_OP_INIT_HUNT (3<<8) /* SCC, SMC UART */
|
||||
#define M360_CR_OP_STOP_TX (4<<8) /* SCC, SMC UART */
|
||||
#define M360_CR_OP_GR_STOP_TX (5<<8) /* SCC */
|
||||
#define M360_CR_OP_INIT_IDMA (5<<8) /* IDMA */
|
||||
#define M360_CR_OP_RESTART_TX (6<<8) /* SCC, SMC UART */
|
||||
#define M360_CR_OP_CLOSE_RX_BD (7<<8) /* SCC, SMC UART, SPI */
|
||||
#define M360_CR_OP_SET_GRP_ADDR (8<<8) /* SCC */
|
||||
#define M360_CR_OP_SET_TIMER (8<<8) /* Timer */
|
||||
#define M360_CR_OP_GCI_TIMEOUT (9<<8) /* SMC GCI */
|
||||
#define M360_CR_OP_RESERT_BCS (10<<8) /* SCC */
|
||||
#define M360_CR_OP_GCI_ABORT (10<<8) /* SMC GCI */
|
||||
#define M360_CR_CHAN_SCC1 (0<<4) /* Channel selection */
|
||||
#define M360_CR_CHAN_SCC2 (4<<4)
|
||||
#define M360_CR_CHAN_SPI (5<<4)
|
||||
#define M360_CR_CHAN_TIMER (5<<4)
|
||||
#define M360_CR_CHAN_SCC3 (8<<4)
|
||||
#define M360_CR_CHAN_SMC1 (9<<4)
|
||||
#define M360_CR_CHAN_IDMA1 (9<<4)
|
||||
#define M360_CR_CHAN_SCC4 (12<<4)
|
||||
#define M360_CR_CHAN_SMC2 (13<<4)
|
||||
#define M360_CR_CHAN_IDMA2 (13<<4)
|
||||
#define M360_CR_FLG (1<<0) /* Command flag */
|
||||
|
||||
/*
|
||||
*************************************************************************
|
||||
* System Protection Control Register (SYPCR) *
|
||||
*************************************************************************
|
||||
*/
|
||||
#define M360_SYPCR_SWE (1<<7) /* Software watchdog enable */
|
||||
#define M360_SYPCR_SWRI (1<<6) /* Software watchdog reset select */
|
||||
#define M360_SYPCR_SWT1 (1<<5) /* Software watchdog timing bit 1 */
|
||||
#define M360_SYPCR_SWT0 (1<<4) /* Software watchdog timing bit 0 */
|
||||
#define M360_SYPCR_DBFE (1<<3) /* Double bus fault monitor enable */
|
||||
#define M360_SYPCR_BME (1<<2) /* Bus monitor external enable */
|
||||
#define M360_SYPCR_BMT1 (1<<1) /* Bus monitor timing bit 1 */
|
||||
#define M360_SYPCR_BMT0 (1<<0) /* Bus monitor timing bit 0 */
|
||||
|
||||
/*
|
||||
*************************************************************************
|
||||
* Memory Control Registers *
|
||||
*************************************************************************
|
||||
*/
|
||||
#define M360_GMR_RCNT(x) ((x)<<24) /* Refresh count */
|
||||
#define M360_GMR_RFEN (1<<23) /* Refresh enable */
|
||||
#define M360_GMR_RCYC(x) ((x)<<21) /* Refresh cycle length */
|
||||
#define M360_GMR_PGS(x) ((x)<<18) /* Page size */
|
||||
#define M360_GMR_DPS_32BIT (0<<16) /* DRAM port size */
|
||||
#define M360_GMR_DPS_16BIT (1<<16)
|
||||
#define M360_GMR_DPS_8BIT (2<<16)
|
||||
#define M360_GMR_DPS_DSACK (3<<16)
|
||||
#define M360_GMR_WBT40 (1<<15) /* Wait between 040 transfers */
|
||||
#define M360_GMR_WBTQ (1<<14) /* Wait between 360 transfers */
|
||||
#define M360_GMR_SYNC (1<<13) /* Synchronous external access */
|
||||
#define M360_GMR_EMWS (1<<12) /* External master wait state */
|
||||
#define M360_GMR_OPAR (1<<11) /* Odd parity */
|
||||
#define M360_GMR_PBEE (1<<10) /* Parity bus error enable */
|
||||
#define M360_GMR_TSS40 (1<<9) /* TS* sample for 040 */
|
||||
#define M360_GMR_NCS (1<<8) /* No CPU space */
|
||||
#define M360_GMR_DWQ (1<<7) /* Delay write for 360 */
|
||||
#define M360_GMR_DW40 (1<<6) /* Delay write for 040 */
|
||||
#define M360_GMR_GAMX (1<<5) /* Global address mux enable */
|
||||
|
||||
#define M360_MEMC_BR_FC(x) ((x)<<7) /* Function code limit */
|
||||
#define M360_MEMC_BR_TRLXQ (1<<6) /* Relax timing requirements */
|
||||
#define M360_MEMC_BR_BACK40 (1<<5) /* Burst acknowledge to 040 */
|
||||
#define M360_MEMC_BR_CSNT40 (1<<4) /* CS* negate timing for 040 */
|
||||
#define M360_MEMC_BR_CSNTQ (1<<3) /* CS* negate timing for 360 */
|
||||
#define M360_MEMC_BR_PAREN (1<<2) /* Enable parity checking */
|
||||
#define M360_MEMC_BR_WP (1<<1) /* Write Protect */
|
||||
#define M360_MEMC_BR_V (1<<0) /* Base/Option register are valid */
|
||||
|
||||
#define M360_MEMC_OR_TCYC(x) ((x)<<28) /* Cycle length (clocks) */
|
||||
#define M360_MEMC_OR_WAITS(x) M360_MEMC_OR_TCYC((x)+1)
|
||||
#define M360_MEMC_OR_2KB 0x0FFFF800 /* Address range */
|
||||
#define M360_MEMC_OR_4KB 0x0FFFF000
|
||||
#define M360_MEMC_OR_8KB 0x0FFFE000
|
||||
#define M360_MEMC_OR_16KB 0x0FFFC000
|
||||
#define M360_MEMC_OR_32KB 0x0FFF8000
|
||||
#define M360_MEMC_OR_64KB 0x0FFF0000
|
||||
#define M360_MEMC_OR_128KB 0x0FFE0000
|
||||
#define M360_MEMC_OR_256KB 0x0FFC0000
|
||||
#define M360_MEMC_OR_512KB 0x0FF80000
|
||||
#define M360_MEMC_OR_1MB 0x0FF00000
|
||||
#define M360_MEMC_OR_2MB 0x0FE00000
|
||||
#define M360_MEMC_OR_4MB 0x0FC00000
|
||||
#define M360_MEMC_OR_8MB 0x0F800000
|
||||
#define M360_MEMC_OR_16MB 0x0F000000
|
||||
#define M360_MEMC_OR_32MB 0x0E000000
|
||||
#define M360_MEMC_OR_64MB 0x0C000000
|
||||
#define M360_MEMC_OR_128MB 0x08000000
|
||||
#define M360_MEMC_OR_256MB 0x00000000
|
||||
#define M360_MEMC_OR_FCMC(x) ((x)<<7) /* Function code mask */
|
||||
#define M360_MEMC_OR_BCYC(x) ((x)<<5) /* Burst cycle length (clocks) */
|
||||
#define M360_MEMC_OR_PGME (1<<3) /* Page mode enable */
|
||||
#define M360_MEMC_OR_32BIT (0<<1) /* Port size */
|
||||
#define M360_MEMC_OR_16BIT (1<<1)
|
||||
#define M360_MEMC_OR_8BIT (2<<1)
|
||||
#define M360_MEMC_OR_DSACK (3<<1)
|
||||
#define M360_MEMC_OR_DRAM (1<<0) /* Dynamic RAM select */
|
||||
|
||||
/*
|
||||
*************************************************************************
|
||||
* SI Mode Register (SIMODE) *
|
||||
*************************************************************************
|
||||
*/
|
||||
#define M360_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */
|
||||
#define M360_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */
|
||||
#define M360_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */
|
||||
#define M360_SI_SMC2_BRG2 (1<<28)
|
||||
#define M360_SI_SMC2_BRG3 (2<<28)
|
||||
#define M360_SI_SMC2_BRG4 (3<<28)
|
||||
#define M360_SI_SMC2_CLK5 (0<<28)
|
||||
#define M360_SI_SMC2_CLK6 (1<<28)
|
||||
#define M360_SI_SMC2_CLK7 (2<<28)
|
||||
#define M360_SI_SMC2_CLK8 (3<<28)
|
||||
#define M360_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */
|
||||
#define M360_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */
|
||||
#define M360_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */
|
||||
#define M360_SI_SMC1_BRG2 (1<<12)
|
||||
#define M360_SI_SMC1_BRG3 (2<<12)
|
||||
#define M360_SI_SMC1_BRG4 (3<<12)
|
||||
#define M360_SI_SMC1_CLK1 (0<<12)
|
||||
#define M360_SI_SMC1_CLK2 (1<<12)
|
||||
#define M360_SI_SMC1_CLK3 (2<<12)
|
||||
#define M360_SI_SMC1_CLK4 (3<<12)
|
||||
|
||||
/*
|
||||
*************************************************************************
|
||||
* SDMA Configuration Register (SDMA) *
|
||||
*************************************************************************
|
||||
*/
|
||||
#define M360_SDMA_FREEZE (2<<13) /* Freeze on next bus cycle */
|
||||
#define M360_SDMA_SISM_7 (7<<8) /* Normal interrupt service mask */
|
||||
#define M360_SDMA_SAID_4 (4<<4) /* Normal arbitration ID */
|
||||
#define M360_SDMA_INTE (1<<1) /* SBER interrupt enable */
|
||||
#define M360_SDMA_INTB (1<<0) /* SBKP interrupt enable */
|
||||
|
||||
/*
|
||||
*************************************************************************
|
||||
* Baud (sic) Rate Generators *
|
||||
*************************************************************************
|
||||
*/
|
||||
#define M360_BRG_RST (1<<17) /* Reset generator */
|
||||
#define M360_BRG_EN (1<<16) /* Enable generator */
|
||||
#define M360_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */
|
||||
#define M360_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */
|
||||
#define M360_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */
|
||||
#define M360_BRG_ATB (1<<13) /* Autobaud */
|
||||
#define M360_BRG_115200 (13<<1) /* Assume 25 MHz clock */
|
||||
#define M360_BRG_57600 (26<<1)
|
||||
#define M360_BRG_38400 (40<<1)
|
||||
#define M360_BRG_19200 (80<<1)
|
||||
#define M360_BRG_9600 (162<<1)
|
||||
#define M360_BRG_4800 (324<<1)
|
||||
#define M360_BRG_2400 (650<<1)
|
||||
#define M360_BRG_1200 (1301<<1)
|
||||
#define M360_BRG_600 (2603<<1)
|
||||
#define M360_BRG_300 ((324<<1) | 1)
|
||||
#define M360_BRG_150 ((650<<1) | 1)
|
||||
#define M360_BRG_75 ((1301<<1) | 1)
|
||||
|
||||
/*
|
||||
*************************************************************************
|
||||
* MC68360 DUAL-PORT RAM AND REGISTERS *
|
||||
*************************************************************************
|
||||
*/
|
||||
typedef struct m360_ {
|
||||
/*
|
||||
* Dual-port RAM
|
||||
*/
|
||||
rtems_unsigned8 dpram0[0x400]; /* Microcode program */
|
||||
rtems_unsigned8 dpram1[0x200];
|
||||
rtems_unsigned8 dpram2[0x100]; /* Microcode scratch */
|
||||
rtems_unsigned8 dpram3[0x100]; /* Not on REV A or B masks */
|
||||
rtems_unsigned8 _rsv0[0xC00-0x800];
|
||||
m360SCCENparms_t scc1p;
|
||||
rtems_unsigned8 _rsv1[0xCB0-0xC00-sizeof(m360SCCENparms_t)];
|
||||
m360MiscParms_t miscp;
|
||||
rtems_unsigned8 _rsv2[0xD00-0xCB0-sizeof(m360MiscParms_t)];
|
||||
m360SCCparms_t scc2p;
|
||||
rtems_unsigned8 _rsv3[0xD80-0xD00-sizeof(m360SCCparms_t)];
|
||||
m360SPIparms_t spip;
|
||||
rtems_unsigned8 _rsv4[0xDB0-0xD80-sizeof(m360SPIparms_t)];
|
||||
m360TimerParms_t tmp;
|
||||
rtems_unsigned8 _rsv5[0xE00-0xDB0-sizeof(m360TimerParms_t)];
|
||||
m360SCCparms_t scc3p;
|
||||
rtems_unsigned8 _rsv6[0xE70-0xE00-sizeof(m360SCCparms_t)];
|
||||
m360IDMAparms_t idma1p;
|
||||
rtems_unsigned8 _rsv7[0xE80-0xE70-sizeof(m360IDMAparms_t)];
|
||||
m360SMCparms_t smc1p;
|
||||
rtems_unsigned8 _rsv8[0xF00-0xE80-sizeof(m360SMCparms_t)];
|
||||
m360SCCparms_t scc4p;
|
||||
rtems_unsigned8 _rsv9[0xF70-0xF00-sizeof(m360SCCparms_t)];
|
||||
m360IDMAparms_t idma2p;
|
||||
rtems_unsigned8 _rsv10[0xF80-0xF70-sizeof(m360IDMAparms_t)];
|
||||
m360SMCparms_t smc2p;
|
||||
rtems_unsigned8 _rsv11[0x1000-0xF80-sizeof(m360SMCparms_t)];
|
||||
|
||||
/*
|
||||
* SIM Block
|
||||
*/
|
||||
rtems_unsigned32 mcr;
|
||||
rtems_unsigned32 _pad00;
|
||||
rtems_unsigned8 avr;
|
||||
rtems_unsigned8 rsr;
|
||||
rtems_unsigned16 _pad01;
|
||||
rtems_unsigned8 clkocr;
|
||||
rtems_unsigned8 _pad02;
|
||||
rtems_unsigned16 _pad03;
|
||||
rtems_unsigned16 pllcr;
|
||||
rtems_unsigned16 _pad04;
|
||||
rtems_unsigned16 cdvcr;
|
||||
rtems_unsigned16 pepar;
|
||||
rtems_unsigned32 _pad05[2];
|
||||
rtems_unsigned16 _pad06;
|
||||
rtems_unsigned8 sypcr;
|
||||
rtems_unsigned8 swiv;
|
||||
rtems_unsigned16 _pad07;
|
||||
rtems_unsigned16 picr;
|
||||
rtems_unsigned16 _pad08;
|
||||
rtems_unsigned16 pitr;
|
||||
rtems_unsigned16 _pad09;
|
||||
rtems_unsigned8 _pad10;
|
||||
rtems_unsigned8 swsr;
|
||||
rtems_unsigned32 bkar;
|
||||
rtems_unsigned32 bcar;
|
||||
rtems_unsigned32 _pad11[2];
|
||||
|
||||
/*
|
||||
* MEMC Block
|
||||
*/
|
||||
rtems_unsigned32 gmr;
|
||||
rtems_unsigned16 mstat;
|
||||
rtems_unsigned16 _pad12;
|
||||
rtems_unsigned32 _pad13[2];
|
||||
m360MEMCRegisters_t memc[8];
|
||||
rtems_unsigned8 _pad14[0xF0-0xD0];
|
||||
rtems_unsigned8 _pad15[0x100-0xF0];
|
||||
rtems_unsigned8 _pad16[0x500-0x100];
|
||||
|
||||
/*
|
||||
* IDMA1 Block
|
||||
*/
|
||||
rtems_unsigned16 iccr;
|
||||
rtems_unsigned16 _pad17;
|
||||
rtems_unsigned16 cmr1;
|
||||
rtems_unsigned16 _pad18;
|
||||
rtems_unsigned32 sapr1;
|
||||
rtems_unsigned32 dapr1;
|
||||
rtems_unsigned32 bcr1;
|
||||
rtems_unsigned8 fcr1;
|
||||
rtems_unsigned8 _pad19;
|
||||
rtems_unsigned8 cmar1;
|
||||
rtems_unsigned8 _pad20;
|
||||
rtems_unsigned8 csr1;
|
||||
rtems_unsigned8 _pad21;
|
||||
rtems_unsigned16 _pad22;
|
||||
|
||||
/*
|
||||
* SDMA Block
|
||||
*/
|
||||
rtems_unsigned8 sdsr;
|
||||
rtems_unsigned8 _pad23;
|
||||
rtems_unsigned16 sdcr;
|
||||
rtems_unsigned32 sdar;
|
||||
|
||||
/*
|
||||
* IDMA2 Block
|
||||
*/
|
||||
rtems_unsigned16 _pad24;
|
||||
rtems_unsigned16 cmr2;
|
||||
rtems_unsigned32 sapr2;
|
||||
rtems_unsigned32 dapr2;
|
||||
rtems_unsigned32 bcr2;
|
||||
rtems_unsigned8 fcr2;
|
||||
rtems_unsigned8 _pad26;
|
||||
rtems_unsigned8 cmar2;
|
||||
rtems_unsigned8 _pad27;
|
||||
rtems_unsigned8 csr2;
|
||||
rtems_unsigned8 _pad28;
|
||||
rtems_unsigned16 _pad29;
|
||||
rtems_unsigned32 _pad30;
|
||||
|
||||
/*
|
||||
* CPIC Block
|
||||
*/
|
||||
rtems_unsigned32 cicr;
|
||||
rtems_unsigned32 cipr;
|
||||
rtems_unsigned32 cimr;
|
||||
rtems_unsigned32 cisr;
|
||||
|
||||
/*
|
||||
* Parallel I/O Block
|
||||
*/
|
||||
rtems_unsigned16 padir;
|
||||
rtems_unsigned16 papar;
|
||||
rtems_unsigned16 paodr;
|
||||
rtems_unsigned16 padat;
|
||||
rtems_unsigned32 _pad31[2];
|
||||
rtems_unsigned16 pcdir;
|
||||
rtems_unsigned16 pcpar;
|
||||
rtems_unsigned16 pcso;
|
||||
rtems_unsigned16 pcdat;
|
||||
rtems_unsigned16 pcint;
|
||||
rtems_unsigned16 _pad32;
|
||||
rtems_unsigned32 _pad33[5];
|
||||
|
||||
/*
|
||||
* TIMER Block
|
||||
*/
|
||||
rtems_unsigned16 tgcr;
|
||||
rtems_unsigned16 _pad34;
|
||||
rtems_unsigned32 _pad35[3];
|
||||
rtems_unsigned16 tmr1;
|
||||
rtems_unsigned16 tmr2;
|
||||
rtems_unsigned16 trr1;
|
||||
rtems_unsigned16 trr2;
|
||||
rtems_unsigned16 tcr1;
|
||||
rtems_unsigned16 tcr2;
|
||||
rtems_unsigned16 tcn1;
|
||||
rtems_unsigned16 tcn2;
|
||||
rtems_unsigned16 tmr3;
|
||||
rtems_unsigned16 tmr4;
|
||||
rtems_unsigned16 trr3;
|
||||
rtems_unsigned16 trr4;
|
||||
rtems_unsigned16 tcr3;
|
||||
rtems_unsigned16 tcr4;
|
||||
rtems_unsigned16 tcn3;
|
||||
rtems_unsigned16 tcn4;
|
||||
rtems_unsigned16 ter1;
|
||||
rtems_unsigned16 ter2;
|
||||
rtems_unsigned16 ter3;
|
||||
rtems_unsigned16 ter4;
|
||||
rtems_unsigned32 _pad36[2];
|
||||
|
||||
/*
|
||||
* CP Block
|
||||
*/
|
||||
rtems_unsigned16 cr;
|
||||
rtems_unsigned16 _pad37;
|
||||
rtems_unsigned16 rccr;
|
||||
rtems_unsigned16 _pad38;
|
||||
rtems_unsigned32 _pad39[3];
|
||||
rtems_unsigned16 _pad40;
|
||||
rtems_unsigned16 rter;
|
||||
rtems_unsigned16 _pad41;
|
||||
rtems_unsigned16 rtmr;
|
||||
rtems_unsigned32 _pad42[5];
|
||||
|
||||
/*
|
||||
* BRG Block
|
||||
*/
|
||||
rtems_unsigned32 brgc1;
|
||||
rtems_unsigned32 brgc2;
|
||||
rtems_unsigned32 brgc3;
|
||||
rtems_unsigned32 brgc4;
|
||||
|
||||
/*
|
||||
* SCC Block
|
||||
*/
|
||||
m360SCCRegisters_t scc1;
|
||||
m360SCCRegisters_t scc2;
|
||||
m360SCCRegisters_t scc3;
|
||||
m360SCCRegisters_t scc4;
|
||||
|
||||
/*
|
||||
* SMC Block
|
||||
*/
|
||||
m360SMCRegisters_t smc1;
|
||||
m360SMCRegisters_t smc2;
|
||||
|
||||
/*
|
||||
* SPI Block
|
||||
*/
|
||||
rtems_unsigned16 spmode;
|
||||
rtems_unsigned16 _pad43[2];
|
||||
rtems_unsigned8 spie;
|
||||
rtems_unsigned8 _pad44;
|
||||
rtems_unsigned16 _pad45;
|
||||
rtems_unsigned8 spim;
|
||||
rtems_unsigned8 _pad46[2];
|
||||
rtems_unsigned8 spcom;
|
||||
rtems_unsigned16 _pad47[2];
|
||||
|
||||
/*
|
||||
* PIP Block
|
||||
*/
|
||||
rtems_unsigned16 pipc;
|
||||
rtems_unsigned16 _pad48;
|
||||
rtems_unsigned16 ptpr;
|
||||
rtems_unsigned32 pbdir;
|
||||
rtems_unsigned32 pbpar;
|
||||
rtems_unsigned16 _pad49;
|
||||
rtems_unsigned16 pbodr;
|
||||
rtems_unsigned32 pbdat;
|
||||
rtems_unsigned32 _pad50[6];
|
||||
|
||||
/*
|
||||
* SI Block
|
||||
*/
|
||||
rtems_unsigned32 simode;
|
||||
rtems_unsigned8 sigmr;
|
||||
rtems_unsigned8 _pad51;
|
||||
rtems_unsigned8 sistr;
|
||||
rtems_unsigned8 sicmr;
|
||||
rtems_unsigned32 _pad52;
|
||||
rtems_unsigned32 sicr;
|
||||
rtems_unsigned16 _pad53;
|
||||
rtems_unsigned16 sirp[2];
|
||||
rtems_unsigned16 _pad54;
|
||||
rtems_unsigned32 _pad55[2];
|
||||
rtems_unsigned8 siram[256];
|
||||
} m360_t;
|
||||
|
||||
extern volatile m360_t m360;
|
||||
|
||||
#endif /* __MC68360_h */
|
||||
@@ -58,11 +58,9 @@ extern "C" {
|
||||
* m68040 (implies FP)
|
||||
* m68lc040 (no FP)
|
||||
* m68ec040 (no FP)
|
||||
* m68302 (no FP)
|
||||
* mcpu32 (no FP) (includes m68360)
|
||||
*
|
||||
* Primary difference (for RTEMS) between m68040, m680lc040, and
|
||||
* m68ec040 is the presence or absence of the FPU.
|
||||
* m68ec040 is the presence or abscense of the FPU.
|
||||
*
|
||||
* Here is some information on the 040 variants (courtesy of Doug McBride,
|
||||
* mcbride@rodin.colorado.edu):
|
||||
@@ -76,17 +74,8 @@ extern "C" {
|
||||
* (cause an indeterminate result). The 68EC040 and 68LC040 do not
|
||||
* implement the DLE or multiplexed bus modes. The 68EC040 does not
|
||||
* implement the output buffer impedance selection mode of operation."
|
||||
*
|
||||
* M68K_HAS_EXTB_L is used to enable/disable usage of the extb.l instruction
|
||||
* which is not available for 68000 or 68ec000 cores (68000, 68001, 68008,
|
||||
* 68010, 68302, 68306, 68307). This instruction is available on the 68020
|
||||
* up and the cpu32 based models.
|
||||
*
|
||||
* NOTE:
|
||||
* Eventually it would be nice to evaluate doing a lot of this section
|
||||
* by having each model specigy which core it uses and then go from there.
|
||||
*/
|
||||
|
||||
|
||||
#if defined(m68000)
|
||||
|
||||
#define CPU_MODEL_NAME "m68000"
|
||||
@@ -95,7 +84,6 @@ extern "C" {
|
||||
#define M68K_HAS_FPU 0
|
||||
#define M68K_HAS_BFFFO 0
|
||||
#define M68K_HAS_PREINDEXING 0
|
||||
#define M68K_HAS_EXTB_L 0
|
||||
|
||||
#elif defined(m68020)
|
||||
|
||||
@@ -105,7 +93,6 @@ extern "C" {
|
||||
#define M68K_HAS_FPU 1
|
||||
#define M68K_HAS_BFFFO 1
|
||||
#define M68K_HAS_PREINDEXING 1
|
||||
#define M68K_HAS_EXTB_L 1
|
||||
|
||||
#elif defined(m68020_nofp)
|
||||
|
||||
@@ -115,7 +102,6 @@ extern "C" {
|
||||
#define M68K_HAS_FPU 0
|
||||
#define M68K_HAS_BFFFO 1
|
||||
#define M68K_HAS_PREINDEXING 1
|
||||
#define M68K_HAS_EXTB_L 1
|
||||
|
||||
#elif defined(m68030)
|
||||
|
||||
@@ -125,7 +111,6 @@ extern "C" {
|
||||
#define M68K_HAS_FPU 1
|
||||
#define M68K_HAS_BFFFO 1
|
||||
#define M68K_HAS_PREINDEXING 1
|
||||
#define M68K_HAS_EXTB_L 1
|
||||
|
||||
#elif defined(m68040)
|
||||
|
||||
@@ -135,7 +120,6 @@ extern "C" {
|
||||
#define M68K_HAS_FPU 1
|
||||
#define M68K_HAS_BFFFO 1
|
||||
#define M68K_HAS_PREINDEXING 1
|
||||
#define M68K_HAS_EXTB_L 1
|
||||
|
||||
#elif defined(m68lc040)
|
||||
|
||||
@@ -145,7 +129,6 @@ extern "C" {
|
||||
#define M68K_HAS_FPU 0
|
||||
#define M68K_HAS_BFFFO 1
|
||||
#define M68K_HAS_PREINDEXING 1
|
||||
#define M68K_HAS_EXTB_L 1
|
||||
|
||||
#elif defined(m68ec040)
|
||||
|
||||
@@ -155,17 +138,6 @@ extern "C" {
|
||||
#define M68K_HAS_FPU 0
|
||||
#define M68K_HAS_BFFFO 1
|
||||
#define M68K_HAS_PREINDEXING 1
|
||||
#define M68K_HAS_EXTB_L 1
|
||||
|
||||
#elif defined(m68302)
|
||||
/* essentially a m68000 with onboard peripherals */
|
||||
#define CPU_MODEL_NAME "m68302"
|
||||
#define M68K_HAS_VBR 0
|
||||
#define M68K_HAS_SEPARATE_STACKS 0
|
||||
#define M68K_HAS_FPU 0
|
||||
#define M68K_HAS_BFFFO 0
|
||||
#define M68K_HAS_PREINDEXING 0
|
||||
#define M68K_HAS_EXTB_L 0
|
||||
|
||||
#elif defined(m68332)
|
||||
|
||||
@@ -175,17 +147,6 @@ extern "C" {
|
||||
#define M68K_HAS_FPU 0
|
||||
#define M68K_HAS_BFFFO 0
|
||||
#define M68K_HAS_PREINDEXING 0
|
||||
#define M68K_HAS_EXTB_L 1
|
||||
|
||||
#elif defined(mcpu32)
|
||||
|
||||
#define CPU_MODEL_NAME "mcpu32"
|
||||
#define M68K_HAS_VBR 1
|
||||
#define M68K_HAS_SEPARATE_STACKS 0
|
||||
#define M68K_HAS_FPU 0
|
||||
#define M68K_HAS_BFFFO 0
|
||||
#define M68K_HAS_PREINDEXING 1
|
||||
#define M68K_HAS_EXTB_L 1
|
||||
|
||||
#else
|
||||
|
||||
@@ -193,6 +154,15 @@ extern "C" {
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* If defined, this causes some of the macros to initialize their
|
||||
* variables to zero before doing inline assembly. This gets rid
|
||||
* of compile time warnings at the cost of a little execution time
|
||||
* in some time critical routines.
|
||||
*/
|
||||
|
||||
#define NO_UNINITIALIZED_WARNINGS
|
||||
|
||||
/*
|
||||
* Define the name of the CPU family.
|
||||
*/
|
||||
@@ -201,42 +171,78 @@ extern "C" {
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
#ifdef NO_UNINITIALIZED_WARNINGS
|
||||
#define m68k_disable_interrupts( _level ) \
|
||||
asm volatile ( "movew %%sr,%0\n\t" \
|
||||
"orw #0x0700,%%sr" \
|
||||
: "=d" (_level))
|
||||
{ \
|
||||
(_level) = 0; /* avoids warnings */ \
|
||||
asm volatile ( "movew %%sr,%0 ; \
|
||||
orw #0x0700,%%sr" \
|
||||
: "=d" ((_level)) : "0" ((_level)) \
|
||||
); \
|
||||
}
|
||||
#else
|
||||
#define m68k_disable_interrupts( _level ) \
|
||||
{ \
|
||||
asm volatile ( "movew %%sr,%0 ; \
|
||||
orw #0x0700,%%sr" \
|
||||
: "=d" ((_level)) : "0" ((_level)) \
|
||||
); \
|
||||
}
|
||||
#endif
|
||||
|
||||
#define m68k_enable_interrupts( _level ) \
|
||||
asm volatile ( "movew %0,%%sr " : : "d" (_level));
|
||||
{ \
|
||||
asm volatile ( "movew %0,%%sr " \
|
||||
: "=d" ((_level)) : "0" ((_level)) \
|
||||
); \
|
||||
}
|
||||
|
||||
#define m68k_flash_interrupts( _level ) \
|
||||
asm volatile ( "movew %0,%%sr\n\t" \
|
||||
"orw #0x0700,%%sr" \
|
||||
: : "d" (_level))
|
||||
{ \
|
||||
asm volatile ( "movew %0,%%sr ; \
|
||||
orw #0x0700,%%sr" \
|
||||
: "=d" ((_level)) : "0" ((_level)) \
|
||||
); \
|
||||
}
|
||||
|
||||
#define m68k_get_interrupt_level( _level ) \
|
||||
do { \
|
||||
register unsigned32 _tmpsr; \
|
||||
register unsigned32 _tmpsr = 0; \
|
||||
\
|
||||
asm volatile( "movw %%sr,%0" \
|
||||
: "=d" (_tmpsr) : "0" (_tmpsr) \
|
||||
); \
|
||||
\
|
||||
asm volatile( "movw %%sr,%0" : "=d" (_tmpsr)); \
|
||||
_level = (_tmpsr & 0x0700) >> 8; \
|
||||
} while (0)
|
||||
|
||||
#define m68k_set_interrupt_level( _newlevel ) \
|
||||
do { \
|
||||
register unsigned32 _tmpsr; \
|
||||
{ \
|
||||
register unsigned32 _tmpsr = 0; \
|
||||
\
|
||||
asm volatile( "movw %%sr,%0" \
|
||||
: "=d" (_tmpsr) : "0" (_tmpsr) \
|
||||
); \
|
||||
\
|
||||
asm volatile( "movw %%sr,%0" : "=d" (_tmpsr)); \
|
||||
_tmpsr = (_tmpsr & 0xf8ff) | ((_newlevel) << 8); \
|
||||
asm volatile( "movw %0,%%sr" : : "d" (_tmpsr)); \
|
||||
} while (0)
|
||||
\
|
||||
asm volatile( "movw %0,%%sr" \
|
||||
: "=d" (_tmpsr) : "0" (_tmpsr) \
|
||||
); \
|
||||
}
|
||||
|
||||
#if ( M68K_HAS_VBR == 1 )
|
||||
#define m68k_get_vbr( vbr ) \
|
||||
asm volatile ( "movec %%vbr,%0 " : "=r" (vbr))
|
||||
{ (vbr) = 0; \
|
||||
asm volatile ( "movec %%vbr,%0 " \
|
||||
: "=r" (vbr) : "0" (vbr) ); \
|
||||
}
|
||||
|
||||
#define m68k_set_vbr( vbr ) \
|
||||
asm volatile ( "movec %0,%%vbr " : : "r" (vbr))
|
||||
{ register m68k_isr *_vbr= (m68k_isr *)(vbr); \
|
||||
asm volatile ( "movec %0,%%vbr " \
|
||||
: "=a" (_vbr) : "0" (_vbr) ); \
|
||||
}
|
||||
#else
|
||||
#define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR
|
||||
#define m68k_set_vbr( _vbr )
|
||||
|
||||
@@ -50,28 +50,14 @@
|
||||
#define _SIM_H_
|
||||
|
||||
|
||||
/*
|
||||
* XXX Why is a generic file like this including a bsp specific file?
|
||||
|
||||
#include <efi332.h>
|
||||
*/
|
||||
|
||||
|
||||
/* SAM-- shift and mask */
|
||||
#undef SAM
|
||||
#define SAM(a,b,c) ((a << b) & c)
|
||||
|
||||
/*
|
||||
* These macros make this file usable from assembly.
|
||||
*/
|
||||
|
||||
#ifdef ASM
|
||||
#define SIM_VOLATILE_USHORT_POINTER
|
||||
#define SIM_VOLATILE_UCHAR_POINTER
|
||||
#else
|
||||
#define SIM_VOLATILE_USHORT_POINTER (volatile unsigned short int * const)
|
||||
#define SIM_VOLATILE_UCHAR_POINTER (volatile unsigned char * const)
|
||||
#endif
|
||||
|
||||
/* SIM_CRB (SIM Control Register Block) base address of the SIM
|
||||
control registers */
|
||||
@@ -87,7 +73,7 @@
|
||||
|
||||
|
||||
|
||||
#define SIMCR SIM_VOLATILE_USHORT_POINTER(0x00 + SIM_CRB)
|
||||
#define SIMCR (volatile unsigned short int * const)(0x00 + SIM_CRB)
|
||||
/* Module Configuration Register */
|
||||
#define EXOFF 0x8000 /* External Clock Off */
|
||||
#define FRZSW 0x4000 /* Freeze Software Enable */
|
||||
@@ -100,13 +86,13 @@
|
||||
|
||||
|
||||
|
||||
#define SIMTR SIM_VOLATILE_USHORT_POINTER(0x02 + SIM_CRB)
|
||||
#define SIMTR (volatile unsigned short int * const)(0x02 + SIM_CRB)
|
||||
/* SIM Test Register */
|
||||
/* Used only for factor testing */
|
||||
|
||||
|
||||
|
||||
#define SYNCR SIM_VOLATILE_USHORT_POINTER(0x04 + SIM_CRB)
|
||||
#define SYNCR (volatile unsigned short int * const)(0x04 + SIM_CRB)
|
||||
/* Clock Synthesizer Control Register */
|
||||
#define W 0x8000 /* Frequency Control (VCO) */
|
||||
#define X 0x4000 /* Frequency Control Bit (Prescale) */
|
||||
@@ -120,7 +106,7 @@
|
||||
|
||||
|
||||
|
||||
#define RSR SIM_VOLATILE_UCHAR_POINTER(0x07 + SIM_CRB)
|
||||
#define RSR (volatile unsigned char * const)(0x07 + SIM_CRB)
|
||||
/* Reset Status Register */
|
||||
#define EXT 0x0080 /* External Reset */
|
||||
#define POW 0x0040 /* Power-On Reset */
|
||||
@@ -132,18 +118,18 @@
|
||||
|
||||
|
||||
|
||||
#define SIMTRE SIM_VOLATILE_USHORT_POINTER(0x08 + SIM_CRB)
|
||||
#define SIMTRE (volatile unsigned short int * const)(0x08 + SIM_CRB)
|
||||
/* System Integration Test Register */
|
||||
/* Used only for factor testing */
|
||||
|
||||
|
||||
|
||||
#define PORTE0 SIM_VOLATILE_UCHAR_POINTER(0x11 + SIM_CRB)
|
||||
#define PORTE1 SIM_VOLATILE_UCHAR_POINTER(0x13 + SIM_CRB)
|
||||
#define PORTE0 (volatile unsigned char * const)(0x11 + SIM_CRB)
|
||||
#define PORTE1 (volatile unsigned char * const)(0x13 + SIM_CRB)
|
||||
/* Port E Data Register */
|
||||
#define DDRE SIM_VOLATILE_UCHAR_POINTER(0x15 + SIM_CRB)
|
||||
#define DDRE (volatile unsigned char * const)(0x15 + SIM_CRB)
|
||||
/* Port E Data Direction Register */
|
||||
#define PEPAR SIM_VOLATILE_UCHAR_POINTER(0x17 + SIM_CRB)
|
||||
#define PEPAR (volatile unsigned char * const)(0x17 + SIM_CRB)
|
||||
/* Port E Pin Assignment Register */
|
||||
/* Any bit cleared (zero) defines the corresponding pin to be an I/O
|
||||
pin. Any bit set defines the corresponding pin to be a bus control
|
||||
@@ -151,19 +137,19 @@
|
||||
|
||||
|
||||
|
||||
#define PORTF0 SIM_VOLATILE_UCHAR_POINTER(0x19 + SIM_CRB)
|
||||
#define PORTF1 SIM_VOLATILE_UCHAR_POINTER(0x1b + SIM_CRB)
|
||||
#define PORTF0 (volatile unsigned char * const)(0x19 + SIM_CRB)
|
||||
#define PORTF1 (volatile unsigned char * const)(0x1b + SIM_CRB)
|
||||
/* Port F Data Register */
|
||||
#define DDRF SIM_VOLATILE_UCHAR_POINTER(0x1d + SIM_CRB)
|
||||
#define DDRF (volatile unsigned char * const)(0x1d + SIM_CRB)
|
||||
/* Port E Data Direction Register */
|
||||
#define PFPAR SIM_VOLATILE_UCHAR_POINTER(0x1f + SIM_CRB)
|
||||
#define PFPAR (volatile unsigned char * const)(0x1f + SIM_CRB)
|
||||
/* Any bit cleared (zero) defines the corresponding pin to be an I/O
|
||||
pin. Any bit set defines the corresponding pin to be a bus control
|
||||
signal. */
|
||||
|
||||
|
||||
|
||||
#define SYPCR SIM_VOLATILE_UCHAR_POINTER(0x21 + SIM_CRB)
|
||||
#define SYPCR (volatile unsigned char * const)(0x21 + SIM_CRB)
|
||||
/* !!! can write to only once after reset !!! */
|
||||
/* System Protection Control Register */
|
||||
#define SWE 0x80 /* Software Watch Enable */
|
||||
@@ -175,55 +161,55 @@
|
||||
|
||||
|
||||
|
||||
#define PICR SIM_VOLATILE_USHORT_POINTER(0x22 + SIM_CRB)
|
||||
#define PICR (volatile unsigned short int * const)(0x22 + SIM_CRB)
|
||||
/* Periodic Interrupt Control Reg. */
|
||||
#define PIRQL 0x0700 /* Periodic Interrupt Request Level */
|
||||
#define PIV 0x00ff /* Periodic Interrupt Level */
|
||||
|
||||
|
||||
|
||||
#define PITR SIM_VOLATILE_USHORT_POINTER(0x24 + SIM_CRB)
|
||||
#define PITR (volatile unsigned short int * const)(0x24 + SIM_CRB)
|
||||
/* Periodic Interrupt Timer Register */
|
||||
#define PTP 0x0100 /* Periodic Timer Prescaler Control */
|
||||
#define PITM 0x00ff /* Periodic Interrupt Timing Modulus */
|
||||
|
||||
|
||||
|
||||
#define SWSR SIM_VOLATILE_UCHAR_POINTER(0x27 + SIM_CRB)
|
||||
#define SWSR (volatile unsigned char * const)(0x27 + SIM_CRB)
|
||||
/* Software Service Register */
|
||||
/* write 0x55 then 0xaa to service the software watchdog */
|
||||
|
||||
|
||||
|
||||
#define TSTMSRA SIM_VOLATILE_USHORT_POINTER(0x30 + SIM_CRB)
|
||||
#define TSTMSRA (volatile unsigned short int * const)(0x30 + SIM_CRB)
|
||||
/* Test Module Master Shift A */
|
||||
#define TSTMSRB SIM_VOLATILE_USHORT_POINTER(0x32 + SIM_CRB)
|
||||
#define TSTMSRB (volatile unsigned short int * const)(0x32 + SIM_CRB)
|
||||
/* Test Module Master Shift A */
|
||||
#define TSTSC SIM_VOLATILE_USHORT_POINTER(0x34 + SIM_CRB)
|
||||
#define TSTSC (volatile unsigned short int * const)(0x34 + SIM_CRB)
|
||||
/* Test Module Shift Count */
|
||||
#define TSTRC SIM_VOLATILE_USHORT_POINTER(0x36 + SIM_CRB)
|
||||
#define TSTRC (volatile unsigned short int * const)(0x36 + SIM_CRB)
|
||||
/* Test Module Repetition Counter */
|
||||
#define CREG SIM_VOLATILE_USHORT_POINTER(0x38 + SIM_CRB)
|
||||
#define CREG (volatile unsigned short int * const)(0x38 + SIM_CRB)
|
||||
/* Test Module Control */
|
||||
#define DREG SIM_VOLATILE_USHORT_POINTER(0x3a + SIM_CRB)
|
||||
#define DREG (volatile unsigned short int * const)(0x3a + SIM_CRB)
|
||||
/* Test Module Distributed */
|
||||
/* Used only for factor testing */
|
||||
|
||||
|
||||
|
||||
#define PORTC SIM_VOLATILE_UCHAR_POINTER(0x41 + SIM_CRB)
|
||||
#define PORTC (volatile unsigned char * const)(0x41 + SIM_CRB)
|
||||
/* Port C Data */
|
||||
|
||||
|
||||
|
||||
#define CSPAR0 SIM_VOLATILE_USHORT_POINTER(0x44 + SIM_CRB)
|
||||
#define CSPAR0 (volatile unsigned short int * const)(0x44 + SIM_CRB)
|
||||
/* Chip Select Pin Assignment
|
||||
Resgister 0 */
|
||||
/* CSPAR0 contains seven two-bit fields that determine the functions
|
||||
of corresponding chip-select pins. CSPAR0[15:14] are not
|
||||
used. These bits always read zero; write have no effect. CSPAR0 bit
|
||||
1 always reads one; writes to CSPAR0 bit 1 have no effect. */
|
||||
#define CSPAR1 SIM_VOLATILE_USHORT_POINTER(0x46 + SIM_CRB)
|
||||
#define CSPAR1 (volatile unsigned short int * const)(0x46 + SIM_CRB)
|
||||
/* Chip Select Pin Assignment
|
||||
Register 1 */
|
||||
/* CSPAR1 contains five two-bit fields that determine the finctions of
|
||||
@@ -269,18 +255,18 @@
|
||||
#define BS_512K 0x6
|
||||
#define BS_1M 0x7
|
||||
|
||||
#define CSBARBT SIM_VOLATILE_USHORT_POINTER(0x48 + SIM_CRB)
|
||||
#define CSBAR0 SIM_VOLATILE_USHORT_POINTER(0x4c + SIM_CRB)
|
||||
#define CSBAR1 SIM_VOLATILE_USHORT_POINTER(0x50 + SIM_CRB)
|
||||
#define CSBAR2 SIM_VOLATILE_USHORT_POINTER(0x54 + SIM_CRB)
|
||||
#define CSBAR3 SIM_VOLATILE_USHORT_POINTER(0x58 + SIM_CRB)
|
||||
#define CSBAR4 SIM_VOLATILE_USHORT_POINTER(0x5c + SIM_CRB)
|
||||
#define CSBAR5 SIM_VOLATILE_USHORT_POINTER(0x60 + SIM_CRB)
|
||||
#define CSBAR6 SIM_VOLATILE_USHORT_POINTER(0x64 + SIM_CRB)
|
||||
#define CSBAR7 SIM_VOLATILE_USHORT_POINTER(0x68 + SIM_CRB)
|
||||
#define CSBAR8 SIM_VOLATILE_USHORT_POINTER(0x6c + SIM_CRB)
|
||||
#define CSBAR9 SIM_VOLATILE_USHORT_POINTER(0x70 + SIM_CRB)
|
||||
#define CSBAR10 SIM_VOLATILE_USHORT_POINTER(0x74 + SIM_CRB)
|
||||
#define CSBARBT (volatile unsigned short int * const)(0x48 + SIM_CRB)
|
||||
#define CSBAR0 (volatile unsigned short int * const)(0x4c + SIM_CRB)
|
||||
#define CSBAR1 (volatile unsigned short int * const)(0x50 + SIM_CRB)
|
||||
#define CSBAR2 (volatile unsigned short int * const)(0x54 + SIM_CRB)
|
||||
#define CSBAR3 (volatile unsigned short int * const)(0x58 + SIM_CRB)
|
||||
#define CSBAR4 (volatile unsigned short int * const)(0x5c + SIM_CRB)
|
||||
#define CSBAR5 (volatile unsigned short int * const)(0x60 + SIM_CRB)
|
||||
#define CSBAR6 (volatile unsigned short int * const)(0x64 + SIM_CRB)
|
||||
#define CSBAR7 (volatile unsigned short int * const)(0x68 + SIM_CRB)
|
||||
#define CSBAR8 (volatile unsigned short int * const)(0x6c + SIM_CRB)
|
||||
#define CSBAR9 (volatile unsigned short int * const)(0x70 + SIM_CRB)
|
||||
#define CSBAR10 (volatile unsigned short int * const)(0x74 + SIM_CRB)
|
||||
|
||||
#define MODE 0x8000
|
||||
#define Disable 0
|
||||
@@ -326,17 +312,17 @@
|
||||
|
||||
#define AVEC 1
|
||||
|
||||
#define CSORBT SIM_VOLATILE_USHORT_POINTER(0x4a + SIM_CRB)
|
||||
#define CSOR0 SIM_VOLATILE_USHORT_POINTER(0x4e + SIM_CRB)
|
||||
#define CSOR1 SIM_VOLATILE_USHORT_POINTER(0x52 + SIM_CRB)
|
||||
#define CSOR2 SIM_VOLATILE_USHORT_POINTER(0x56 + SIM_CRB)
|
||||
#define CSOR3 SIM_VOLATILE_USHORT_POINTER(0x5a + SIM_CRB)
|
||||
#define CSOR4 SIM_VOLATILE_USHORT_POINTER(0x5e + SIM_CRB)
|
||||
#define CSOR5 SIM_VOLATILE_USHORT_POINTER(0x62 + SIM_CRB)
|
||||
#define CSOR6 SIM_VOLATILE_USHORT_POINTER(0x66 + SIM_CRB)
|
||||
#define CSOR7 SIM_VOLATILE_USHORT_POINTER(0x6a + SIM_CRB)
|
||||
#define CSOR8 SIM_VOLATILE_USHORT_POINTER(0x6e + SIM_CRB)
|
||||
#define CSOR9 SIM_VOLATILE_USHORT_POINTER(0x72 + SIM_CRB)
|
||||
#define CSOR10 SIM_VOLATILE_USHORT_POINTER(0x76 + SIM_CRB)
|
||||
#define CSORBT (volatile unsigned short int * const)(0x4a + SIM_CRB)
|
||||
#define CSOR0 (volatile unsigned short int * const)(0x4e + SIM_CRB)
|
||||
#define CSOR1 (volatile unsigned short int * const)(0x52 + SIM_CRB)
|
||||
#define CSOR2 (volatile unsigned short int * const)(0x56 + SIM_CRB)
|
||||
#define CSOR3 (volatile unsigned short int * const)(0x5a + SIM_CRB)
|
||||
#define CSOR4 (volatile unsigned short int * const)(0x5e + SIM_CRB)
|
||||
#define CSOR5 (volatile unsigned short int * const)(0x62 + SIM_CRB)
|
||||
#define CSOR6 (volatile unsigned short int * const)(0x66 + SIM_CRB)
|
||||
#define CSOR7 (volatile unsigned short int * const)(0x6a + SIM_CRB)
|
||||
#define CSOR8 (volatile unsigned short int * const)(0x6e + SIM_CRB)
|
||||
#define CSOR9 (volatile unsigned short int * const)(0x72 + SIM_CRB)
|
||||
#define CSOR10 (volatile unsigned short int * const)(0x76 + SIM_CRB)
|
||||
|
||||
#endif /* _SIM_h_ */
|
||||
|
||||
@@ -137,7 +137,7 @@ void _CPU_Install_interrupt_stack( void )
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* _CPU_Thread_Idle_body
|
||||
* _CPU_Internal_threads_Idle_thread_body
|
||||
*
|
||||
* NOTES:
|
||||
*
|
||||
@@ -152,7 +152,7 @@ void _CPU_Install_interrupt_stack( void )
|
||||
* hook with caution.
|
||||
*/
|
||||
|
||||
void _CPU_Thread_Idle_body( void )
|
||||
void _CPU_Internal_threads_Idle_thread_body( void )
|
||||
{
|
||||
|
||||
for( ; ; )
|
||||
|
||||
@@ -207,9 +207,9 @@ extern "C" {
|
||||
/*
|
||||
* Does this port provide a CPU dependent IDLE task implementation?
|
||||
*
|
||||
* If TRUE, then the routine _CPU_Thread_Idle_body
|
||||
* If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
|
||||
* must be provided and is the default IDLE thread body instead of
|
||||
* _CPU_Thread_Idle_body.
|
||||
* _Internal_threads_Idle_thread_body.
|
||||
*
|
||||
* If FALSE, then use the generic IDLE thread body if the BSP does
|
||||
* not provide one.
|
||||
@@ -328,6 +328,12 @@ typedef struct {
|
||||
/*
|
||||
* The following table contains the information required to configure
|
||||
* the XXX processor specific parameters.
|
||||
*
|
||||
* NOTE: The interrupt_stack_size field is required if
|
||||
* CPU_ALLOCATE_INTERRUPT_STACK is defined as TRUE.
|
||||
*
|
||||
* The pretasking_hook, predriver_hook, and postdriver_hook,
|
||||
* and the do_zero_of_workspace fields are required on ALL CPUs.
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
@@ -337,11 +343,7 @@ typedef struct {
|
||||
void (*idle_task)( void );
|
||||
boolean do_zero_of_workspace;
|
||||
unsigned32 interrupt_stack_size;
|
||||
unsigned32 extra_mpci_receive_server_stack;
|
||||
void * (*stack_allocate_hook)( unsigned32 );
|
||||
void (*stack_free_hook)( void* );
|
||||
/* end of fields required on all CPUs */
|
||||
|
||||
unsigned32 extra_system_initialization_stack;
|
||||
unsigned32 some_other_cpu_dependent_info;
|
||||
} rtems_cpu_table;
|
||||
|
||||
@@ -352,7 +354,7 @@ typedef struct {
|
||||
* _CPU_Context_Initialize.
|
||||
*/
|
||||
|
||||
SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
|
||||
EXTERN Context_Control_fp _CPU_Null_fp_context;
|
||||
|
||||
/*
|
||||
* On some CPUs, RTEMS supports a software managed interrupt stack.
|
||||
@@ -367,8 +369,8 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
|
||||
* CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
|
||||
*/
|
||||
|
||||
SCORE_EXTERN void *_CPU_Interrupt_stack_low;
|
||||
SCORE_EXTERN void *_CPU_Interrupt_stack_high;
|
||||
EXTERN void *_CPU_Interrupt_stack_low;
|
||||
EXTERN void *_CPU_Interrupt_stack_high;
|
||||
|
||||
/*
|
||||
* With some compilation systems, it is difficult if not impossible to
|
||||
@@ -380,7 +382,7 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high;
|
||||
* sequence (if a dispatch is necessary).
|
||||
*/
|
||||
|
||||
SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
|
||||
EXTERN void (*_CPU_Thread_dispatch_pointer)();
|
||||
|
||||
/*
|
||||
* Nothing prevents the porter from declaring more CPU specific variables.
|
||||
@@ -399,11 +401,11 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
|
||||
|
||||
/*
|
||||
* Amount of extra stack (above minimum stack size) required by
|
||||
* MPCI receive server thread. Remember that in a multiprocessor
|
||||
* system this thread must exist and be able to process all directives.
|
||||
* system initialization thread. Remember that in a multiprocessor
|
||||
* system the system intialization thread becomes the MP server thread.
|
||||
*/
|
||||
|
||||
#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
|
||||
#define CPU_SYSTEM_INITIALIZATION_THREAD_EXTRA_STACK 0
|
||||
|
||||
/*
|
||||
* This defines the number of entries in the ISR_Vector_table managed
|
||||
@@ -757,7 +759,7 @@ void _CPU_ISR_install_vector(
|
||||
void _CPU_Install_interrupt_stack( void );
|
||||
|
||||
/*
|
||||
* _CPU_Thread_Idle_body
|
||||
* _CPU_Internal_threads_Idle_thread_body
|
||||
*
|
||||
* This routine is the CPU dependent IDLE thread body.
|
||||
*
|
||||
@@ -765,7 +767,7 @@ void _CPU_Install_interrupt_stack( void );
|
||||
* is TRUE.
|
||||
*/
|
||||
|
||||
void _CPU_Thread_Idle_body( void );
|
||||
void _CPU_Internal_threads_Idle_thread_body( void );
|
||||
|
||||
/*
|
||||
* _CPU_Context_switch
|
||||
|
||||
@@ -149,7 +149,6 @@ void _ISR_Handler()
|
||||
* goto the label "exit interrupt (simple case)"
|
||||
*
|
||||
* if ( !_ISR_Signals_to_thread_executing )
|
||||
* _ISR_Signals_to_thread_executing = FALSE;
|
||||
* goto the label "exit interrupt (simple case)"
|
||||
*
|
||||
* call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
|
||||
|
||||
@@ -1,110 +0,0 @@
|
||||
#
|
||||
# $Id$
|
||||
#
|
||||
|
||||
This file discusses SPARC specific issues which are important to
|
||||
this port. The primary topics in this file are:
|
||||
|
||||
+ Global Register Usage
|
||||
+ Stack Frame
|
||||
+ EF bit in the PSR
|
||||
|
||||
|
||||
Global Register Usage
|
||||
=====================
|
||||
|
||||
This information on register usage is based heavily on a comment in the
|
||||
file gcc-2.7.0/config/sparc/sparc.h in the the gcc 2.7.0 source.
|
||||
|
||||
+ g0 is hardwired to 0
|
||||
+ On non-v9 systems:
|
||||
- g1 is free to use as temporary.
|
||||
- g2-g4 are reserved for applications. Gcc normally uses them as
|
||||
temporaries, but this can be disabled via the -mno-app-regs option.
|
||||
- g5 through g7 are reserved for the operating system.
|
||||
+ On v9 systems:
|
||||
- g1 and g5 are free to use as temporaries.
|
||||
- g2-g4 are reserved for applications (the compiler will not normally use
|
||||
them, but they can be used as temporaries with -mapp-regs).
|
||||
- g6-g7 are reserved for the operating system.
|
||||
|
||||
NOTE: As of gcc 2.7.0 register g1 was used in the following scenarios:
|
||||
|
||||
+ as a temporary by the 64 bit sethi pattern
|
||||
+ when restoring call-preserved registers in large stack frames
|
||||
|
||||
RTEMS places no constraints on the usage of the global registers. Although
|
||||
gcc assumes that either g5-g7 (non-V9) or g6-g7 (V9) are reserved for the
|
||||
operating system, RTEMS does not assume any special use for them.
|
||||
|
||||
|
||||
|
||||
Stack Frame
|
||||
===========
|
||||
|
||||
The stack grows downward (i.e. to lower addresses) on the SPARC architecture.
|
||||
|
||||
The following is the organization of the stack frame:
|
||||
|
||||
|
||||
|
||||
| ............... |
|
||||
fp | |
|
||||
+-------------------------------+
|
||||
| |
|
||||
| Local registers, temporaries, |
|
||||
| and saved floats | x bytes
|
||||
| |
|
||||
sp + x +-------------------------------+
|
||||
| |
|
||||
| outgoing parameters past |
|
||||
| the sixth one | x bytes
|
||||
| |
|
||||
sp + 92 +-------------------------------+ *
|
||||
| | *
|
||||
| area for callee to save | *
|
||||
| register arguments | * 24 bytes
|
||||
| | *
|
||||
sp + 68 +-------------------------------+ *
|
||||
| | *
|
||||
| structure return pointer | * 4 bytes
|
||||
| | *
|
||||
sp + 64 +-------------------------------+ *
|
||||
| | *
|
||||
| local register set | * 32 bytes
|
||||
| | *
|
||||
sp + 32 +-------------------------------+ *
|
||||
| | *
|
||||
| input register set | * 32 bytes
|
||||
| | *
|
||||
sp +-------------------------------+ *
|
||||
|
||||
|
||||
* = minimal stack frame
|
||||
|
||||
x = optional components
|
||||
|
||||
EF bit in the PSR
|
||||
=================
|
||||
|
||||
The EF (enable floating point unit) in the PSR is utilized in this port to
|
||||
prevent non-floating point tasks from performing floating point
|
||||
operations. This bit is maintained as part of the integer context.
|
||||
However, the floating point context is switched BEFORE the integer
|
||||
context. Thus the EF bit in place at the time of the FP switch may
|
||||
indicate that FP operations are disabled. This occurs on certain task
|
||||
switches, when the EF bit will be 0 for the outgoing task and thus a fault
|
||||
will be generated on the first FP operation of the FP context save.
|
||||
|
||||
The remedy for this is to enable FP access as the first step in both the
|
||||
save and restore of the FP context area. This bit will be subsequently
|
||||
reloaded by the integer context switch.
|
||||
|
||||
Two of the scenarios which demonstrate this problem are outlined below:
|
||||
|
||||
1. When the first FP task is switched to. The system tasks are not FP and
|
||||
thus would be unable to restore the FP context of the incoming task.
|
||||
|
||||
2. On a deferred FP context switch. In this case, the system might switch
|
||||
from FP Task A to non-FP Task B and then to FP Task C. In this scenario,
|
||||
the floating point state must technically be saved by a non-FP task.
|
||||
@@ -1,111 +0,0 @@
|
||||
/* asm.h
|
||||
*
|
||||
* This include file attempts to address the problems
|
||||
* caused by incompatible flavors of assemblers and
|
||||
* toolsets. It primarily addresses variations in the
|
||||
* use of leading underscores on symbols and the requirement
|
||||
* that register names be preceded by a %.
|
||||
*
|
||||
*
|
||||
* NOTE: The spacing in the use of these macros
|
||||
* is critical to them working as advertised.
|
||||
*
|
||||
* COPYRIGHT:
|
||||
*
|
||||
* This file is based on similar code found in newlib available
|
||||
* from ftp.cygnus.com. The file which was used had no copyright
|
||||
* notice. This file is freely distributable as long as the source
|
||||
* of the file is noted.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef __SPARC_ASM_h
|
||||
#define __SPARC_ASM_h
|
||||
|
||||
/*
|
||||
* Indicate we are in an assembly file and get the basic CPU definitions.
|
||||
*/
|
||||
|
||||
#define ASM
|
||||
|
||||
#include <rtems/score/sparc.h>
|
||||
#include <rtems/score/cpu.h>
|
||||
|
||||
/*
|
||||
* Recent versions of GNU cpp define variables which indicate the
|
||||
* need for underscores and percents. If not using GNU cpp or
|
||||
* the version does not support this, then you will obviously
|
||||
* have to define these as appropriate.
|
||||
*/
|
||||
|
||||
/* XXX __USER_LABEL_PREFIX__ and __REGISTER_PREFIX__ do not work on gcc 2.7.0 */
|
||||
/* XXX The following ifdef magic fixes the problem but results in a warning */
|
||||
/* XXX when compiling assembly code. */
|
||||
#undef __USER_LABEL_PREFIX__
|
||||
#ifndef __USER_LABEL_PREFIX__
|
||||
#define __USER_LABEL_PREFIX__ _
|
||||
#endif
|
||||
|
||||
#ifndef __REGISTER_PREFIX__
|
||||
#define __REGISTER_PREFIX__
|
||||
#endif
|
||||
|
||||
/* ANSI concatenation macros. */
|
||||
|
||||
#define CONCAT1(a, b) CONCAT2(a, b)
|
||||
#define CONCAT2(a, b) a ## b
|
||||
|
||||
/* Use the right prefix for global labels. */
|
||||
|
||||
#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
|
||||
|
||||
/* Use the right prefix for registers. */
|
||||
|
||||
#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
|
||||
|
||||
/*
|
||||
* define macros for all of the registers on this CPU
|
||||
*
|
||||
* EXAMPLE: #define d0 REG (d0)
|
||||
*/
|
||||
|
||||
/*
|
||||
* Define macros to handle section beginning and ends.
|
||||
*/
|
||||
|
||||
|
||||
#define BEGIN_CODE_DCL .text
|
||||
#define END_CODE_DCL
|
||||
#define BEGIN_DATA_DCL .data
|
||||
#define END_DATA_DCL
|
||||
#define BEGIN_CODE .text
|
||||
#define END_CODE
|
||||
#define BEGIN_DATA
|
||||
#define END_DATA
|
||||
#define BEGIN_BSS
|
||||
#define END_BSS
|
||||
#define END
|
||||
|
||||
/*
|
||||
* Following must be tailor for a particular flavor of the C compiler.
|
||||
* They may need to put underscores in front of the symbols.
|
||||
*/
|
||||
|
||||
#define PUBLIC(sym) .globl SYM (sym)
|
||||
#define EXTERN(sym) .globl SYM (sym)
|
||||
|
||||
/*
|
||||
* Entry for traps which jump to a programmer-specified trap handler.
|
||||
*/
|
||||
|
||||
#define TRAP(_vector, _handler) \
|
||||
mov %psr, %l0 ; \
|
||||
sethi %hi(_handler), %l4 ; \
|
||||
jmp %l4+%lo(_handler); \
|
||||
mov _vector, %l3
|
||||
|
||||
#endif
|
||||
/* end of include file */
|
||||
|
||||
|
||||
@@ -1,404 +0,0 @@
|
||||
/*
|
||||
* SPARC Dependent Source
|
||||
*
|
||||
* COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
* All rights assigned to U.S. Government, 1994.
|
||||
*
|
||||
* This material may be reproduced by or for the U.S. Government pursuant
|
||||
* to the copyright license under the clause at DFARS 252.227-7013. This
|
||||
* notice must appear in all copies of this file and its derivatives.
|
||||
*
|
||||
* Ported to ERC32 implementation of the SPARC by On-Line Applications
|
||||
* Research Corporation (OAR) under contract to the European Space
|
||||
* Agency (ESA).
|
||||
*
|
||||
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
|
||||
* European Space Agency.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <rtems/system.h>
|
||||
#include <rtems/score/isr.h>
|
||||
|
||||
#if defined(erc32)
|
||||
#include <erc32.h>
|
||||
#endif
|
||||
|
||||
/*
|
||||
* This initializes the set of opcodes placed in each trap
|
||||
* table entry. The routine which installs a handler is responsible
|
||||
* for filling in the fields for the _handler address and the _vector
|
||||
* trap type.
|
||||
*
|
||||
* The constants following this structure are masks for the fields which
|
||||
* must be filled in when the handler is installed.
|
||||
*/
|
||||
|
||||
const CPU_Trap_table_entry _CPU_Trap_slot_template = {
|
||||
0xa1480000, /* mov %psr, %l0 */
|
||||
0x29000000, /* sethi %hi(_handler), %l4 */
|
||||
0x81c52000, /* jmp %l4 + %lo(_handler) */
|
||||
0xa6102000 /* mov _vector, %l3 */
|
||||
};
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* _CPU_Initialize
|
||||
*
|
||||
* This routine performs processor dependent initialization.
|
||||
*
|
||||
* Input Parameters:
|
||||
* cpu_table - CPU table to initialize
|
||||
* thread_dispatch - address of disptaching routine
|
||||
*
|
||||
* Output Parameters: NONE
|
||||
*
|
||||
* NOTE: There is no need to save the pointer to the thread dispatch routine.
|
||||
* The SPARC's assembly code can reference it directly with no problems.
|
||||
*/
|
||||
|
||||
void _CPU_Initialize(
|
||||
rtems_cpu_table *cpu_table,
|
||||
void (*thread_dispatch) /* ignored on this CPU */
|
||||
)
|
||||
{
|
||||
void *pointer;
|
||||
unsigned32 trap_table_start;
|
||||
unsigned32 tbr_value;
|
||||
CPU_Trap_table_entry *old_tbr;
|
||||
CPU_Trap_table_entry *trap_table;
|
||||
|
||||
/*
|
||||
* Install the executive's trap table. All entries from the original
|
||||
* trap table are copied into the executive's trap table. This is essential
|
||||
* since this preserves critical trap handlers such as the window underflow
|
||||
* and overflow handlers. It is the responsibility of the BSP to provide
|
||||
* install these in the initial trap table.
|
||||
*/
|
||||
|
||||
trap_table_start = (unsigned32) &_CPU_Trap_Table_area;
|
||||
if (trap_table_start & (SPARC_TRAP_TABLE_ALIGNMENT-1))
|
||||
trap_table_start = (trap_table_start + SPARC_TRAP_TABLE_ALIGNMENT) &
|
||||
~(SPARC_TRAP_TABLE_ALIGNMENT-1);
|
||||
|
||||
trap_table = (CPU_Trap_table_entry *) trap_table_start;
|
||||
|
||||
sparc_get_tbr( tbr_value );
|
||||
|
||||
old_tbr = (CPU_Trap_table_entry *) (tbr_value & 0xfffff000);
|
||||
|
||||
memcpy( trap_table, (void *) old_tbr, 256 * sizeof( CPU_Trap_table_entry ) );
|
||||
|
||||
sparc_set_tbr( trap_table_start );
|
||||
|
||||
/*
|
||||
* This seems to be the most appropriate way to obtain an initial
|
||||
* FP context on the SPARC. The NULL fp context is copied it to
|
||||
* the task's FP context during Context_Initialize.
|
||||
*/
|
||||
|
||||
pointer = &_CPU_Null_fp_context;
|
||||
_CPU_Context_save_fp( &pointer );
|
||||
|
||||
/*
|
||||
* Grab our own copy of the user's CPU table.
|
||||
*/
|
||||
|
||||
_CPU_Table = *cpu_table;
|
||||
|
||||
#if defined(erc32)
|
||||
|
||||
/*
|
||||
* ERC32 specific initialization
|
||||
*/
|
||||
|
||||
_ERC32_MEC_Timer_Control_Mirror = 0;
|
||||
ERC32_MEC.Timer_Control = 0;
|
||||
|
||||
ERC32_MEC.Control |= ERC32_CONFIGURATION_POWER_DOWN_ALLOWED;
|
||||
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* _CPU_ISR_Get_level
|
||||
*
|
||||
* Input Parameters: NONE
|
||||
*
|
||||
* Output Parameters:
|
||||
* returns the current interrupt level (PIL field of the PSR)
|
||||
*/
|
||||
|
||||
unsigned32 _CPU_ISR_Get_level( void )
|
||||
{
|
||||
unsigned32 level;
|
||||
|
||||
sparc_get_interrupt_level( level );
|
||||
|
||||
return level;
|
||||
}
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* _CPU_ISR_install_raw_handler
|
||||
*
|
||||
* This routine installs the specified handler as a "raw" non-executive
|
||||
* supported trap handler (a.k.a. interrupt service routine).
|
||||
*
|
||||
* Input Parameters:
|
||||
* vector - trap table entry number plus synchronous
|
||||
* vs. asynchronous information
|
||||
* new_handler - address of the handler to be installed
|
||||
* old_handler - pointer to an address of the handler previously installed
|
||||
*
|
||||
* Output Parameters: NONE
|
||||
* *new_handler - address of the handler previously installed
|
||||
*
|
||||
* NOTE:
|
||||
*
|
||||
* On the SPARC, there are really only 256 vectors. However, the executive
|
||||
* has no easy, fast, reliable way to determine which traps are synchronous
|
||||
* and which are asynchronous. By default, synchronous traps return to the
|
||||
* instruction which caused the interrupt. So if you install a software
|
||||
* trap handler as an executive interrupt handler (which is desirable since
|
||||
* RTEMS takes care of window and register issues), then the executive needs
|
||||
* to know that the return address is to the trap rather than the instruction
|
||||
* following the trap.
|
||||
*
|
||||
* So vectors 0 through 255 are treated as regular asynchronous traps which
|
||||
* provide the "correct" return address. Vectors 256 through 512 are assumed
|
||||
* by the executive to be synchronous and to require that the return address
|
||||
* be fudged.
|
||||
*
|
||||
* If you use this mechanism to install a trap handler which must reexecute
|
||||
* the instruction which caused the trap, then it should be installed as
|
||||
* an asynchronous trap. This will avoid the executive changing the return
|
||||
* address.
|
||||
*/
|
||||
|
||||
void _CPU_ISR_install_raw_handler(
|
||||
unsigned32 vector,
|
||||
proc_ptr new_handler,
|
||||
proc_ptr *old_handler
|
||||
)
|
||||
{
|
||||
unsigned32 real_vector;
|
||||
CPU_Trap_table_entry *tbr;
|
||||
CPU_Trap_table_entry *slot;
|
||||
unsigned32 u32_tbr;
|
||||
unsigned32 u32_handler;
|
||||
|
||||
/*
|
||||
* Get the "real" trap number for this vector ignoring the synchronous
|
||||
* versus asynchronous indicator included with our vector numbers.
|
||||
*/
|
||||
|
||||
real_vector = SPARC_REAL_TRAP_NUMBER( vector );
|
||||
|
||||
/*
|
||||
* Get the current base address of the trap table and calculate a pointer
|
||||
* to the slot we are interested in.
|
||||
*/
|
||||
|
||||
sparc_get_tbr( u32_tbr );
|
||||
|
||||
u32_tbr &= 0xfffff000;
|
||||
|
||||
tbr = (CPU_Trap_table_entry *) u32_tbr;
|
||||
|
||||
slot = &tbr[ real_vector ];
|
||||
|
||||
/*
|
||||
* Get the address of the old_handler from the trap table.
|
||||
*
|
||||
* NOTE: The old_handler returned will be bogus if it does not follow
|
||||
* the RTEMS model.
|
||||
*/
|
||||
|
||||
#define HIGH_BITS_MASK 0xFFFFFC00
|
||||
#define HIGH_BITS_SHIFT 10
|
||||
#define LOW_BITS_MASK 0x000003FF
|
||||
|
||||
if ( slot->mov_psr_l0 == _CPU_Trap_slot_template.mov_psr_l0 ) {
|
||||
u32_handler =
|
||||
((slot->sethi_of_handler_to_l4 & HIGH_BITS_MASK) << HIGH_BITS_SHIFT) |
|
||||
(slot->jmp_to_low_of_handler_plus_l4 & LOW_BITS_MASK);
|
||||
*old_handler = (proc_ptr) u32_handler;
|
||||
} else
|
||||
*old_handler = 0;
|
||||
|
||||
/*
|
||||
* Copy the template to the slot and then fix it.
|
||||
*/
|
||||
|
||||
*slot = _CPU_Trap_slot_template;
|
||||
|
||||
u32_handler = (unsigned32) new_handler;
|
||||
|
||||
slot->mov_vector_l3 |= vector;
|
||||
slot->sethi_of_handler_to_l4 |=
|
||||
(u32_handler & HIGH_BITS_MASK) >> HIGH_BITS_SHIFT;
|
||||
slot->jmp_to_low_of_handler_plus_l4 |= (u32_handler & LOW_BITS_MASK);
|
||||
}
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* _CPU_ISR_install_vector
|
||||
*
|
||||
* This kernel routine installs the RTEMS handler for the
|
||||
* specified vector.
|
||||
*
|
||||
* Input parameters:
|
||||
* vector - interrupt vector number
|
||||
* new_handler - replacement ISR for this vector number
|
||||
* old_handler - pointer to former ISR for this vector number
|
||||
*
|
||||
* Output parameters:
|
||||
* *old_handler - former ISR for this vector number
|
||||
*
|
||||
*/
|
||||
|
||||
void _CPU_ISR_install_vector(
|
||||
unsigned32 vector,
|
||||
proc_ptr new_handler,
|
||||
proc_ptr *old_handler
|
||||
)
|
||||
{
|
||||
unsigned32 real_vector;
|
||||
proc_ptr ignored;
|
||||
|
||||
/*
|
||||
* Get the "real" trap number for this vector ignoring the synchronous
|
||||
* versus asynchronous indicator included with our vector numbers.
|
||||
*/
|
||||
|
||||
real_vector = SPARC_REAL_TRAP_NUMBER( vector );
|
||||
|
||||
/*
|
||||
* Return the previous ISR handler.
|
||||
*/
|
||||
|
||||
*old_handler = _ISR_Vector_table[ real_vector ];
|
||||
|
||||
/*
|
||||
* Install the wrapper so this ISR can be invoked properly.
|
||||
*/
|
||||
|
||||
_CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
|
||||
|
||||
/*
|
||||
* We put the actual user ISR address in '_ISR_vector_table'. This will
|
||||
* be used by the _ISR_Handler so the user gets control.
|
||||
*/
|
||||
|
||||
_ISR_Vector_table[ real_vector ] = new_handler;
|
||||
}
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* _CPU_Context_Initialize
|
||||
*
|
||||
* This kernel routine initializes the basic non-FP context area associated
|
||||
* with each thread.
|
||||
*
|
||||
* Input parameters:
|
||||
* the_context - pointer to the context area
|
||||
* stack_base - address of memory for the SPARC
|
||||
* size - size in bytes of the stack area
|
||||
* new_level - interrupt level for this context area
|
||||
* entry_point - the starting execution point for this this context
|
||||
* is_fp - TRUE if this context is associated with an FP thread
|
||||
*
|
||||
* Output parameters: NONE
|
||||
*/
|
||||
|
||||
void _CPU_Context_Initialize(
|
||||
Context_Control *the_context,
|
||||
unsigned32 *stack_base,
|
||||
unsigned32 size,
|
||||
unsigned32 new_level,
|
||||
void *entry_point,
|
||||
boolean is_fp
|
||||
)
|
||||
{
|
||||
unsigned32 stack_high; /* highest "stack aligned" address */
|
||||
unsigned32 the_size;
|
||||
unsigned32 tmp_psr;
|
||||
|
||||
/*
|
||||
* On CPUs with stacks which grow down (i.e. SPARC), we build the stack
|
||||
* based on the stack_high address.
|
||||
*/
|
||||
|
||||
stack_high = ((unsigned32)(stack_base) + size);
|
||||
stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
|
||||
|
||||
the_size = size & ~(CPU_STACK_ALIGNMENT - 1);
|
||||
|
||||
/*
|
||||
* See the README in this directory for a diagram of the stack.
|
||||
*/
|
||||
|
||||
the_context->o7 = ((unsigned32) entry_point) - 8;
|
||||
the_context->o6_sp = stack_high - CPU_MINIMUM_STACK_FRAME_SIZE;
|
||||
the_context->i6_fp = stack_high;
|
||||
|
||||
/*
|
||||
* Build the PSR for the task. Most everything can be 0 and the
|
||||
* CWP is corrected during the context switch.
|
||||
*
|
||||
* The EF bit determines if the floating point unit is available.
|
||||
* The FPU is ONLY enabled if the context is associated with an FP task
|
||||
* and this SPARC model has an FPU.
|
||||
*/
|
||||
|
||||
sparc_get_psr( tmp_psr );
|
||||
tmp_psr &= ~SPARC_PSR_PIL_MASK;
|
||||
tmp_psr |= (new_level << 8) & SPARC_PSR_PIL_MASK;
|
||||
tmp_psr &= ~SPARC_PSR_EF_MASK; /* disabled by default */
|
||||
|
||||
#if (SPARC_HAS_FPU == 1)
|
||||
/*
|
||||
* If this bit is not set, then a task gets a fault when it accesses
|
||||
* a floating point register. This is a nice way to detect floating
|
||||
* point tasks which are not currently declared as such.
|
||||
*/
|
||||
|
||||
if ( is_fp )
|
||||
tmp_psr |= SPARC_PSR_EF_MASK;
|
||||
#endif
|
||||
the_context->psr = tmp_psr;
|
||||
}
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* _CPU_Thread_Idle_body
|
||||
*
|
||||
* Some SPARC implementations have low power, sleep, or idle modes. This
|
||||
* tries to take advantage of those models.
|
||||
*/
|
||||
|
||||
#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
|
||||
|
||||
/*
|
||||
* This is the implementation for the erc32.
|
||||
*
|
||||
* NOTE: Low power mode was enabled at initialization time.
|
||||
*/
|
||||
|
||||
#if defined(erc32)
|
||||
|
||||
void _CPU_Thread_Idle_body( void )
|
||||
{
|
||||
while (1) {
|
||||
ERC32_MEC.Power_Down = 0; /* value is irrelevant */
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* CPU_PROVIDES_IDLE_THREAD_BODY */
|
||||
@@ -1,991 +0,0 @@
|
||||
/* cpu.h
|
||||
*
|
||||
* This include file contains information pertaining to the port of
|
||||
* the executive to the SPARC processor.
|
||||
*
|
||||
* COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
* All rights assigned to U.S. Government, 1994.
|
||||
*
|
||||
* This material may be reproduced by or for the U.S. Government pursuant
|
||||
* to the copyright license under the clause at DFARS 252.227-7013. This
|
||||
* notice must appear in all copies of this file and its derivatives.
|
||||
*
|
||||
* Ported to ERC32 implementation of the SPARC by On-Line Applications
|
||||
* Research Corporation (OAR) under contract to the European Space
|
||||
* Agency (ESA).
|
||||
*
|
||||
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
|
||||
* European Space Agency.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef __CPU_h
|
||||
#define __CPU_h
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <rtems/score/sparc.h> /* pick up machine definitions */
|
||||
#ifndef ASM
|
||||
#include <rtems/score/sparctypes.h>
|
||||
#endif
|
||||
|
||||
/* conditional compilation parameters */
|
||||
|
||||
/*
|
||||
* Should the calls to _Thread_Enable_dispatch be inlined?
|
||||
*
|
||||
* If TRUE, then they are inlined.
|
||||
* If FALSE, then a subroutine call is made.
|
||||
*/
|
||||
|
||||
#define CPU_INLINE_ENABLE_DISPATCH TRUE
|
||||
|
||||
/*
|
||||
* Should the body of the search loops in _Thread_queue_Enqueue_priority
|
||||
* be unrolled one time? In unrolled each iteration of the loop examines
|
||||
* two "nodes" on the chain being searched. Otherwise, only one node
|
||||
* is examined per iteration.
|
||||
*
|
||||
* If TRUE, then the loops are unrolled.
|
||||
* If FALSE, then the loops are not unrolled.
|
||||
*
|
||||
* This parameter could go either way on the SPARC. The interrupt flash
|
||||
* code is relatively lengthy given the requirements for nops following
|
||||
* writes to the psr. But if the clock speed were high enough, this would
|
||||
* not represent a great deal of time.
|
||||
*/
|
||||
|
||||
#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE
|
||||
|
||||
/*
|
||||
* Does the executive manage a dedicated interrupt stack in software?
|
||||
*
|
||||
* If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
|
||||
* If FALSE, nothing is done.
|
||||
*
|
||||
* The SPARC does not have a dedicated HW interrupt stack and one has
|
||||
* been implemented in SW.
|
||||
*/
|
||||
|
||||
#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
|
||||
|
||||
/*
|
||||
* Does this CPU have hardware support for a dedicated interrupt stack?
|
||||
*
|
||||
* If TRUE, then it must be installed during initialization.
|
||||
* If FALSE, then no installation is performed.
|
||||
*
|
||||
* The SPARC does not have a dedicated HW interrupt stack.
|
||||
*/
|
||||
|
||||
#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
|
||||
|
||||
/*
|
||||
* Do we allocate a dedicated interrupt stack in the Interrupt Manager?
|
||||
*
|
||||
* If TRUE, then the memory is allocated during initialization.
|
||||
* If FALSE, then the memory is allocated during initialization.
|
||||
*/
|
||||
|
||||
#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
|
||||
|
||||
/*
|
||||
* Does the CPU have hardware floating point?
|
||||
*
|
||||
* If TRUE, then the FLOATING_POINT task attribute is supported.
|
||||
* If FALSE, then the FLOATING_POINT task attribute is ignored.
|
||||
*/
|
||||
|
||||
#if ( SPARC_HAS_FPU == 1 )
|
||||
#define CPU_HARDWARE_FP TRUE
|
||||
#else
|
||||
#define CPU_HARDWARE_FP FALSE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Are all tasks FLOATING_POINT tasks implicitly?
|
||||
*
|
||||
* If TRUE, then the FLOATING_POINT task attribute is assumed.
|
||||
* If FALSE, then the FLOATING_POINT task attribute is followed.
|
||||
*/
|
||||
|
||||
#define CPU_ALL_TASKS_ARE_FP FALSE
|
||||
|
||||
/*
|
||||
* Should the IDLE task have a floating point context?
|
||||
*
|
||||
* If TRUE, then the IDLE task is created as a FLOATING_POINT task
|
||||
* and it has a floating point context which is switched in and out.
|
||||
* If FALSE, then the IDLE task does not have a floating point context.
|
||||
*/
|
||||
|
||||
#define CPU_IDLE_TASK_IS_FP FALSE
|
||||
|
||||
/*
|
||||
* Should the saving of the floating point registers be deferred
|
||||
* until a context switch is made to another different floating point
|
||||
* task?
|
||||
*
|
||||
* If TRUE, then the floating point context will not be stored until
|
||||
* necessary. It will remain in the floating point registers and not
|
||||
* disturned until another floating point task is switched to.
|
||||
*
|
||||
* If FALSE, then the floating point context is saved when a floating
|
||||
* point task is switched out and restored when the next floating point
|
||||
* task is restored. The state of the floating point registers between
|
||||
* those two operations is not specified.
|
||||
*/
|
||||
|
||||
#define CPU_USE_DEFERRED_FP_SWITCH TRUE
|
||||
|
||||
/*
|
||||
* Does this port provide a CPU dependent IDLE task implementation?
|
||||
*
|
||||
* If TRUE, then the routine _CPU_Thread_Idle_body
|
||||
* must be provided and is the default IDLE thread body instead of
|
||||
* _CPU_Thread_Idle_body.
|
||||
*
|
||||
* If FALSE, then use the generic IDLE thread body if the BSP does
|
||||
* not provide one.
|
||||
*/
|
||||
|
||||
#if (SPARC_HAS_LOW_POWER_MODE == 1)
|
||||
#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE
|
||||
#else
|
||||
#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Does the stack grow up (toward higher addresses) or down
|
||||
* (toward lower addresses)?
|
||||
*
|
||||
* If TRUE, then the grows upward.
|
||||
* If FALSE, then the grows toward smaller addresses.
|
||||
*
|
||||
* The stack grows to lower addresses on the SPARC.
|
||||
*/
|
||||
|
||||
#define CPU_STACK_GROWS_UP FALSE
|
||||
|
||||
/*
|
||||
* The following is the variable attribute used to force alignment
|
||||
* of critical data structures. On some processors it may make
|
||||
* sense to have these aligned on tighter boundaries than
|
||||
* the minimum requirements of the compiler in order to have as
|
||||
* much of the critical data area as possible in a cache line.
|
||||
*
|
||||
* The SPARC does not appear to have particularly strict alignment
|
||||
* requirements. This value was chosen to take advantages of caches.
|
||||
*/
|
||||
|
||||
#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16)))
|
||||
|
||||
/*
|
||||
* The following defines the number of bits actually used in the
|
||||
* interrupt field of the task mode. How those bits map to the
|
||||
* CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
|
||||
*
|
||||
* The SPARC has 16 interrupt levels in the PIL field of the PSR.
|
||||
*/
|
||||
|
||||
#define CPU_MODES_INTERRUPT_MASK 0x0000000F
|
||||
|
||||
/*
|
||||
* This structure represents the organization of the minimum stack frame
|
||||
* for the SPARC. More framing information is required in certain situaions
|
||||
* such as when there are a large number of out parameters or when the callee
|
||||
* must save floating point registers.
|
||||
*/
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
typedef struct {
|
||||
unsigned32 l0;
|
||||
unsigned32 l1;
|
||||
unsigned32 l2;
|
||||
unsigned32 l3;
|
||||
unsigned32 l4;
|
||||
unsigned32 l5;
|
||||
unsigned32 l6;
|
||||
unsigned32 l7;
|
||||
unsigned32 i0;
|
||||
unsigned32 i1;
|
||||
unsigned32 i2;
|
||||
unsigned32 i3;
|
||||
unsigned32 i4;
|
||||
unsigned32 i5;
|
||||
unsigned32 i6_fp;
|
||||
unsigned32 i7;
|
||||
void *structure_return_address;
|
||||
/*
|
||||
* The following are for the callee to save the register arguments in
|
||||
* should this be necessary.
|
||||
*/
|
||||
unsigned32 saved_arg0;
|
||||
unsigned32 saved_arg1;
|
||||
unsigned32 saved_arg2;
|
||||
unsigned32 saved_arg3;
|
||||
unsigned32 saved_arg4;
|
||||
unsigned32 saved_arg5;
|
||||
unsigned32 pad0;
|
||||
} CPU_Minimum_stack_frame;
|
||||
|
||||
#endif /* ASM */
|
||||
|
||||
#define CPU_STACK_FRAME_L0_OFFSET 0x00
|
||||
#define CPU_STACK_FRAME_L1_OFFSET 0x04
|
||||
#define CPU_STACK_FRAME_L2_OFFSET 0x08
|
||||
#define CPU_STACK_FRAME_L3_OFFSET 0x0c
|
||||
#define CPU_STACK_FRAME_L4_OFFSET 0x10
|
||||
#define CPU_STACK_FRAME_L5_OFFSET 0x14
|
||||
#define CPU_STACK_FRAME_L6_OFFSET 0x18
|
||||
#define CPU_STACK_FRAME_L7_OFFSET 0x1c
|
||||
#define CPU_STACK_FRAME_I0_OFFSET 0x20
|
||||
#define CPU_STACK_FRAME_I1_OFFSET 0x24
|
||||
#define CPU_STACK_FRAME_I2_OFFSET 0x28
|
||||
#define CPU_STACK_FRAME_I3_OFFSET 0x2c
|
||||
#define CPU_STACK_FRAME_I4_OFFSET 0x30
|
||||
#define CPU_STACK_FRAME_I5_OFFSET 0x34
|
||||
#define CPU_STACK_FRAME_I6_FP_OFFSET 0x38
|
||||
#define CPU_STACK_FRAME_I7_OFFSET 0x3c
|
||||
#define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET 0x40
|
||||
#define CPU_STACK_FRAME_SAVED_ARG0_OFFSET 0x44
|
||||
#define CPU_STACK_FRAME_SAVED_ARG1_OFFSET 0x48
|
||||
#define CPU_STACK_FRAME_SAVED_ARG2_OFFSET 0x4c
|
||||
#define CPU_STACK_FRAME_SAVED_ARG3_OFFSET 0x50
|
||||
#define CPU_STACK_FRAME_SAVED_ARG4_OFFSET 0x54
|
||||
#define CPU_STACK_FRAME_SAVED_ARG5_OFFSET 0x58
|
||||
#define CPU_STACK_FRAME_PAD0_OFFSET 0x5c
|
||||
|
||||
#define CPU_MINIMUM_STACK_FRAME_SIZE 0x60
|
||||
|
||||
/*
|
||||
* Contexts
|
||||
*
|
||||
* Generally there are 2 types of context to save.
|
||||
* 1. Interrupt registers to save
|
||||
* 2. Task level registers to save
|
||||
*
|
||||
* This means we have the following 3 context items:
|
||||
* 1. task level context stuff:: Context_Control
|
||||
* 2. floating point task stuff:: Context_Control_fp
|
||||
* 3. special interrupt level context :: Context_Control_interrupt
|
||||
*
|
||||
* On the SPARC, we are relatively conservative in that we save most
|
||||
* of the CPU state in the context area. The ET (enable trap) bit and
|
||||
* the CWP (current window pointer) fields of the PSR are considered
|
||||
* system wide resources and are not maintained on a per-thread basis.
|
||||
*/
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
typedef struct {
|
||||
/*
|
||||
* Using a double g0_g1 will put everything in this structure on a
|
||||
* double word boundary which allows us to use double word loads
|
||||
* and stores safely in the context switch.
|
||||
*/
|
||||
double g0_g1;
|
||||
unsigned32 g2;
|
||||
unsigned32 g3;
|
||||
unsigned32 g4;
|
||||
unsigned32 g5;
|
||||
unsigned32 g6;
|
||||
unsigned32 g7;
|
||||
|
||||
unsigned32 l0;
|
||||
unsigned32 l1;
|
||||
unsigned32 l2;
|
||||
unsigned32 l3;
|
||||
unsigned32 l4;
|
||||
unsigned32 l5;
|
||||
unsigned32 l6;
|
||||
unsigned32 l7;
|
||||
|
||||
unsigned32 i0;
|
||||
unsigned32 i1;
|
||||
unsigned32 i2;
|
||||
unsigned32 i3;
|
||||
unsigned32 i4;
|
||||
unsigned32 i5;
|
||||
unsigned32 i6_fp;
|
||||
unsigned32 i7;
|
||||
|
||||
unsigned32 o0;
|
||||
unsigned32 o1;
|
||||
unsigned32 o2;
|
||||
unsigned32 o3;
|
||||
unsigned32 o4;
|
||||
unsigned32 o5;
|
||||
unsigned32 o6_sp;
|
||||
unsigned32 o7;
|
||||
|
||||
unsigned32 psr;
|
||||
} Context_Control;
|
||||
|
||||
#endif /* ASM */
|
||||
|
||||
/*
|
||||
* Offsets of fields with Context_Control for assembly routines.
|
||||
*/
|
||||
|
||||
#define G0_OFFSET 0x00
|
||||
#define G1_OFFSET 0x04
|
||||
#define G2_OFFSET 0x08
|
||||
#define G3_OFFSET 0x0C
|
||||
#define G4_OFFSET 0x10
|
||||
#define G5_OFFSET 0x14
|
||||
#define G6_OFFSET 0x18
|
||||
#define G7_OFFSET 0x1C
|
||||
|
||||
#define L0_OFFSET 0x20
|
||||
#define L1_OFFSET 0x24
|
||||
#define L2_OFFSET 0x28
|
||||
#define L3_OFFSET 0x2C
|
||||
#define L4_OFFSET 0x30
|
||||
#define L5_OFFSET 0x34
|
||||
#define L6_OFFSET 0x38
|
||||
#define L7_OFFSET 0x3C
|
||||
|
||||
#define I0_OFFSET 0x40
|
||||
#define I1_OFFSET 0x44
|
||||
#define I2_OFFSET 0x48
|
||||
#define I3_OFFSET 0x4C
|
||||
#define I4_OFFSET 0x50
|
||||
#define I5_OFFSET 0x54
|
||||
#define I6_FP_OFFSET 0x58
|
||||
#define I7_OFFSET 0x5C
|
||||
|
||||
#define O0_OFFSET 0x60
|
||||
#define O1_OFFSET 0x64
|
||||
#define O2_OFFSET 0x68
|
||||
#define O3_OFFSET 0x6C
|
||||
#define O4_OFFSET 0x70
|
||||
#define O5_OFFSET 0x74
|
||||
#define O6_SP_OFFSET 0x78
|
||||
#define O7_OFFSET 0x7C
|
||||
|
||||
#define PSR_OFFSET 0x80
|
||||
|
||||
#define CONTEXT_CONTROL_SIZE 0x84
|
||||
|
||||
/*
|
||||
* The floating point context area.
|
||||
*/
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
typedef struct {
|
||||
double f0_f1;
|
||||
double f2_f3;
|
||||
double f4_f5;
|
||||
double f6_f7;
|
||||
double f8_f9;
|
||||
double f10_f11;
|
||||
double f12_f13;
|
||||
double f14_f15;
|
||||
double f16_f17;
|
||||
double f18_f19;
|
||||
double f20_f21;
|
||||
double f22_f23;
|
||||
double f24_f25;
|
||||
double f26_f27;
|
||||
double f28_f29;
|
||||
double f30_f31;
|
||||
unsigned32 fsr;
|
||||
} Context_Control_fp;
|
||||
|
||||
#endif /* ASM */
|
||||
|
||||
/*
|
||||
* Offsets of fields with Context_Control_fp for assembly routines.
|
||||
*/
|
||||
|
||||
#define FO_F1_OFFSET 0x00
|
||||
#define F2_F3_OFFSET 0x08
|
||||
#define F4_F5_OFFSET 0x10
|
||||
#define F6_F7_OFFSET 0x18
|
||||
#define F8_F9_OFFSET 0x20
|
||||
#define F1O_F11_OFFSET 0x28
|
||||
#define F12_F13_OFFSET 0x30
|
||||
#define F14_F15_OFFSET 0x38
|
||||
#define F16_F17_OFFSET 0x40
|
||||
#define F18_F19_OFFSET 0x48
|
||||
#define F2O_F21_OFFSET 0x50
|
||||
#define F22_F23_OFFSET 0x58
|
||||
#define F24_F25_OFFSET 0x60
|
||||
#define F26_F27_OFFSET 0x68
|
||||
#define F28_F29_OFFSET 0x70
|
||||
#define F3O_F31_OFFSET 0x78
|
||||
#define FSR_OFFSET 0x80
|
||||
|
||||
#define CONTEXT_CONTROL_FP_SIZE 0x84
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
/*
|
||||
* Context saved on stack for an interrupt.
|
||||
*
|
||||
* NOTE: The PSR, PC, and NPC are only saved in this structure for the
|
||||
* benefit of the user's handler.
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
CPU_Minimum_stack_frame Stack_frame;
|
||||
unsigned32 psr;
|
||||
unsigned32 pc;
|
||||
unsigned32 npc;
|
||||
unsigned32 g1;
|
||||
unsigned32 g2;
|
||||
unsigned32 g3;
|
||||
unsigned32 g4;
|
||||
unsigned32 g5;
|
||||
unsigned32 g6;
|
||||
unsigned32 g7;
|
||||
unsigned32 i0;
|
||||
unsigned32 i1;
|
||||
unsigned32 i2;
|
||||
unsigned32 i3;
|
||||
unsigned32 i4;
|
||||
unsigned32 i5;
|
||||
unsigned32 i6_fp;
|
||||
unsigned32 i7;
|
||||
unsigned32 y;
|
||||
unsigned32 pad0_offset;
|
||||
} CPU_Interrupt_frame;
|
||||
|
||||
#endif /* ASM */
|
||||
|
||||
/*
|
||||
* Offsets of fields with CPU_Interrupt_frame for assembly routines.
|
||||
*/
|
||||
|
||||
#define ISF_STACK_FRAME_OFFSET 0x00
|
||||
#define ISF_PSR_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x00
|
||||
#define ISF_PC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x04
|
||||
#define ISF_NPC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x08
|
||||
#define ISF_G1_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x0c
|
||||
#define ISF_G2_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x10
|
||||
#define ISF_G3_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x14
|
||||
#define ISF_G4_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x18
|
||||
#define ISF_G5_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x1c
|
||||
#define ISF_G6_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x20
|
||||
#define ISF_G7_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x24
|
||||
#define ISF_I0_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x28
|
||||
#define ISF_I1_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x2c
|
||||
#define ISF_I2_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x30
|
||||
#define ISF_I3_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x34
|
||||
#define ISF_I4_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x38
|
||||
#define ISF_I5_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x3c
|
||||
#define ISF_I6_FP_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x40
|
||||
#define ISF_I7_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x44
|
||||
#define ISF_Y_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x48
|
||||
#define ISF_PAD0_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x4c
|
||||
|
||||
#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE CPU_MINIMUM_STACK_FRAME_SIZE + 0x50
|
||||
#ifndef ASM
|
||||
|
||||
/*
|
||||
* The following table contains the information required to configure
|
||||
* the processor specific parameters.
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
void (*pretasking_hook)( void );
|
||||
void (*predriver_hook)( void );
|
||||
void (*postdriver_hook)( void );
|
||||
void (*idle_task)( void );
|
||||
boolean do_zero_of_workspace;
|
||||
unsigned32 interrupt_stack_size;
|
||||
unsigned32 extra_mpci_receive_server_stack;
|
||||
void * (*stack_allocate_hook)( unsigned32 );
|
||||
void (*stack_free_hook)( void* );
|
||||
/* end of fields required on all CPUs */
|
||||
|
||||
} rtems_cpu_table;
|
||||
|
||||
/*
|
||||
* This variable is contains the initialize context for the FP unit.
|
||||
* It is filled in by _CPU_Initialize and copied into the task's FP
|
||||
* context area during _CPU_Context_Initialize.
|
||||
*/
|
||||
|
||||
SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context CPU_STRUCTURE_ALIGNMENT;
|
||||
|
||||
/*
|
||||
* This stack is allocated by the Interrupt Manager and the switch
|
||||
* is performed in _ISR_Handler. These variables contain pointers
|
||||
* to the lowest and highest addresses in the chunk of memory allocated
|
||||
* for the interrupt stack. Since it is unknown whether the stack
|
||||
* grows up or down (in general), this give the CPU dependent
|
||||
* code the option of picking the version it wants to use. Thus
|
||||
* both must be present if either is.
|
||||
*
|
||||
* The SPARC supports a software based interrupt stack and these
|
||||
* are required.
|
||||
*/
|
||||
|
||||
SCORE_EXTERN void *_CPU_Interrupt_stack_low;
|
||||
SCORE_EXTERN void *_CPU_Interrupt_stack_high;
|
||||
|
||||
#if defined(erc32)
|
||||
|
||||
/*
|
||||
* ERC32 Specific Variables
|
||||
*/
|
||||
|
||||
SCORE_EXTERN unsigned32 _ERC32_MEC_Timer_Control_Mirror;
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The following type defines an entry in the SPARC's trap table.
|
||||
*
|
||||
* NOTE: The instructions chosen are RTEMS dependent although one is
|
||||
* obligated to use two of the four instructions to perform a
|
||||
* long jump. The other instructions load one register with the
|
||||
* trap type (a.k.a. vector) and another with the psr.
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
unsigned32 mov_psr_l0; /* mov %psr, %l0 */
|
||||
unsigned32 sethi_of_handler_to_l4; /* sethi %hi(_handler), %l4 */
|
||||
unsigned32 jmp_to_low_of_handler_plus_l4; /* jmp %l4 + %lo(_handler) */
|
||||
unsigned32 mov_vector_l3; /* mov _vector, %l3 */
|
||||
} CPU_Trap_table_entry;
|
||||
|
||||
/*
|
||||
* This is the set of opcodes for the instructions loaded into a trap
|
||||
* table entry. The routine which installs a handler is responsible
|
||||
* for filling in the fields for the _handler address and the _vector
|
||||
* trap type.
|
||||
*
|
||||
* The constants following this structure are masks for the fields which
|
||||
* must be filled in when the handler is installed.
|
||||
*/
|
||||
|
||||
extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
|
||||
|
||||
/*
|
||||
* This is the executive's trap table which is installed into the TBR
|
||||
* register.
|
||||
*
|
||||
* NOTE: Unfortunately, this must be aligned on a 4096 byte boundary.
|
||||
* The GNU tools as of binutils 2.5.2 and gcc 2.7.0 would not
|
||||
* align an entity to anything greater than a 512 byte boundary.
|
||||
*
|
||||
* Because of this, we pull a little bit of a trick. We allocate
|
||||
* enough memory so we can grab an address on a 4096 byte boundary
|
||||
* from this area.
|
||||
*/
|
||||
|
||||
#define SPARC_TRAP_TABLE_ALIGNMENT 4096
|
||||
|
||||
SCORE_EXTERN unsigned8 _CPU_Trap_Table_area[ 8192 ]
|
||||
__attribute__ ((aligned (SPARC_TRAP_TABLE_ALIGNMENT)));
|
||||
|
||||
|
||||
/*
|
||||
* The size of the floating point context area.
|
||||
*/
|
||||
|
||||
#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Amount of extra stack (above minimum stack size) required by
|
||||
* MPCI receive server thread. Remember that in a multiprocessor
|
||||
* system this thread must exist and be able to process all directives.
|
||||
*/
|
||||
|
||||
#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
|
||||
|
||||
/*
|
||||
* This defines the number of entries in the ISR_Vector_table managed
|
||||
* by the executive.
|
||||
*
|
||||
* On the SPARC, there are really only 256 vectors. However, the executive
|
||||
* has no easy, fast, reliable way to determine which traps are synchronous
|
||||
* and which are asynchronous. By default, synchronous traps return to the
|
||||
* instruction which caused the interrupt. So if you install a software
|
||||
* trap handler as an executive interrupt handler (which is desirable since
|
||||
* RTEMS takes care of window and register issues), then the executive needs
|
||||
* to know that the return address is to the trap rather than the instruction
|
||||
* following the trap.
|
||||
*
|
||||
* So vectors 0 through 255 are treated as regular asynchronous traps which
|
||||
* provide the "correct" return address. Vectors 256 through 512 are assumed
|
||||
* by the executive to be synchronous and to require that the return address
|
||||
* be fudged.
|
||||
*
|
||||
* If you use this mechanism to install a trap handler which must reexecute
|
||||
* the instruction which caused the trap, then it should be installed as
|
||||
* an asynchronous trap. This will avoid the executive changing the return
|
||||
* address.
|
||||
*/
|
||||
|
||||
#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256
|
||||
#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 511
|
||||
|
||||
#define SPARC_SYNCHRONOUS_TRAP_BIT_MASK 0x100
|
||||
#define SPARC_ASYNCHRONOUS_TRAP( _trap ) (_trap)
|
||||
#define SPARC_SYNCHRONOUS_TRAP( _trap ) ((_trap) + 256 )
|
||||
|
||||
#define SPARC_REAL_TRAP_NUMBER( _trap ) ((_trap) % 256)
|
||||
|
||||
/*
|
||||
* Should be large enough to run all tests. This insures
|
||||
* that a "reasonable" small application should not have any problems.
|
||||
*
|
||||
* This appears to be a fairly generous number for the SPARC since
|
||||
* represents a call depth of about 20 routines based on the minimum
|
||||
* stack frame.
|
||||
*/
|
||||
|
||||
#define CPU_STACK_MINIMUM_SIZE (1024*2 + 512)
|
||||
|
||||
/*
|
||||
* CPU's worst alignment requirement for data types on a byte boundary. This
|
||||
* alignment does not take into account the requirements for the stack.
|
||||
*
|
||||
* On the SPARC, this is required for double word loads and stores.
|
||||
*/
|
||||
|
||||
#define CPU_ALIGNMENT 8
|
||||
|
||||
/*
|
||||
* This number corresponds to the byte alignment requirement for the
|
||||
* heap handler. This alignment requirement may be stricter than that
|
||||
* for the data types alignment specified by CPU_ALIGNMENT. It is
|
||||
* common for the heap to follow the same alignment requirement as
|
||||
* CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap,
|
||||
* then this should be set to CPU_ALIGNMENT.
|
||||
*
|
||||
* NOTE: This does not have to be a power of 2. It does have to
|
||||
* be greater or equal to than CPU_ALIGNMENT.
|
||||
*/
|
||||
|
||||
#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
|
||||
|
||||
/*
|
||||
* This number corresponds to the byte alignment requirement for memory
|
||||
* buffers allocated by the partition manager. This alignment requirement
|
||||
* may be stricter than that for the data types alignment specified by
|
||||
* CPU_ALIGNMENT. It is common for the partition to follow the same
|
||||
* alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict
|
||||
* enough for the partition, then this should be set to CPU_ALIGNMENT.
|
||||
*
|
||||
* NOTE: This does not have to be a power of 2. It does have to
|
||||
* be greater or equal to than CPU_ALIGNMENT.
|
||||
*/
|
||||
|
||||
#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
|
||||
|
||||
/*
|
||||
* This number corresponds to the byte alignment requirement for the
|
||||
* stack. This alignment requirement may be stricter than that for the
|
||||
* data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT
|
||||
* is strict enough for the stack, then this should be set to 0.
|
||||
*
|
||||
* NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
|
||||
*
|
||||
* The alignment restrictions for the SPARC are not that strict but this
|
||||
* should unsure that the stack is always sufficiently alignment that the
|
||||
* window overflow, underflow, and flush routines can use double word loads
|
||||
* and stores.
|
||||
*/
|
||||
|
||||
#define CPU_STACK_ALIGNMENT 16
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
/* ISR handler macros */
|
||||
|
||||
/*
|
||||
* Disable all interrupts for a critical section. The previous
|
||||
* level is returned in _level.
|
||||
*/
|
||||
|
||||
#define _CPU_ISR_Disable( _level ) \
|
||||
sparc_disable_interrupts( _level )
|
||||
|
||||
/*
|
||||
* Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
|
||||
* This indicates the end of a critical section. The parameter
|
||||
* _level is not modified.
|
||||
*/
|
||||
|
||||
#define _CPU_ISR_Enable( _level ) \
|
||||
sparc_enable_interrupts( _level )
|
||||
|
||||
/*
|
||||
* This temporarily restores the interrupt to _level before immediately
|
||||
* disabling them again. This is used to divide long critical
|
||||
* sections into two or more parts. The parameter _level is not
|
||||
* modified.
|
||||
*/
|
||||
|
||||
#define _CPU_ISR_Flash( _level ) \
|
||||
sparc_flash_interrupts( _level )
|
||||
|
||||
/*
|
||||
* Map interrupt level in task mode onto the hardware that the CPU
|
||||
* actually provides. Currently, interrupt levels which do not
|
||||
* map onto the CPU in a straight fashion are undefined.
|
||||
*/
|
||||
|
||||
#define _CPU_ISR_Set_level( _newlevel ) \
|
||||
sparc_set_interrupt_level( _newlevel )
|
||||
|
||||
unsigned32 _CPU_ISR_Get_level( void );
|
||||
|
||||
/* end of ISR handler macros */
|
||||
|
||||
/* Context handler macros */
|
||||
|
||||
/*
|
||||
* Initialize the context to a state suitable for starting a
|
||||
* task after a context restore operation. Generally, this
|
||||
* involves:
|
||||
*
|
||||
* - setting a starting address
|
||||
* - preparing the stack
|
||||
* - preparing the stack and frame pointers
|
||||
* - setting the proper interrupt level in the context
|
||||
* - initializing the floating point context
|
||||
*
|
||||
* NOTE: Implemented as a subroutine for the SPARC port.
|
||||
*/
|
||||
|
||||
void _CPU_Context_Initialize(
|
||||
Context_Control *the_context,
|
||||
unsigned32 *stack_base,
|
||||
unsigned32 size,
|
||||
unsigned32 new_level,
|
||||
void *entry_point,
|
||||
boolean is_fp
|
||||
);
|
||||
|
||||
/*
|
||||
* This routine is responsible for somehow restarting the currently
|
||||
* executing task.
|
||||
*
|
||||
* On the SPARC, this is is relatively painless but requires a small
|
||||
* amount of wrapper code before using the regular restore code in
|
||||
* of the context switch.
|
||||
*/
|
||||
|
||||
#define _CPU_Context_Restart_self( _the_context ) \
|
||||
_CPU_Context_restore( (_the_context) );
|
||||
|
||||
/*
|
||||
* The FP context area for the SPARC is a simple structure and nothing
|
||||
* special is required to find the "starting load point"
|
||||
*/
|
||||
|
||||
#define _CPU_Context_Fp_start( _base, _offset ) \
|
||||
( (void *) (_base) + (_offset) )
|
||||
|
||||
/*
|
||||
* This routine initializes the FP context area passed to it to.
|
||||
*
|
||||
* The SPARC allows us to use the simple initialization model
|
||||
* in which an "initial" FP context was saved into _CPU_Null_fp_context
|
||||
* at CPU initialization and it is simply copied into the destination
|
||||
* context.
|
||||
*/
|
||||
|
||||
#define _CPU_Context_Initialize_fp( _destination ) \
|
||||
do { \
|
||||
*((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
|
||||
} while (0)
|
||||
|
||||
/* end of Context handler macros */
|
||||
|
||||
/* Fatal Error manager macros */
|
||||
|
||||
/*
|
||||
* This routine copies _error into a known place -- typically a stack
|
||||
* location or a register, optionally disables interrupts, and
|
||||
* halts/stops the CPU.
|
||||
*/
|
||||
|
||||
#define _CPU_Fatal_halt( _error ) \
|
||||
do { \
|
||||
unsigned32 level; \
|
||||
\
|
||||
sparc_disable_interrupts( level ); \
|
||||
asm volatile ( "mov %0, %%g1 " : "=r" (level) : "0" (level) ); \
|
||||
while (1); /* loop forever */ \
|
||||
} while (0)
|
||||
|
||||
/* end of Fatal Error manager macros */
|
||||
|
||||
/* Bitfield handler macros */
|
||||
|
||||
/*
|
||||
* The SPARC port uses the generic C algorithm for bitfield scan if the
|
||||
* CPU model does not have a scan instruction.
|
||||
*/
|
||||
|
||||
#if ( SPARC_HAS_BITSCAN == 0 )
|
||||
#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
|
||||
#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
|
||||
#else
|
||||
#error "scan instruction not currently supported by RTEMS!!"
|
||||
#endif
|
||||
|
||||
/* end of Bitfield handler macros */
|
||||
|
||||
/* Priority handler handler macros */
|
||||
|
||||
/*
|
||||
* The SPARC port uses the generic C algorithm for bitfield scan if the
|
||||
* CPU model does not have a scan instruction.
|
||||
*/
|
||||
|
||||
#if ( SPARC_HAS_BITSCAN == 1 )
|
||||
#error "scan instruction not currently supported by RTEMS!!"
|
||||
#endif
|
||||
|
||||
/* end of Priority handler macros */
|
||||
|
||||
/* functions */
|
||||
|
||||
/*
|
||||
* _CPU_Initialize
|
||||
*
|
||||
* This routine performs CPU dependent initialization.
|
||||
*/
|
||||
|
||||
void _CPU_Initialize(
|
||||
rtems_cpu_table *cpu_table,
|
||||
void (*thread_dispatch)
|
||||
);
|
||||
|
||||
/*
|
||||
* _CPU_ISR_install_raw_handler
|
||||
*
|
||||
* This routine installs new_handler to be directly called from the trap
|
||||
* table.
|
||||
*/
|
||||
|
||||
void _CPU_ISR_install_raw_handler(
|
||||
unsigned32 vector,
|
||||
proc_ptr new_handler,
|
||||
proc_ptr *old_handler
|
||||
);
|
||||
|
||||
/*
|
||||
* _CPU_ISR_install_vector
|
||||
*
|
||||
* This routine installs an interrupt vector.
|
||||
*/
|
||||
|
||||
void _CPU_ISR_install_vector(
|
||||
unsigned32 vector,
|
||||
proc_ptr new_handler,
|
||||
proc_ptr *old_handler
|
||||
);
|
||||
|
||||
#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
|
||||
|
||||
/*
|
||||
* _CPU_Thread_Idle_body
|
||||
*
|
||||
* Some SPARC implementations have low power, sleep, or idle modes. This
|
||||
* tries to take advantage of those models.
|
||||
*/
|
||||
|
||||
void _CPU_Thread_Idle_body( void );
|
||||
|
||||
#endif /* CPU_PROVIDES_IDLE_THREAD_BODY */
|
||||
|
||||
/*
|
||||
* _CPU_Context_switch
|
||||
*
|
||||
* This routine switches from the run context to the heir context.
|
||||
*/
|
||||
|
||||
void _CPU_Context_switch(
|
||||
Context_Control *run,
|
||||
Context_Control *heir
|
||||
);
|
||||
|
||||
/*
|
||||
* _CPU_Context_restore
|
||||
*
|
||||
* This routine is generallu used only to restart self in an
|
||||
* efficient manner.
|
||||
*/
|
||||
|
||||
void _CPU_Context_restore(
|
||||
Context_Control *new_context
|
||||
);
|
||||
|
||||
/*
|
||||
* _CPU_Context_save_fp
|
||||
*
|
||||
* This routine saves the floating point context passed to it.
|
||||
*/
|
||||
|
||||
void _CPU_Context_save_fp(
|
||||
void **fp_context_ptr
|
||||
);
|
||||
|
||||
/*
|
||||
* _CPU_Context_restore_fp
|
||||
*
|
||||
* This routine restores the floating point context passed to it.
|
||||
*/
|
||||
|
||||
void _CPU_Context_restore_fp(
|
||||
void **fp_context_ptr
|
||||
);
|
||||
|
||||
/*
|
||||
* CPU_swap_u32
|
||||
*
|
||||
* The following routine swaps the endian format of an unsigned int.
|
||||
* It must be static because it is referenced indirectly.
|
||||
*
|
||||
* This version will work on any processor, but if you come across a better
|
||||
* way for the SPARC PLEASE use it. The most common way to swap a 32-bit
|
||||
* entity as shown below is not any more efficient on the SPARC.
|
||||
*
|
||||
* swap least significant two bytes with 16-bit rotate
|
||||
* swap upper and lower 16-bits
|
||||
* swap most significant two bytes with 16-bit rotate
|
||||
*
|
||||
* It is not obvious how the SPARC can do significantly better than the
|
||||
* generic code. gcc 2.7.0 only generates about 12 instructions for the
|
||||
* following code at optimization level four (i.e. -O4).
|
||||
*/
|
||||
|
||||
static inline unsigned int CPU_swap_u32(
|
||||
unsigned int value
|
||||
)
|
||||
{
|
||||
unsigned32 byte1, byte2, byte3, byte4, swapped;
|
||||
|
||||
byte4 = (value >> 24) & 0xff;
|
||||
byte3 = (value >> 16) & 0xff;
|
||||
byte2 = (value >> 8) & 0xff;
|
||||
byte1 = value & 0xff;
|
||||
|
||||
swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
|
||||
return( swapped );
|
||||
}
|
||||
|
||||
#endif ASM
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,707 +0,0 @@
|
||||
/* cpu_asm.s
|
||||
*
|
||||
* This file contains the basic algorithms for all assembly code used
|
||||
* in an specific CPU port of RTEMS. These algorithms must be implemented
|
||||
* in assembly language.
|
||||
*
|
||||
* COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
* All rights assigned to U.S. Government, 1994.
|
||||
*
|
||||
* This material may be reproduced by or for the U.S. Government pursuant
|
||||
* to the copyright license under the clause at DFARS 252.227-7013. This
|
||||
* notice must appear in all copies of this file and its derivatives.
|
||||
*
|
||||
* Ported to ERC32 implementation of the SPARC by On-Line Applications
|
||||
* Research Corporation (OAR) under contract to the European Space
|
||||
* Agency (ESA).
|
||||
*
|
||||
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
|
||||
* European Space Agency.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <asm.h>
|
||||
#include <rtems/score/cpu.h>
|
||||
|
||||
#if (SPARC_HAS_FPU == 1)
|
||||
|
||||
/*
|
||||
* void _CPU_Context_save_fp(
|
||||
* void **fp_context_ptr
|
||||
* )
|
||||
*
|
||||
* This routine is responsible for saving the FP context
|
||||
* at *fp_context_ptr. If the point to load the FP context
|
||||
* from is changed then the pointer is modified by this routine.
|
||||
*
|
||||
* NOTE: See the README in this directory for information on the
|
||||
* management of the "EF" bit in the PSR.
|
||||
*/
|
||||
|
||||
.align 4
|
||||
PUBLIC(_CPU_Context_save_fp)
|
||||
SYM(_CPU_Context_save_fp):
|
||||
save %sp, -CPU_MINIMUM_STACK_FRAME_SIZE, %sp
|
||||
|
||||
/*
|
||||
* The following enables the floating point unit.
|
||||
*/
|
||||
|
||||
mov %psr, %l0
|
||||
sethi %hi(SPARC_PSR_EF_MASK), %l1
|
||||
or %l1, %lo(SPARC_PSR_EF_MASK), %l1
|
||||
or %l0, %l1, %l0
|
||||
mov %l0, %psr ! **** ENABLE FLOAT ACCESS ****
|
||||
|
||||
ld [%i0], %l0
|
||||
std %f0, [%l0 + FO_F1_OFFSET]
|
||||
std %f2, [%l0 + F2_F3_OFFSET]
|
||||
std %f4, [%l0 + F4_F5_OFFSET]
|
||||
std %f6, [%l0 + F6_F7_OFFSET]
|
||||
std %f8, [%l0 + F8_F9_OFFSET]
|
||||
std %f10, [%l0 + F1O_F11_OFFSET]
|
||||
std %f12, [%l0 + F12_F13_OFFSET]
|
||||
std %f14, [%l0 + F14_F15_OFFSET]
|
||||
std %f16, [%l0 + F16_F17_OFFSET]
|
||||
std %f18, [%l0 + F18_F19_OFFSET]
|
||||
std %f20, [%l0 + F2O_F21_OFFSET]
|
||||
std %f22, [%l0 + F22_F23_OFFSET]
|
||||
std %f24, [%l0 + F24_F25_OFFSET]
|
||||
std %f26, [%l0 + F26_F27_OFFSET]
|
||||
std %f28, [%l0 + F28_F29_OFFSET]
|
||||
std %f30, [%l0 + F3O_F31_OFFSET]
|
||||
st %fsr, [%l0 + FSR_OFFSET]
|
||||
ret
|
||||
restore
|
||||
|
||||
/*
|
||||
* void _CPU_Context_restore_fp(
|
||||
* void **fp_context_ptr
|
||||
* )
|
||||
*
|
||||
* This routine is responsible for restoring the FP context
|
||||
* at *fp_context_ptr. If the point to load the FP context
|
||||
* from is changed then the pointer is modified by this routine.
|
||||
*
|
||||
* NOTE: See the README in this directory for information on the
|
||||
* management of the "EF" bit in the PSR.
|
||||
*/
|
||||
|
||||
.align 4
|
||||
PUBLIC(_CPU_Context_restore_fp)
|
||||
SYM(_CPU_Context_restore_fp):
|
||||
save %sp, -CPU_MINIMUM_STACK_FRAME_SIZE , %sp
|
||||
|
||||
/*
|
||||
* The following enables the floating point unit.
|
||||
*/
|
||||
|
||||
mov %psr, %l0
|
||||
sethi %hi(SPARC_PSR_EF_MASK), %l1
|
||||
or %l1, %lo(SPARC_PSR_EF_MASK), %l1
|
||||
or %l0, %l1, %l0
|
||||
mov %l0, %psr ! **** ENABLE FLOAT ACCESS ****
|
||||
|
||||
ld [%i0], %l0
|
||||
ldd [%l0 + FO_F1_OFFSET], %f0
|
||||
ldd [%l0 + F2_F3_OFFSET], %f2
|
||||
ldd [%l0 + F4_F5_OFFSET], %f4
|
||||
ldd [%l0 + F6_F7_OFFSET], %f6
|
||||
ldd [%l0 + F8_F9_OFFSET], %f8
|
||||
ldd [%l0 + F1O_F11_OFFSET], %f10
|
||||
ldd [%l0 + F12_F13_OFFSET], %f12
|
||||
ldd [%l0 + F14_F15_OFFSET], %f14
|
||||
ldd [%l0 + F16_F17_OFFSET], %f16
|
||||
ldd [%l0 + F18_F19_OFFSET], %f18
|
||||
ldd [%l0 + F2O_F21_OFFSET], %f20
|
||||
ldd [%l0 + F22_F23_OFFSET], %f22
|
||||
ldd [%l0 + F24_F25_OFFSET], %f24
|
||||
ldd [%l0 + F26_F27_OFFSET], %f26
|
||||
ldd [%l0 + F28_F29_OFFSET], %f28
|
||||
ldd [%l0 + F3O_F31_OFFSET], %f30
|
||||
ld [%l0 + FSR_OFFSET], %fsr
|
||||
ret
|
||||
restore
|
||||
|
||||
#endif /* SPARC_HAS_FPU */
|
||||
|
||||
/*
|
||||
* void _CPU_Context_switch(
|
||||
* Context_Control *run,
|
||||
* Context_Control *heir
|
||||
* )
|
||||
*
|
||||
* This routine performs a normal non-FP context switch.
|
||||
*/
|
||||
|
||||
.align 4
|
||||
PUBLIC(_CPU_Context_switch)
|
||||
SYM(_CPU_Context_switch):
|
||||
! skip g0
|
||||
st %g1, [%o0 + G1_OFFSET] ! save the global registers
|
||||
std %g2, [%o0 + G2_OFFSET]
|
||||
std %g4, [%o0 + G4_OFFSET]
|
||||
std %g6, [%o0 + G6_OFFSET]
|
||||
|
||||
std %l0, [%o0 + L0_OFFSET] ! save the local registers
|
||||
std %l2, [%o0 + L2_OFFSET]
|
||||
std %l4, [%o0 + L4_OFFSET]
|
||||
std %l6, [%o0 + L6_OFFSET]
|
||||
|
||||
std %i0, [%o0 + I0_OFFSET] ! save the input registers
|
||||
std %i2, [%o0 + I2_OFFSET]
|
||||
std %i4, [%o0 + I4_OFFSET]
|
||||
std %i6, [%o0 + I6_FP_OFFSET]
|
||||
|
||||
std %o0, [%o0 + O0_OFFSET] ! save the output registers
|
||||
std %o2, [%o0 + O2_OFFSET]
|
||||
std %o4, [%o0 + O4_OFFSET]
|
||||
std %o6, [%o0 + O6_SP_OFFSET]
|
||||
|
||||
rd %psr, %o2
|
||||
st %o2, [%o0 + PSR_OFFSET] ! save status register
|
||||
|
||||
/*
|
||||
* This is entered from _CPU_Context_restore with:
|
||||
* o1 = context to restore
|
||||
* o2 = psr
|
||||
*/
|
||||
|
||||
PUBLIC(_CPU_Context_restore_heir)
|
||||
SYM(_CPU_Context_restore_heir):
|
||||
/*
|
||||
* Flush all windows with valid contents except the current one.
|
||||
* In examining the set register windows, one may logically divide
|
||||
* the windows into sets (some of which may be empty) based on their
|
||||
* current status:
|
||||
*
|
||||
* + current (i.e. in use),
|
||||
* + used (i.e. a restore would not trap)
|
||||
* + invalid (i.e. 1 in corresponding bit in WIM)
|
||||
* + unused
|
||||
*
|
||||
* Either the used or unused set of windows may be empty.
|
||||
*
|
||||
* NOTE: We assume only one bit is set in the WIM at a time.
|
||||
*
|
||||
* Given a CWP of 5 and a WIM of 0x1, the registers are divided
|
||||
* into sets as follows:
|
||||
*
|
||||
* + 0 - invalid
|
||||
* + 1-4 - unused
|
||||
* + 5 - current
|
||||
* + 6-7 - used
|
||||
*
|
||||
* In this case, we only would save the used windows -- 6 and 7.
|
||||
*
|
||||
* Traps are disabled for the same logical period as in a
|
||||
* flush all windows trap handler.
|
||||
*
|
||||
* Register Usage while saving the windows:
|
||||
* g1 = current PSR
|
||||
* g2 = current wim
|
||||
* g3 = CWP
|
||||
* g4 = wim scratch
|
||||
* g5 = scratch
|
||||
*/
|
||||
|
||||
ld [%o1 + PSR_OFFSET], %g1 ! g1 = saved psr
|
||||
|
||||
and %o2, SPARC_PSR_CWP_MASK, %g3 ! g3 = CWP
|
||||
! g1 = psr w/o cwp
|
||||
andn %g1, SPARC_PSR_ET_MASK | SPARC_PSR_CWP_MASK, %g1
|
||||
or %g1, %g3, %g1 ! g1 = heirs psr
|
||||
mov %g1, %psr ! restore status register and
|
||||
! **** DISABLE TRAPS ****
|
||||
mov %wim, %g2 ! g2 = wim
|
||||
mov 1, %g4
|
||||
sll %g4, %g3, %g4 ! g4 = WIM mask for CW invalid
|
||||
|
||||
save_frame_loop:
|
||||
sll %g4, 1, %g5 ! rotate the "wim" left 1
|
||||
srl %g4, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g4
|
||||
or %g4, %g5, %g4 ! g4 = wim if we do one restore
|
||||
|
||||
/*
|
||||
* If a restore would not underflow, then continue.
|
||||
*/
|
||||
|
||||
andcc %g4, %g2, %g0 ! Any windows to flush?
|
||||
bnz done_flushing ! No, then continue
|
||||
nop
|
||||
|
||||
restore ! back one window
|
||||
|
||||
/*
|
||||
* Now save the window just as if we overflowed to it.
|
||||
*/
|
||||
|
||||
std %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET]
|
||||
std %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET]
|
||||
std %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET]
|
||||
std %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET]
|
||||
|
||||
std %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET]
|
||||
std %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET]
|
||||
std %i4, [%sp + CPU_STACK_FRAME_I4_OFFSET]
|
||||
std %i6, [%sp + CPU_STACK_FRAME_I6_FP_OFFSET]
|
||||
|
||||
ba save_frame_loop
|
||||
nop
|
||||
|
||||
done_flushing:
|
||||
|
||||
add %g3, 1, %g3 ! calculate desired WIM
|
||||
and %g3, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g3
|
||||
mov 1, %g4
|
||||
sll %g4, %g3, %g4 ! g4 = new WIM
|
||||
mov %g4, %wim
|
||||
|
||||
or %g1, SPARC_PSR_ET_MASK, %g1
|
||||
mov %g1, %psr ! **** ENABLE TRAPS ****
|
||||
! and restore CWP
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
|
||||
! skip g0
|
||||
ld [%o1 + G1_OFFSET], %g1 ! restore the global registers
|
||||
ldd [%o1 + G2_OFFSET], %g2
|
||||
ldd [%o1 + G4_OFFSET], %g4
|
||||
ldd [%o1 + G6_OFFSET], %g6
|
||||
|
||||
ldd [%o1 + L0_OFFSET], %l0 ! restore the local registers
|
||||
ldd [%o1 + L2_OFFSET], %l2
|
||||
ldd [%o1 + L4_OFFSET], %l4
|
||||
ldd [%o1 + L6_OFFSET], %l6
|
||||
|
||||
ldd [%o1 + I0_OFFSET], %i0 ! restore the output registers
|
||||
ldd [%o1 + I2_OFFSET], %i2
|
||||
ldd [%o1 + I4_OFFSET], %i4
|
||||
ldd [%o1 + I6_FP_OFFSET], %i6
|
||||
|
||||
ldd [%o1 + O2_OFFSET], %o2 ! restore the output registers
|
||||
ldd [%o1 + O4_OFFSET], %o4
|
||||
ldd [%o1 + O6_SP_OFFSET], %o6
|
||||
! do o0/o1 last to avoid destroying heir context pointer
|
||||
ldd [%o1 + O0_OFFSET], %o0 ! overwrite heir pointer
|
||||
|
||||
jmp %o7 + 8 ! return
|
||||
nop ! delay slot
|
||||
|
||||
/*
|
||||
* void _CPU_Context_restore(
|
||||
* Context_Control *new_context
|
||||
* )
|
||||
*
|
||||
* This routine is generally used only to perform restart self.
|
||||
*
|
||||
* NOTE: It is unnecessary to reload some registers.
|
||||
*/
|
||||
|
||||
.align 4
|
||||
PUBLIC(_CPU_Context_restore)
|
||||
SYM(_CPU_Context_restore):
|
||||
save %sp, -CPU_MINIMUM_STACK_FRAME_SIZE, %sp
|
||||
rd %psr, %o2
|
||||
ba SYM(_CPU_Context_restore_heir)
|
||||
mov %i0, %o1 ! in the delay slot
|
||||
|
||||
/*
|
||||
* void _ISR_Handler()
|
||||
*
|
||||
* This routine provides the RTEMS interrupt management.
|
||||
*
|
||||
* We enter this handler from the 4 instructions in the trap table with
|
||||
* the following registers assumed to be set as shown:
|
||||
*
|
||||
* l0 = PSR
|
||||
* l1 = PC
|
||||
* l2 = nPC
|
||||
* l3 = trap type
|
||||
*
|
||||
* NOTE: By an executive defined convention, trap type is between 0 and 255 if
|
||||
* it is an asynchonous trap and 256 and 511 if it is synchronous.
|
||||
*/
|
||||
|
||||
.align 4
|
||||
PUBLIC(_ISR_Handler)
|
||||
SYM(_ISR_Handler):
|
||||
/*
|
||||
* Fix the return address for synchronous traps.
|
||||
*/
|
||||
|
||||
andcc %l3, SPARC_SYNCHRONOUS_TRAP_BIT_MASK, %g0
|
||||
! Is this a synchronous trap?
|
||||
be,a win_ovflow ! No, then skip the adjustment
|
||||
nop ! DELAY
|
||||
mov %l2, %l1 ! do not return to the instruction
|
||||
add %l2, 4, %l2 ! indicated
|
||||
|
||||
win_ovflow:
|
||||
/*
|
||||
* Save the globals this block uses.
|
||||
*
|
||||
* These registers are not restored from the locals. Their contents
|
||||
* are saved directly from the locals into the ISF below.
|
||||
*/
|
||||
|
||||
mov %g4, %l4 ! save the globals this block uses
|
||||
mov %g5, %l5
|
||||
|
||||
/*
|
||||
* When at a "window overflow" trap, (wim == (1 << cwp)).
|
||||
* If we get here like that, then process a window overflow.
|
||||
*/
|
||||
|
||||
rd %wim, %g4
|
||||
srl %g4, %l0, %g5 ! g5 = win >> cwp ; shift count and CWP
|
||||
! are LS 5 bits ; how convenient :)
|
||||
cmp %g5, 1 ! Is this an invalid window?
|
||||
bne dont_do_the_window ! No, then skip all this stuff
|
||||
! we are using the delay slot
|
||||
|
||||
/*
|
||||
* The following is same as a 1 position right rotate of WIM
|
||||
*/
|
||||
|
||||
srl %g4, 1, %g5 ! g5 = WIM >> 1
|
||||
sll %g4, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %g4
|
||||
! g4 = WIM << (Number Windows - 1)
|
||||
or %g4, %g5, %g4 ! g4 = (WIM >> 1) |
|
||||
! (WIM << (Number Windows - 1))
|
||||
|
||||
/*
|
||||
* At this point:
|
||||
*
|
||||
* g4 = the new WIM
|
||||
* g5 is free
|
||||
*/
|
||||
|
||||
/*
|
||||
* Since we are tinkering with the register windows, we need to
|
||||
* make sure that all the required information is in global registers.
|
||||
*/
|
||||
|
||||
save ! Save into the window
|
||||
wr %g4, 0, %wim ! WIM = new WIM
|
||||
nop ! delay slots
|
||||
nop
|
||||
nop
|
||||
|
||||
/*
|
||||
* Now save the window just as if we overflowed to it.
|
||||
*/
|
||||
|
||||
std %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET]
|
||||
std %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET]
|
||||
std %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET]
|
||||
std %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET]
|
||||
|
||||
std %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET]
|
||||
std %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET]
|
||||
std %i4, [%sp + CPU_STACK_FRAME_I4_OFFSET]
|
||||
std %i6, [%sp + CPU_STACK_FRAME_I6_FP_OFFSET]
|
||||
|
||||
restore
|
||||
nop
|
||||
|
||||
dont_do_the_window:
|
||||
/*
|
||||
* Global registers %g4 and %g5 are saved directly from %l4 and
|
||||
* %l5 directly into the ISF below.
|
||||
*/
|
||||
|
||||
save_isf:
|
||||
|
||||
/*
|
||||
* Save the state of the interrupted task -- especially the global
|
||||
* registers -- in the Interrupt Stack Frame. Note that the ISF
|
||||
* includes a regular minimum stack frame which will be used if
|
||||
* needed by register window overflow and underflow handlers.
|
||||
*
|
||||
* REGISTERS SAME AS AT _ISR_Handler
|
||||
*/
|
||||
|
||||
sub %fp, CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE, %sp
|
||||
! make space for ISF
|
||||
|
||||
std %l0, [%sp + ISF_PSR_OFFSET] ! save psr, PC
|
||||
st %l2, [%sp + ISF_NPC_OFFSET] ! save nPC
|
||||
st %g1, [%sp + ISF_G1_OFFSET] ! save g1
|
||||
std %g2, [%sp + ISF_G2_OFFSET] ! save g2, g3
|
||||
std %l4, [%sp + ISF_G4_OFFSET] ! save g4, g5 -- see above
|
||||
std %g6, [%sp + ISF_G6_OFFSET] ! save g6, g7
|
||||
|
||||
std %i0, [%sp + ISF_I0_OFFSET] ! save i0, i1
|
||||
std %i2, [%sp + ISF_I2_OFFSET] ! save i2, i3
|
||||
std %i4, [%sp + ISF_I4_OFFSET] ! save i4, i5
|
||||
std %i6, [%sp + ISF_I6_FP_OFFSET] ! save i6/fp, i7
|
||||
|
||||
rd %y, %g1
|
||||
st %g1, [%sp + ISF_Y_OFFSET] ! save y
|
||||
|
||||
mov %sp, %o1 ! 2nd arg to ISR Handler
|
||||
|
||||
/*
|
||||
* Increment ISR nest level and Thread dispatch disable level.
|
||||
*
|
||||
* Register usage for this section:
|
||||
*
|
||||
* l4 = _Thread_Dispatch_disable_level pointer
|
||||
* l5 = _ISR_Nest_level pointer
|
||||
* l6 = _Thread_Dispatch_disable_level value
|
||||
* l7 = _ISR_Nest_level value
|
||||
*
|
||||
* NOTE: It is assumed that l4 - l7 will be preserved until the ISR
|
||||
* nest and thread dispatch disable levels are unnested.
|
||||
*/
|
||||
|
||||
sethi %hi(SYM(_Thread_Dispatch_disable_level)), %l4
|
||||
ld [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))], %l6
|
||||
sethi %hi(SYM(_ISR_Nest_level)), %l5
|
||||
ld [%l5 + %lo(SYM(_ISR_Nest_level))], %l7
|
||||
|
||||
add %l6, 1, %l6
|
||||
st %l6, [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))]
|
||||
|
||||
add %l7, 1, %l7
|
||||
st %l7, [%l5 + %lo(SYM(_ISR_Nest_level))]
|
||||
|
||||
/*
|
||||
* If ISR nest level was zero (now 1), then switch stack.
|
||||
*/
|
||||
|
||||
mov %sp, %fp
|
||||
subcc %l7, 1, %l7 ! outermost interrupt handler?
|
||||
bnz dont_switch_stacks ! No, then do not switch stacks
|
||||
|
||||
sethi %hi(SYM(_CPU_Interrupt_stack_high)), %g4
|
||||
ld [%g4 + %lo(SYM(_CPU_Interrupt_stack_high))], %sp
|
||||
|
||||
dont_switch_stacks:
|
||||
/*
|
||||
* Make sure we have a place on the stack for the window overflow
|
||||
* trap handler to write into. At this point it is safe to
|
||||
* enable traps again.
|
||||
*/
|
||||
|
||||
sub %sp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp
|
||||
|
||||
wr %l0, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS ****
|
||||
|
||||
/*
|
||||
* Vector to user's handler.
|
||||
*
|
||||
* NOTE: TBR may no longer have vector number in it since
|
||||
* we just enabled traps. It is definitely in l3.
|
||||
*/
|
||||
|
||||
sethi %hi(SYM(_ISR_Vector_table)), %g4
|
||||
or %g4, %lo(SYM(_ISR_Vector_table)), %g4
|
||||
and %l3, 0xFF, %g5 ! remove synchronous trap indicator
|
||||
sll %g5, 2, %g5 ! g5 = offset into table
|
||||
ld [%g4 + %g5], %g4 ! g4 = _ISR_Vector_table[ vector ]
|
||||
|
||||
|
||||
! o1 = 2nd arg = address of the ISF
|
||||
! WAS LOADED WHEN ISF WAS SAVED!!!
|
||||
mov %l3, %o0 ! o0 = 1st arg = vector number
|
||||
call %g4, 0
|
||||
nop ! delay slot
|
||||
|
||||
/*
|
||||
* Redisable traps so we can finish up the interrupt processing.
|
||||
* This is a VERY conservative place to do this.
|
||||
*
|
||||
* NOTE: %l0 has the PSR which was in place when we took the trap.
|
||||
*/
|
||||
|
||||
mov %l0, %psr ! **** DISABLE TRAPS ****
|
||||
|
||||
/*
|
||||
* Decrement ISR nest level and Thread dispatch disable level.
|
||||
*
|
||||
* Register usage for this section:
|
||||
*
|
||||
* l4 = _Thread_Dispatch_disable_level pointer
|
||||
* l5 = _ISR_Nest_level pointer
|
||||
* l6 = _Thread_Dispatch_disable_level value
|
||||
* l7 = _ISR_Nest_level value
|
||||
*/
|
||||
|
||||
sub %l6, 1, %l6
|
||||
st %l6, [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))]
|
||||
|
||||
st %l7, [%l5 + %lo(SYM(_ISR_Nest_level))]
|
||||
|
||||
/*
|
||||
* If dispatching is disabled (includes nested interrupt case),
|
||||
* then do a "simple" exit.
|
||||
*/
|
||||
|
||||
orcc %l6, %g0, %g0 ! Is dispatching disabled?
|
||||
bnz simple_return ! Yes, then do a "simple" exit
|
||||
nop ! delay slot
|
||||
|
||||
/*
|
||||
* If a context switch is necessary, then do fudge stack to
|
||||
* return to the interrupt dispatcher.
|
||||
*/
|
||||
|
||||
sethi %hi(SYM(_Context_Switch_necessary)), %l4
|
||||
ld [%l4 + %lo(SYM(_Context_Switch_necessary))], %l5
|
||||
|
||||
orcc %l5, %g0, %g0 ! Is thread switch necessary?
|
||||
bnz SYM(_ISR_Dispatch) ! yes, then invoke the dispatcher
|
||||
nop ! delay slot
|
||||
|
||||
/*
|
||||
* Finally, check to see if signals were sent to the currently
|
||||
* executing task. If so, we need to invoke the interrupt dispatcher.
|
||||
*/
|
||||
|
||||
sethi %hi(SYM(_ISR_Signals_to_thread_executing)), %l6
|
||||
ld [%l6 + %lo(SYM(_ISR_Signals_to_thread_executing))], %l7
|
||||
|
||||
orcc %l7, %g0, %g0 ! Were signals sent to the currently
|
||||
! executing thread?
|
||||
bz simple_return ! yes, then invoke the dispatcher
|
||||
! use the delay slot to clear the signals
|
||||
! to the currently executing task flag
|
||||
st %g0, [%l6 + %lo(SYM(_ISR_Signals_to_thread_executing))]
|
||||
|
||||
|
||||
/*
|
||||
* Invoke interrupt dispatcher.
|
||||
*/
|
||||
|
||||
PUBLIC(_ISR_Dispatch)
|
||||
SYM(_ISR_Dispatch):
|
||||
|
||||
/*
|
||||
* The following subtract should get us back on the interrupted
|
||||
* tasks stack and add enough room to invoke the dispatcher.
|
||||
* When we enable traps, we are mostly back in the context
|
||||
* of the task and subsequent interrupts can operate normally.
|
||||
*/
|
||||
|
||||
sub %fp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp
|
||||
|
||||
or %l0, SPARC_PSR_ET_MASK, %l7 ! l7 = PSR with ET=1
|
||||
mov %l7, %psr ! **** ENABLE TRAPS ****
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
|
||||
call SYM(_Thread_Dispatch), 0
|
||||
nop
|
||||
|
||||
/*
|
||||
* The CWP in place at this point may be different from
|
||||
* that which was in effect at the beginning of the ISR if we
|
||||
* have been context switched between the beginning of this invocation
|
||||
* of _ISR_Handler and this point. Thus the CWP and WIM should
|
||||
* not be changed back to their values at ISR entry time. Any
|
||||
* changes to the PSR must preserve the CWP.
|
||||
*/
|
||||
|
||||
simple_return:
|
||||
ld [%fp + ISF_Y_OFFSET], %l5 ! restore y
|
||||
wr %l5, 0, %y
|
||||
|
||||
ldd [%fp + ISF_PSR_OFFSET], %l0 ! restore psr, PC
|
||||
ld [%fp + ISF_NPC_OFFSET], %l2 ! restore nPC
|
||||
rd %psr, %l3
|
||||
and %l3, SPARC_PSR_CWP_MASK, %l3 ! want "current" CWP
|
||||
andn %l0, SPARC_PSR_CWP_MASK, %l0 ! want rest from task
|
||||
or %l3, %l0, %l0 ! install it later...
|
||||
andn %l0, SPARC_PSR_ET_MASK, %l0
|
||||
|
||||
/*
|
||||
* Restore tasks global and out registers
|
||||
*/
|
||||
|
||||
mov %fp, %g1
|
||||
|
||||
! g1 is restored later
|
||||
ldd [%fp + ISF_G2_OFFSET], %g2 ! restore g2, g3
|
||||
ldd [%fp + ISF_G4_OFFSET], %g4 ! restore g4, g5
|
||||
ldd [%fp + ISF_G6_OFFSET], %g6 ! restore g6, g7
|
||||
|
||||
ldd [%fp + ISF_I0_OFFSET], %i0 ! restore i0, i1
|
||||
ldd [%fp + ISF_I2_OFFSET], %i2 ! restore i2, i3
|
||||
ldd [%fp + ISF_I4_OFFSET], %i4 ! restore i4, i5
|
||||
ldd [%fp + ISF_I6_FP_OFFSET], %i6 ! restore i6/fp, i7
|
||||
|
||||
/*
|
||||
* Registers:
|
||||
*
|
||||
* ALL global registers EXCEPT G1 and the input registers have
|
||||
* already been restored and thuse off limits.
|
||||
*
|
||||
* The following is the contents of the local registers:
|
||||
*
|
||||
* l0 = original psr
|
||||
* l1 = return address (i.e. PC)
|
||||
* l2 = nPC
|
||||
* l3 = CWP
|
||||
*/
|
||||
|
||||
/*
|
||||
* if (CWP + 1) is an invalid window then we need to reload it.
|
||||
*
|
||||
* WARNING: Traps should now be disabled
|
||||
*/
|
||||
|
||||
mov %l0, %psr ! **** DISABLE TRAPS ****
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
rd %wim, %l4
|
||||
add %l0, 1, %l6 ! l6 = cwp + 1
|
||||
and %l6, SPARC_PSR_CWP_MASK, %l6 ! do the modulo on it
|
||||
srl %l4, %l6, %l5 ! l5 = win >> cwp + 1 ; shift count
|
||||
! and CWP are conveniently LS 5 bits
|
||||
cmp %l5, 1 ! Is tasks window invalid?
|
||||
bne good_task_window
|
||||
|
||||
/*
|
||||
* The following code is the same as a 1 position left rotate of WIM.
|
||||
*/
|
||||
|
||||
sll %l4, 1, %l5 ! l5 = WIM << 1
|
||||
srl %l4, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %l4
|
||||
! l4 = WIM >> (Number Windows - 1)
|
||||
or %l4, %l5, %l4 ! l4 = (WIM << 1) |
|
||||
! (WIM >> (Number Windows - 1))
|
||||
|
||||
/*
|
||||
* Now restore the window just as if we underflowed to it.
|
||||
*/
|
||||
|
||||
wr %l4, 0, %wim ! WIM = new WIM
|
||||
restore ! now into the tasks window
|
||||
|
||||
ldd [%g1 + CPU_STACK_FRAME_L0_OFFSET], %l0
|
||||
ldd [%g1 + CPU_STACK_FRAME_L2_OFFSET], %l2
|
||||
ldd [%g1 + CPU_STACK_FRAME_L4_OFFSET], %l4
|
||||
ldd [%g1 + CPU_STACK_FRAME_L6_OFFSET], %l6
|
||||
ldd [%g1 + CPU_STACK_FRAME_I0_OFFSET], %i0
|
||||
ldd [%g1 + CPU_STACK_FRAME_I2_OFFSET], %i2
|
||||
ldd [%g1 + CPU_STACK_FRAME_I4_OFFSET], %i4
|
||||
ldd [%g1 + CPU_STACK_FRAME_I6_FP_OFFSET], %i6
|
||||
! reload of sp clobbers ISF
|
||||
save ! Back to ISR dispatch window
|
||||
|
||||
good_task_window:
|
||||
|
||||
mov %l0, %psr ! **** DISABLE TRAPS ****
|
||||
! and restore condition codes.
|
||||
ld [%g1 + ISF_G1_OFFSET], %g1 ! restore g1
|
||||
jmp %l1 ! transfer control and
|
||||
rett %l2 ! go back to tasks window
|
||||
|
||||
/* end of file */
|
||||
@@ -1,518 +0,0 @@
|
||||
/* erc32.h
|
||||
*
|
||||
* This include file contains information pertaining to the ERC32.
|
||||
* The ERC32 is a custom SPARC V7 implementation based on the Cypress
|
||||
* 601/602 chipset. This CPU has a number of on-board peripherals and
|
||||
* was developed by the European Space Agency to target space applications.
|
||||
*
|
||||
* NOTE: Other than where absolutely required, this version currently
|
||||
* supports only the peripherals and bits used by the basic board
|
||||
* support package. This includes at least significant pieces of
|
||||
* the following items:
|
||||
*
|
||||
* + UART Channels A and B
|
||||
* + General Purpose Timer
|
||||
* + Real Time Clock
|
||||
* + Watchdog Timer (so it can be disabled)
|
||||
* + Control Register (so powerdown mode can be enabled)
|
||||
* + Memory Control Register
|
||||
* + Interrupt Control
|
||||
*
|
||||
* COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
* All rights assigned to U.S. Government, 1994.
|
||||
*
|
||||
* This material may be reproduced by or for the U.S. Government pursuant
|
||||
* to the copyright license under the clause at DFARS 252.227-7013. This
|
||||
* notice must appear in all copies of this file and its derivatives.
|
||||
*
|
||||
* Ported to ERC32 implementation of the SPARC by On-Line Applications
|
||||
* Research Corporation (OAR) under contract to the European Space
|
||||
* Agency (ESA).
|
||||
*
|
||||
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
|
||||
* European Space Agency.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _INCLUDE_ERC32_h
|
||||
#define _INCLUDE_ERC32_h
|
||||
|
||||
#include <rtems/score/sparc.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Interrupt Sources
|
||||
*
|
||||
* The interrupt source numbers directly map to the trap type and to
|
||||
* the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask,
|
||||
* and the Interrupt Pending Registers.
|
||||
*/
|
||||
|
||||
#define ERC32_INTERRUPT_MASKED_ERRORS 1
|
||||
#define ERC32_INTERRUPT_EXTERNAL_1 2
|
||||
#define ERC32_INTERRUPT_EXTERNAL_2 3
|
||||
#define ERC32_INTERRUPT_UART_A_RX_TX 4
|
||||
#define ERC32_INTERRUPT_UART_B_RX_TX 5
|
||||
#define ERC32_INTERRUPT_CORRECTABLE_MEMORY_ERROR 6
|
||||
#define ERC32_INTERRUPT_UART_ERROR 7
|
||||
#define ERC32_INTERRUPT_DMA_ACCESS_ERROR 8
|
||||
#define ERC32_INTERRUPT_DMA_TIMEOUT 9
|
||||
#define ERC32_INTERRUPT_EXTERNAL_3 10
|
||||
#define ERC32_INTERRUPT_EXTERNAL_4 11
|
||||
#define ERC32_INTERRUPT_GENERAL_PURPOSE_TIMER 12
|
||||
#define ERC32_INTERRUPT_REAL_TIME_CLOCK 13
|
||||
#define ERC32_INTERRUPT_EXTERNAL_5 14
|
||||
#define ERC32_INTERRUPT_WATCHDOG_TIMEOUT 15
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
/*
|
||||
* Trap Types for on-chip peripherals
|
||||
*
|
||||
* Source: Table 8 - Interrupt Trap Type and Default Priority Assignments
|
||||
*
|
||||
* NOTE: The priority level for each source corresponds to the least
|
||||
* significant nibble of the trap type.
|
||||
*/
|
||||
|
||||
#define ERC32_TRAP_TYPE( _source ) SPARC_ASYNCHRONOUS_TRAP((_source) + 0x10)
|
||||
|
||||
#define ERC32_TRAP_SOURCE( _trap ) ((_trap) - 0x10)
|
||||
|
||||
#define ERC32_Is_MEC_Trap( _trap ) \
|
||||
( (_trap) >= ERC32_TRAP_TYPE( ERC32_INTERRUPT_MASKED_ERRORS ) && \
|
||||
(_trap) <= ERC32_TRAP_TYPE( ERC32_INTERRUPT_WATCHDOG_TIMEOUT ) )
|
||||
|
||||
/*
|
||||
* Structure for ERC32 memory mapped registers.
|
||||
*
|
||||
* Source: Section 3.25.2 - Register Address Map
|
||||
*
|
||||
* NOTE: There is only one of these structures per CPU, its base address
|
||||
* is 0x01f80000, and the variable MEC is placed there by the
|
||||
* linkcmds file.
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
volatile unsigned32 Control; /* offset 0x00 */
|
||||
volatile unsigned32 Software_Reset; /* offset 0x04 */
|
||||
volatile unsigned32 Power_Down; /* offset 0x08 */
|
||||
volatile unsigned32 Unimplemented_0; /* offset 0x0c */
|
||||
volatile unsigned32 Memory_Configuration; /* offset 0x10 */
|
||||
volatile unsigned32 IO_Configuration; /* offset 0x14 */
|
||||
volatile unsigned32 Wait_State_Configuration; /* offset 0x18 */
|
||||
volatile unsigned32 Unimplemented_1; /* offset 0x1c */
|
||||
volatile unsigned32 Memory_Access_0; /* offset 0x20 */
|
||||
volatile unsigned32 Memory_Access_1; /* offset 0x24 */
|
||||
volatile unsigned32 Unimplemented_2[ 7 ]; /* offset 0x28 */
|
||||
volatile unsigned32 Interrupt_Shape; /* offset 0x44 */
|
||||
volatile unsigned32 Interrupt_Pending; /* offset 0x48 */
|
||||
volatile unsigned32 Interrupt_Mask; /* offset 0x4c */
|
||||
volatile unsigned32 Interrupt_Clear; /* offset 0x50 */
|
||||
volatile unsigned32 Interrupt_Force; /* offset 0x54 */
|
||||
volatile unsigned32 Unimplemented_3[ 2 ]; /* offset 0x58 */
|
||||
/* offset 0x60 */
|
||||
volatile unsigned32 Watchdog_Program_and_Timeout_Acknowledge;
|
||||
volatile unsigned32 Watchdog_Trap_Door_Set; /* offset 0x64 */
|
||||
volatile unsigned32 Unimplemented_4[ 6 ]; /* offset 0x68 */
|
||||
volatile unsigned32 Real_Time_Clock_Counter; /* offset 0x80 */
|
||||
volatile unsigned32 Real_Time_Clock_Scalar; /* offset 0x84 */
|
||||
volatile unsigned32 General_Purpose_Timer_Counter; /* offset 0x88 */
|
||||
volatile unsigned32 General_Purpose_Timer_Scalar; /* offset 0x8c */
|
||||
volatile unsigned32 Unimplemented_5[ 2 ]; /* offset 0x90 */
|
||||
volatile unsigned32 Timer_Control; /* offset 0x98 */
|
||||
volatile unsigned32 Unimplemented_6; /* offset 0x9c */
|
||||
volatile unsigned32 System_Fault_Status; /* offset 0xa0 */
|
||||
volatile unsigned32 First_Failing_Address; /* offset 0xa4 */
|
||||
volatile unsigned32 First_Failing_Data; /* offset 0xa8 */
|
||||
volatile unsigned32 First_Failing_Syndrome_and_Check_Bits;/* offset 0xac */
|
||||
volatile unsigned32 Error_and_Reset_Status; /* offset 0xb0 */
|
||||
volatile unsigned32 Error_Mask; /* offset 0xb4 */
|
||||
volatile unsigned32 Unimplemented_7[ 2 ]; /* offset 0xb8 */
|
||||
volatile unsigned32 Debug_Control; /* offset 0xc0 */
|
||||
volatile unsigned32 Breakpoint; /* offset 0xc4 */
|
||||
volatile unsigned32 Watchpoint; /* offset 0xc8 */
|
||||
volatile unsigned32 Unimplemented_8; /* offset 0xcc */
|
||||
volatile unsigned32 Test_Control; /* offset 0xd0 */
|
||||
volatile unsigned32 Test_Data; /* offset 0xd4 */
|
||||
volatile unsigned32 Unimplemented_9[ 2 ]; /* offset 0xd8 */
|
||||
volatile unsigned32 UART_Channel_A; /* offset 0xe0 */
|
||||
volatile unsigned32 UART_Channel_B; /* offset 0xe4 */
|
||||
volatile unsigned32 UART_Status; /* offset 0xe8 */
|
||||
} ERC32_Register_Map;
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The following constants are intended to be used ONLY in assembly
|
||||
* language files.
|
||||
*
|
||||
* NOTE: The intended style of usage is to load the address of MEC
|
||||
* into a register and then use these as displacements from
|
||||
* that register.
|
||||
*/
|
||||
|
||||
#ifdef ASM
|
||||
|
||||
#define ERC32_MEC_CONTROL_OFFSET 0x00
|
||||
#define ERC32_MEC_SOFTWARE_RESET_OFFSET 0x04
|
||||
#define ERC32_MEC_POWER_DOWN_OFFSET 0x08
|
||||
#define ERC32_MEC_UNIMPLEMENTED_0_OFFSET 0x0C
|
||||
#define ERC32_MEC_MEMORY_CONFIGURATION_OFFSET 0x10
|
||||
#define ERC32_MEC_IO_CONFIGURATION_OFFSET 0x14
|
||||
#define ERC32_MEC_WAIT_STATE_CONFIGURATION_OFFSET 0x18
|
||||
#define ERC32_MEC_UNIMPLEMENTED_1_OFFSET 0x1C
|
||||
#define ERC32_MEC_MEMORY_ACCESS_0_OFFSET 0x20
|
||||
#define ERC32_MEC_MEMORY_ACCESS_1_OFFSET 0x24
|
||||
#define ERC32_MEC_UNIMPLEMENTED_2_OFFSET 0x28
|
||||
#define ERC32_MEC_INTERRUPT_SHAPE_OFFSET 0x44
|
||||
#define ERC32_MEC_INTERRUPT_PENDING_OFFSET 0x48
|
||||
#define ERC32_MEC_INTERRUPT_MASK_OFFSET 0x4C
|
||||
#define ERC32_MEC_INTERRUPT_CLEAR_OFFSET 0x50
|
||||
#define ERC32_MEC_INTERRUPT_FORCE_OFFSET 0x54
|
||||
#define ERC32_MEC_UNIMPLEMENTED_3_OFFSET 0x58
|
||||
#define ERC32_MEC_WATCHDOG_PROGRAM_AND_TIMEOUT_ACKNOWLEDGE_OFFSET 0x60
|
||||
#define ERC32_MEC_WATCHDOG_TRAP_DOOR_SET_OFFSET 0x64
|
||||
#define ERC32_MEC_UNIMPLEMENTED_4_OFFSET 0x6C
|
||||
#define ERC32_MEC_REAL_TIME_CLOCK_COUNTER_OFFSET 0x80
|
||||
#define ERC32_MEC_REAL_TIME_CLOCK_SCALAR_OFFSET 0x84
|
||||
#define ERC32_MEC_GENERAL_PURPOSE_TIMER_COUNTER_OFFSET 0x88
|
||||
#define ERC32_MEC_GENERAL_PURPOSE_TIMER_SCALAR_OFFSET 0x8C
|
||||
#define ERC32_MEC_UNIMPLEMENTED_5_OFFSET 0x90
|
||||
#define ERC32_MEC_TIMER_CONTROL_OFFSET 0x98
|
||||
#define ERC32_MEC_UNIMPLEMENTED_6_OFFSET 0x9C
|
||||
#define ERC32_MEC_SYSTEM_FAULT_STATUS_OFFSET 0xA0
|
||||
#define ERC32_MEC_FIRST_FAILING_ADDRESS_OFFSET 0xA4
|
||||
#define ERC32_MEC_FIRST_FAILING_DATA_OFFSET 0xA8
|
||||
#define ERC32_MEC_FIRST_FAILING_SYNDROME_AND_CHECK_BITS_OFFSET 0xAC
|
||||
#define ERC32_MEC_ERROR_AND_RESET_STATUS_OFFSET 0xB0
|
||||
#define ERC32_MEC_ERROR_MASK_OFFSET 0xB4
|
||||
#define ERC32_MEC_UNIMPLEMENTED_7_OFFSET 0xB8
|
||||
#define ERC32_MEC_DEBUG_CONTROL_OFFSET 0xC0
|
||||
#define ERC32_MEC_BREAKPOINT_OFFSET 0xC4
|
||||
#define ERC32_MEC_WATCHPOINT_OFFSET 0xC8
|
||||
#define ERC32_MEC_UNIMPLEMENTED_8_OFFSET 0xCC
|
||||
#define ERC32_MEC_TEST_CONTROL_OFFSET 0xD0
|
||||
#define ERC32_MEC_TEST_DATA_OFFSET 0xD4
|
||||
#define ERC32_MEC_UNIMPLEMENTED_9_OFFSET 0xD8
|
||||
#define ERC32_MEC_UART_CHANNEL_A_OFFSET 0xE0
|
||||
#define ERC32_MEC_UART_CHANNEL_B_OFFSET 0xE4
|
||||
#define ERC32_MEC_UART_STATUS_OFFSET 0xE8
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The following defines the bits in the Configuration Register.
|
||||
*/
|
||||
|
||||
#define ERC32_CONFIGURATION_POWER_DOWN_MASK 0x00000001
|
||||
#define ERC32_CONFIGURATION_POWER_DOWN_ALLOWED 0x00000001
|
||||
#define ERC32_CONFIGURATION_POWER_DOWN_DISABLED 0x00000000
|
||||
|
||||
#define ERC32_CONFIGURATION_SOFTWARE_RESET_MASK 0x00000002
|
||||
#define ERC32_CONFIGURATION_SOFTWARE_RESET_ALLOWED 0x00000002
|
||||
#define ERC32_CONFIGURATION_SOFTWARE_RESET_DISABLED 0x00000000
|
||||
|
||||
#define ERC32_CONFIGURATION_BUS_TIMEOUT_MASK 0x00000004
|
||||
#define ERC32_CONFIGURATION_BUS_TIMEOUT_ENABLED 0x00000004
|
||||
#define ERC32_CONFIGURATION_BUS_TIMEOUT_DISABLED 0x00000000
|
||||
|
||||
#define ERC32_CONFIGURATION_ACCESS_PROTECTION_MASK 0x00000008
|
||||
#define ERC32_CONFIGURATION_ACCESS_PROTECTION_ENABLED 0x00000008
|
||||
#define ERC32_CONFIGURATION_ACCESS_PROTECTION_DISABLED 0x00000000
|
||||
|
||||
|
||||
/*
|
||||
* The following defines the bits in the Memory Configuration Register.
|
||||
*/
|
||||
|
||||
#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_MASK 0x00001C00
|
||||
#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_256K ( 0 << 10 )
|
||||
#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_512K ( 1 << 10 )
|
||||
#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_1MB ( 2 << 10 )
|
||||
#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_2MB ( 3 << 10 )
|
||||
#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_4MB ( 4 << 10 )
|
||||
#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_8MB ( 5 << 10 )
|
||||
#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_16MB ( 6 << 10 )
|
||||
#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_32MB ( 7 << 10 )
|
||||
|
||||
#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_MASK 0x001C0000
|
||||
#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_4K ( 0 << 18 )
|
||||
#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_8K ( 1 << 18 )
|
||||
#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_16K ( 2 << 18 )
|
||||
#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_32K ( 3 << 18 )
|
||||
#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_64K ( 4 << 18 )
|
||||
#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_128K ( 5 << 18 )
|
||||
#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_256K ( 6 << 18 )
|
||||
#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_512K ( 7 << 18 )
|
||||
|
||||
/*
|
||||
* The following defines the bits in the Timer Control Register.
|
||||
*/
|
||||
|
||||
#define ERC32_MEC_TIMER_CONTROL_GCR 0x00000001 /* 1 = reload at 0 */
|
||||
/* 0 = stop at 0 */
|
||||
#define ERC32_MEC_TIMER_CONTROL_GCL 0x00000002 /* 1 = load and start */
|
||||
/* 0 = no function */
|
||||
#define ERC32_MEC_TIMER_CONTROL_GSE 0x00000004 /* 1 = enable counting */
|
||||
/* 0 = hold scalar and counter */
|
||||
#define ERC32_MEC_TIMER_CONTROL_GSL 0x00000008 /* 1 = load scalar and start */
|
||||
/* 0 = no function */
|
||||
|
||||
#define ERC32_MEC_TIMER_CONTROL_RTCCR 0x00000100 /* 1 = reload at 0 */
|
||||
/* 0 = stop at 0 */
|
||||
#define ERC32_MEC_TIMER_CONTROL_RTCCL 0x00000200 /* 1 = load and start */
|
||||
/* 0 = no function */
|
||||
#define ERC32_MEC_TIMER_CONTROL_RTCSE 0x00000400 /* 1 = enable counting */
|
||||
/* 0 = hold scalar and counter */
|
||||
#define ERC32_MEC_TIMER_CONTROL_RTCSL 0x00000800 /* 1 = load scalar and start */
|
||||
/* 0 = no function */
|
||||
|
||||
/*
|
||||
* The following defines the bits in the UART Control Registers.
|
||||
*
|
||||
* NOTE: Same bits in UART channels A and B.
|
||||
*/
|
||||
|
||||
#define ERC32_MEC_UART_CONTROL_RTD 0x000000FF /* RX/TX data */
|
||||
#define ERC32_MEC_UART_CONTROL_DR 0x00000100 /* RX Data Ready */
|
||||
#define ERC32_MEC_UART_CONTROL_TSE 0x00000200 /* TX Send Empty */
|
||||
/* (i.e. no data to send) */
|
||||
#define ERC32_MEC_UART_CONTROL_THE 0x00000400 /* TX Hold Empty */
|
||||
/* (i.e. ready to load) */
|
||||
|
||||
/*
|
||||
* The following defines the bits in the MEC UART Control Registers.
|
||||
*/
|
||||
|
||||
#define ERC32_MEC_UART_STATUS_DR 0x00000001 /* Data Ready */
|
||||
#define ERC32_MEC_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */
|
||||
#define ERC32_MEC_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */
|
||||
#define ERC32_MEC_UART_STATUS_FE 0x00000010 /* RX Framing Error */
|
||||
#define ERC32_MEC_UART_STATUS_PE 0x00000020 /* RX Parity Error */
|
||||
#define ERC32_MEC_UART_STATUS_OE 0x00000040 /* RX Overrun Error */
|
||||
#define ERC32_MEC_UART_STATUS_CU 0x00000080 /* Clear Errors */
|
||||
#define ERC32_MEC_UART_STATUS_TXE 0x00000006 /* TX Empty */
|
||||
|
||||
#define ERC32_MEC_UART_STATUS_DRA (ERC32_MEC_UART_STATUS_DR << 0)
|
||||
#define ERC32_MEC_UART_STATUS_TSEA (ERC32_MEC_UART_STATUS_TSE << 0)
|
||||
#define ERC32_MEC_UART_STATUS_THEA (ERC32_MEC_UART_STATUS_THE << 0)
|
||||
#define ERC32_MEC_UART_STATUS_FEA (ERC32_MEC_UART_STATUS_FE << 0)
|
||||
#define ERC32_MEC_UART_STATUS_PEA (ERC32_MEC_UART_STATUS_PE << 0)
|
||||
#define ERC32_MEC_UART_STATUS_OEA (ERC32_MEC_UART_STATUS_OE << 0)
|
||||
#define ERC32_MEC_UART_STATUS_CUA (ERC32_MEC_UART_STATUS_CU << 0)
|
||||
#define ERC32_MEC_UART_STATUS_TXEA (ERC32_MEC_UART_STATUS_TXE << 0)
|
||||
|
||||
#define ERC32_MEC_UART_STATUS_DRB (ERC32_MEC_UART_STATUS_DR << 16)
|
||||
#define ERC32_MEC_UART_STATUS_TSEB (ERC32_MEC_UART_STATUS_TSE << 16)
|
||||
#define ERC32_MEC_UART_STATUS_THEB (ERC32_MEC_UART_STATUS_THE << 16)
|
||||
#define ERC32_MEC_UART_STATUS_FEB (ERC32_MEC_UART_STATUS_FE << 16)
|
||||
#define ERC32_MEC_UART_STATUS_PEB (ERC32_MEC_UART_STATUS_PE << 16)
|
||||
#define ERC32_MEC_UART_STATUS_OEB (ERC32_MEC_UART_STATUS_OE << 16)
|
||||
#define ERC32_MEC_UART_STATUS_CUB (ERC32_MEC_UART_STATUS_CU << 16)
|
||||
#define ERC32_MEC_UART_STATUS_TXEB (ERC32_MEC_UART_STATUS_TXE << 16)
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
/*
|
||||
* This is used to manipulate the on-chip registers.
|
||||
*
|
||||
* The following symbol must be defined in the linkcmds file and point
|
||||
* to the correct location.
|
||||
*/
|
||||
|
||||
extern ERC32_Register_Map ERC32_MEC;
|
||||
|
||||
/*
|
||||
* Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask,
|
||||
* and the Interrupt Pending Registers.
|
||||
*
|
||||
* NOTE: For operations which are not atomic, this code disables interrupts
|
||||
* to guarantee there are no intervening accesses to the same register.
|
||||
* The operations which read the register, modify the value and then
|
||||
* store the result back are vulnerable.
|
||||
*/
|
||||
|
||||
#define ERC32_Clear_interrupt( _source ) \
|
||||
do { \
|
||||
ERC32_MEC.Interrupt_Clear = (1 << (_source)); \
|
||||
} while (0)
|
||||
|
||||
#define ERC32_Force_interrupt( _source ) \
|
||||
do { \
|
||||
ERC32_MEC.Interrupt_Force = (1 << (_source)); \
|
||||
} while (0)
|
||||
|
||||
#define ERC32_Is_interrupt_pending( _source ) \
|
||||
(ERC32_MEC.Interrupt_Pending & (1 << (_source)))
|
||||
|
||||
#define ERC32_Is_interrupt_masked( _source ) \
|
||||
(ERC32_MEC.Interrupt_Masked & (1 << (_source)))
|
||||
|
||||
#define ERC32_Mask_interrupt( _source ) \
|
||||
do { \
|
||||
unsigned32 _level; \
|
||||
\
|
||||
sparc_disable_interrupts( _level ); \
|
||||
ERC32_MEC.Interrupt_Mask |= (1 << (_source)); \
|
||||
sparc_enable_interrupts( _level ); \
|
||||
} while (0)
|
||||
|
||||
#define ERC32_Unmask_interrupt( _source ) \
|
||||
do { \
|
||||
unsigned32 _level; \
|
||||
\
|
||||
sparc_disable_interrupts( _level ); \
|
||||
ERC32_MEC.Interrupt_Mask &= ~(1 << (_source)); \
|
||||
sparc_enable_interrupts( _level ); \
|
||||
} while (0)
|
||||
|
||||
#define ERC32_Disable_interrupt( _source, _previous ) \
|
||||
do { \
|
||||
unsigned32 _level; \
|
||||
unsigned32 _mask = 1 << (_source); \
|
||||
\
|
||||
sparc_disable_interrupts( _level ); \
|
||||
(_previous) = ERC32_MEC.Interrupt_Mask; \
|
||||
ERC32_MEC.Interrupt_Mask = _previous | _mask; \
|
||||
sparc_enable_interrupts( _level ); \
|
||||
(_previous) &= ~_mask; \
|
||||
} while (0)
|
||||
|
||||
#define ERC32_Restore_interrupt( _source, _previous ) \
|
||||
do { \
|
||||
unsigned32 _level; \
|
||||
unsigned32 _mask = 1 << (_source); \
|
||||
\
|
||||
sparc_disable_interrupts( _level ); \
|
||||
ERC32_MEC.Interrupt_Mask = \
|
||||
(ERC32_MEC.Interrupt_Mask & ~_mask) | (_previous); \
|
||||
sparc_enable_interrupts( _level ); \
|
||||
} while (0)
|
||||
|
||||
/*
|
||||
* The following macros attempt to hide the fact that the General Purpose
|
||||
* Timer and Real Time Clock Timer share the Timer Control Register. Because
|
||||
* the Timer Control Register is write only, we must mirror it in software
|
||||
* and insure that writes to one timer do not alter the current settings
|
||||
* and status of the other timer.
|
||||
*
|
||||
* This code promotes the view that the two timers are completely independent.
|
||||
* By exclusively using the routines below to access the Timer Control
|
||||
* Register, the application can view the system as having a General Purpose
|
||||
* Timer Control Register and a Real Time Clock Timer Control Register
|
||||
* rather than the single shared value.
|
||||
*
|
||||
* Each logical timer control register is organized as follows:
|
||||
*
|
||||
* D0 - Counter Reload
|
||||
* 1 = reload counter at zero and restart
|
||||
* 0 = stop counter at zero
|
||||
*
|
||||
* D1 - Counter Load
|
||||
* 1 = load counter with preset value and restart
|
||||
* 0 = no function
|
||||
*
|
||||
* D2 - Enable
|
||||
* 1 = enable counting
|
||||
* 0 = hold scaler and counter
|
||||
*
|
||||
* D2 - Scaler Load
|
||||
* 1 = load scalar with preset value and restart
|
||||
* 0 = no function
|
||||
*
|
||||
* To insure the management of the mirror is atomic, we disable interrupts
|
||||
* around updates.
|
||||
*/
|
||||
|
||||
#define ERC32_MEC_TIMER_COUNTER_RELOAD_AT_ZERO 0x00000001
|
||||
#define ERC32_MEC_TIMER_COUNTER_STOP_AT_ZERO 0x00000000
|
||||
|
||||
#define ERC32_MEC_TIMER_COUNTER_LOAD_COUNTER 0x00000002
|
||||
|
||||
#define ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING 0x00000004
|
||||
#define ERC32_MEC_TIMER_COUNTER_DISABLE_COUNTING 0x00000000
|
||||
|
||||
#define ERC32_MEC_TIMER_COUNTER_LOAD_SCALER 0x00000008
|
||||
|
||||
#define ERC32_MEC_TIMER_COUNTER_RELOAD_MASK 0x00000001
|
||||
#define ERC32_MEC_TIMER_COUNTER_ENABLE_MASK 0x00000004
|
||||
|
||||
#define ERC32_MEC_TIMER_COUNTER_DEFINED_MASK 0x0000000F
|
||||
#define ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000005
|
||||
|
||||
extern unsigned32 _ERC32_MEC_Timer_Control_Mirror;
|
||||
|
||||
/*
|
||||
* This macros manipulate the General Purpose Timer portion of the
|
||||
* Timer Control register and promote the view that there are actually
|
||||
* two independent Timer Control Registers.
|
||||
*/
|
||||
|
||||
#define ERC32_MEC_Set_General_Purpose_Timer_Control( _value ) \
|
||||
do { \
|
||||
unsigned32 _level; \
|
||||
unsigned32 _control; \
|
||||
unsigned32 __value; \
|
||||
\
|
||||
__value = ((_value) & 0x0f); \
|
||||
sparc_disable_interrupts( _level ); \
|
||||
_control = _ERC32_MEC_Timer_Control_Mirror; \
|
||||
_control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK << 8; \
|
||||
_ERC32_MEC_Timer_Control_Mirror = _control | _value; \
|
||||
_control &= (ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK << 8); \
|
||||
_control |= __value; \
|
||||
/* printf( "GPT 0x%x 0x%x 0x%x\n", _value, __value, _control ); */ \
|
||||
ERC32_MEC.Timer_Control = _control; \
|
||||
sparc_enable_interrupts( _level ); \
|
||||
} while ( 0 )
|
||||
|
||||
#define ERC32_MEC_Get_General_Purpose_Timer_Control( _value ) \
|
||||
do { \
|
||||
(_value) = _ERC32_MEC_Timer_Control_Mirror & 0xf; \
|
||||
} while ( 0 )
|
||||
|
||||
/*
|
||||
* This macros manipulate the Real Timer Clock Timer portion of the
|
||||
* Timer Control register and promote the view that there are actually
|
||||
* two independent Timer Control Registers.
|
||||
*/
|
||||
|
||||
#define ERC32_MEC_Set_Real_Time_Clock_Timer_Control( _value ) \
|
||||
do { \
|
||||
unsigned32 _level; \
|
||||
unsigned32 _control; \
|
||||
unsigned32 __value; \
|
||||
\
|
||||
__value = ((_value) & 0x0f) << 8; \
|
||||
sparc_disable_interrupts( _level ); \
|
||||
_control = _ERC32_MEC_Timer_Control_Mirror; \
|
||||
_control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK; \
|
||||
_ERC32_MEC_Timer_Control_Mirror = _control | _value; \
|
||||
_control &= ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK; \
|
||||
_control |= __value; \
|
||||
/* printf( "RTC 0x%x 0x%x 0x%x\n", _value, __value, _control ); */ \
|
||||
ERC32_MEC.Timer_Control = _control; \
|
||||
sparc_enable_interrupts( _level ); \
|
||||
} while ( 0 )
|
||||
|
||||
#define ERC32_MEC_Get_Real_Time_Clock_Timer_Control( _value ) \
|
||||
do { \
|
||||
(_value) = _ERC32_MEC_Timer_Control_Mirror & 0xf; \
|
||||
} while ( 0 )
|
||||
|
||||
|
||||
#endif /* !ASM */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* !_INCLUDE_ERC32_h */
|
||||
/* end of include file */
|
||||
|
||||
@@ -1,58 +0,0 @@
|
||||
/* rtems.s
|
||||
*
|
||||
* This file contains the single entry point code for
|
||||
* the SPARC port of RTEMS.
|
||||
*
|
||||
* COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
* All rights assigned to U.S. Government, 1994.
|
||||
*
|
||||
* This material may be reproduced by or for the U.S. Government pursuant
|
||||
* to the copyright license under the clause at DFARS 252.227-7013. This
|
||||
* notice must appear in all copies of this file and its derivatives.
|
||||
*
|
||||
* Ported to ERC32 implementation of the SPARC by On-Line Applications
|
||||
* Research Corporation (OAR) under contract to the European Space
|
||||
* Agency (ESA).
|
||||
*
|
||||
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
|
||||
* European Space Agency.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <asm.h>
|
||||
|
||||
/*
|
||||
* RTEMS
|
||||
*
|
||||
* This routine jumps to the directive indicated in the
|
||||
* CPU defined register. This routine is used when RTEMS is
|
||||
* linked by itself and placed in ROM. This routine is the
|
||||
* first address in the ROM space for RTEMS. The user "calls"
|
||||
* this address with the directive arguments in the normal place.
|
||||
* This routine then jumps indirectly to the correct directive
|
||||
* preserving the arguments. The directive should not realize
|
||||
* it has been "wrapped" in this way. The table "_Entry_points"
|
||||
* is used to look up the directive.
|
||||
*
|
||||
* void RTEMS()
|
||||
*/
|
||||
|
||||
.align 4
|
||||
PUBLIC(RTEMS)
|
||||
SYM(RTEMS):
|
||||
/*
|
||||
* g2 was chosen because gcc uses it as a scratch register in
|
||||
* similar code scenarios and the other locals, ins, and outs
|
||||
* are off limits to this routine unless it does a "save" and
|
||||
* copies its in registers to the outs which only works up until
|
||||
* 6 parameters. Best to take the simple approach in this case.
|
||||
*/
|
||||
sethi SYM(_Entry_points), %g2
|
||||
or %g2, %lo(SYM(_Entry_points)), %g2
|
||||
sll %g1, 2, %g1
|
||||
add %g1, %g2, %g2
|
||||
jmp %g2
|
||||
nop
|
||||
|
||||
@@ -1,275 +0,0 @@
|
||||
/* sparc.h
|
||||
*
|
||||
* This include file contains information pertaining to the SPARC
|
||||
* processor family.
|
||||
*
|
||||
* COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
* All rights assigned to U.S. Government, 1994.
|
||||
*
|
||||
* This material may be reproduced by or for the U.S. Government pursuant
|
||||
* to the copyright license under the clause at DFARS 252.227-7013. This
|
||||
* notice must appear in all copies of this file and its derivatives.
|
||||
*
|
||||
* Ported to ERC32 implementation of the SPARC by On-Line Applications
|
||||
* Research Corporation (OAR) under contract to the European Space
|
||||
* Agency (ESA).
|
||||
*
|
||||
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
|
||||
* European Space Agency.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _INCLUDE_SPARC_h
|
||||
#define _INCLUDE_SPARC_h
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The following define the CPU Family and Model within the family
|
||||
*
|
||||
* NOTE: The string "REPLACE_THIS_WITH_THE_CPU_MODEL" is replaced
|
||||
* with the name of the appropriate macro for this target CPU.
|
||||
*/
|
||||
|
||||
#ifdef sparc
|
||||
#undef sparc
|
||||
#endif
|
||||
#define sparc
|
||||
|
||||
#ifdef REPLACE_THIS_WITH_THE_CPU_MODEL
|
||||
#undef REPLACE_THIS_WITH_THE_CPU_MODEL
|
||||
#endif
|
||||
#define REPLACE_THIS_WITH_THE_CPU_MODEL
|
||||
|
||||
#ifdef REPLACE_THIS_WITH_THE_BSP
|
||||
#undef REPLACE_THIS_WITH_THE_BSP
|
||||
#endif
|
||||
#define REPLACE_THIS_WITH_THE_BSP
|
||||
|
||||
/*
|
||||
* This file contains the information required to build
|
||||
* RTEMS for a particular member of the "sparc" family. It does
|
||||
* this by setting variables to indicate which implementation
|
||||
* dependent features are present in a particular member
|
||||
* of the family.
|
||||
*
|
||||
* Currently recognized feature flags:
|
||||
*
|
||||
* + SPARC_HAS_FPU
|
||||
* 0 - no HW FPU
|
||||
* 1 - has HW FPU (assumed to be compatible w/90C602)
|
||||
*
|
||||
* + SPARC_HAS_BITSCAN
|
||||
* 0 - does not have scan instructions
|
||||
* 1 - has scan instruction (not currently implemented)
|
||||
*
|
||||
* + SPARC_NUMBER_OF_REGISTER_WINDOWS
|
||||
* 8 is the most common number supported by SPARC implementations.
|
||||
* SPARC_PSR_CWP_MASK is derived from this value.
|
||||
*
|
||||
* + SPARC_HAS_LOW_POWER_MODE
|
||||
* 0 - does not have low power mode support (or not supported)
|
||||
* 1 - has low power mode and thus a CPU model dependent idle task.
|
||||
*
|
||||
*/
|
||||
|
||||
#if defined(erc32)
|
||||
|
||||
#define CPU_MODEL_NAME "erc32"
|
||||
#define SPARC_HAS_FPU 1
|
||||
#define SPARC_HAS_BITSCAN 0
|
||||
#define SPARC_NUMBER_OF_REGISTER_WINDOWS 8
|
||||
#define SPARC_HAS_LOW_POWER_MODE 1
|
||||
|
||||
#else
|
||||
|
||||
#error "Unsupported CPU Model"
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Define the name of the CPU family.
|
||||
*/
|
||||
|
||||
#define CPU_NAME "SPARC"
|
||||
|
||||
/*
|
||||
* Miscellaneous constants
|
||||
*/
|
||||
|
||||
/*
|
||||
* PSR masks and starting bit positions
|
||||
*
|
||||
* NOTE: Reserved bits are ignored.
|
||||
*/
|
||||
|
||||
#if (SPARC_NUMBER_OF_REGISTER_WINDOWS == 8)
|
||||
#define SPARC_PSR_CWP_MASK 0x07 /* bits 0 - 4 */
|
||||
#elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 16)
|
||||
#define SPARC_PSR_CWP_MASK 0x0F /* bits 0 - 4 */
|
||||
#elif (SPARC_NUMBER_OF_REGISTER_WINDOWS == 32)
|
||||
#define SPARC_PSR_CWP_MASK 0x1F /* bits 0 - 4 */
|
||||
#else
|
||||
#error "Unsupported number of register windows for this cpu"
|
||||
#endif
|
||||
|
||||
#define SPARC_PSR_ET_MASK 0x00000020 /* bit 5 */
|
||||
#define SPARC_PSR_PS_MASK 0x00000040 /* bit 6 */
|
||||
#define SPARC_PSR_S_MASK 0x00000080 /* bit 7 */
|
||||
#define SPARC_PSR_PIL_MASK 0x00000F00 /* bits 8 - 11 */
|
||||
#define SPARC_PSR_EF_MASK 0x00001000 /* bit 12 */
|
||||
#define SPARC_PSR_EC_MASK 0x00002000 /* bit 13 */
|
||||
#define SPARC_PSR_ICC_MASK 0x00F00000 /* bits 20 - 23 */
|
||||
#define SPARC_PSR_VER_MASK 0x0F000000 /* bits 24 - 27 */
|
||||
#define SPARC_PSR_IMPL_MASK 0xF0000000 /* bits 28 - 31 */
|
||||
|
||||
#define SPARC_PSR_CWP_BIT_POSITION 0 /* bits 0 - 4 */
|
||||
#define SPARC_PSR_ET_BIT_POSITION 5 /* bit 5 */
|
||||
#define SPARC_PSR_PS_BIT_POSITION 6 /* bit 6 */
|
||||
#define SPARC_PSR_S_BIT_POSITION 7 /* bit 7 */
|
||||
#define SPARC_PSR_PIL_BIT_POSITION 8 /* bits 8 - 11 */
|
||||
#define SPARC_PSR_EF_BIT_POSITION 12 /* bit 12 */
|
||||
#define SPARC_PSR_EC_BIT_POSITION 13 /* bit 13 */
|
||||
#define SPARC_PSR_ICC_BIT_POSITION 20 /* bits 20 - 23 */
|
||||
#define SPARC_PSR_VER_BIT_POSITION 24 /* bits 24 - 27 */
|
||||
#define SPARC_PSR_IMPL_BIT_POSITION 28 /* bits 28 - 31 */
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
/*
|
||||
* Standard nop
|
||||
*/
|
||||
|
||||
#define nop() \
|
||||
do { \
|
||||
asm volatile ( "nop" ); \
|
||||
} while ( 0 )
|
||||
|
||||
/*
|
||||
* Get and set the PSR
|
||||
*/
|
||||
|
||||
#define sparc_get_psr( _psr ) \
|
||||
do { \
|
||||
(_psr) = 0; \
|
||||
asm volatile( "rd %%psr, %0" : "=r" (_psr) : "0" (_psr) ); \
|
||||
} while ( 0 )
|
||||
|
||||
#define sparc_set_psr( _psr ) \
|
||||
do { \
|
||||
asm volatile ( "mov %0, %%psr " : "=r" ((_psr)) : "0" ((_psr)) ); \
|
||||
nop(); \
|
||||
nop(); \
|
||||
nop(); \
|
||||
} while ( 0 )
|
||||
|
||||
/*
|
||||
* Get and set the TBR
|
||||
*/
|
||||
|
||||
#define sparc_get_tbr( _tbr ) \
|
||||
do { \
|
||||
(_tbr) = 0; /* to avoid unitialized warnings */ \
|
||||
asm volatile( "rd %%tbr, %0" : "=r" (_tbr) : "0" (_tbr) ); \
|
||||
} while ( 0 )
|
||||
|
||||
#define sparc_set_tbr( _tbr ) \
|
||||
do { \
|
||||
asm volatile( "wr %0, 0, %%tbr" : "=r" (_tbr) : "0" (_tbr) ); \
|
||||
} while ( 0 )
|
||||
|
||||
/*
|
||||
* Get and set the WIM
|
||||
*/
|
||||
|
||||
#define sparc_get_wim( _wim ) \
|
||||
do { \
|
||||
asm volatile( "rd %%wim, %0" : "=r" (_wim) : "0" (_wim) ); \
|
||||
} while ( 0 )
|
||||
|
||||
#define sparc_set_wim( _wim ) \
|
||||
do { \
|
||||
asm volatile( "wr %0, %%wim" : "=r" (_wim) : "0" (_wim) ); \
|
||||
nop(); \
|
||||
nop(); \
|
||||
nop(); \
|
||||
} while ( 0 )
|
||||
|
||||
/*
|
||||
* Get and set the Y
|
||||
*/
|
||||
|
||||
#define sparc_get_y( _y ) \
|
||||
do { \
|
||||
asm volatile( "rd %%y, %0" : "=r" (_y) : "0" (_y) ); \
|
||||
} while ( 0 )
|
||||
|
||||
#define sparc_set_y( _y ) \
|
||||
do { \
|
||||
asm volatile( "wr %0, %%y" : "=r" (_y) : "0" (_y) ); \
|
||||
} while ( 0 )
|
||||
|
||||
/*
|
||||
* Manipulate the interrupt level in the psr
|
||||
*
|
||||
*/
|
||||
|
||||
#define sparc_disable_interrupts( _level ) \
|
||||
do { \
|
||||
register unsigned int _newlevel; \
|
||||
\
|
||||
sparc_get_psr( _level ); \
|
||||
(_newlevel) = (_level) | SPARC_PSR_PIL_MASK; \
|
||||
sparc_set_psr( _newlevel ); \
|
||||
} while ( 0 )
|
||||
|
||||
#define sparc_enable_interrupts( _level ) \
|
||||
do { \
|
||||
unsigned int _tmp; \
|
||||
\
|
||||
sparc_get_psr( _tmp ); \
|
||||
_tmp &= ~SPARC_PSR_PIL_MASK; \
|
||||
_tmp |= (_level) & SPARC_PSR_PIL_MASK; \
|
||||
sparc_set_psr( _tmp ); \
|
||||
} while ( 0 )
|
||||
|
||||
#define sparc_flash_interrupts( _level ) \
|
||||
do { \
|
||||
register unsigned32 _ignored = 0; \
|
||||
\
|
||||
sparc_enable_interrupts( (_level) ); \
|
||||
sparc_disable_interrupts( _ignored ); \
|
||||
} while ( 0 )
|
||||
|
||||
#define sparc_set_interrupt_level( _new_level ) \
|
||||
do { \
|
||||
register unsigned32 _new_psr_level = 0; \
|
||||
\
|
||||
sparc_get_psr( _new_psr_level ); \
|
||||
_new_psr_level &= ~SPARC_PSR_PIL_MASK; \
|
||||
_new_psr_level |= \
|
||||
(((_new_level) << SPARC_PSR_PIL_BIT_POSITION) & SPARC_PSR_PIL_MASK); \
|
||||
sparc_set_psr( _new_psr_level ); \
|
||||
} while ( 0 )
|
||||
|
||||
#define sparc_get_interrupt_level( _level ) \
|
||||
do { \
|
||||
register unsigned32 _psr_level = 0; \
|
||||
\
|
||||
sparc_get_psr( _psr_level ); \
|
||||
(_level) = \
|
||||
(_psr_level & SPARC_PSR_PIL_MASK) >> SPARC_PSR_PIL_BIT_POSITION; \
|
||||
} while ( 0 )
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ! _INCLUDE_SPARC_h */
|
||||
/* end of include file */
|
||||
@@ -1,64 +0,0 @@
|
||||
/* sparctypes.h
|
||||
*
|
||||
* This include file contains type definitions pertaining to the
|
||||
* SPARC processor family.
|
||||
*
|
||||
* COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
* All rights assigned to U.S. Government, 1994.
|
||||
*
|
||||
* This material may be reproduced by or for the U.S. Government pursuant
|
||||
* to the copyright license under the clause at DFARS 252.227-7013. This
|
||||
* notice must appear in all copies of this file and its derivatives.
|
||||
*
|
||||
* Ported to ERC32 implementation of the SPARC by On-Line Applications
|
||||
* Research Corporation (OAR) under contract to the European Space
|
||||
* Agency (ESA).
|
||||
*
|
||||
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
|
||||
* European Space Agency.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef __SPARC_TYPES_h
|
||||
#define __SPARC_TYPES_h
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* This section defines the basic types for this processor.
|
||||
*/
|
||||
|
||||
typedef unsigned char unsigned8; /* unsigned 8-bit integer */
|
||||
typedef unsigned short unsigned16; /* unsigned 16-bit integer */
|
||||
typedef unsigned int unsigned32; /* unsigned 32-bit integer */
|
||||
typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
|
||||
|
||||
typedef unsigned16 Priority_Bit_map_control;
|
||||
|
||||
typedef signed char signed8; /* 8-bit signed integer */
|
||||
typedef signed short signed16; /* 16-bit signed integer */
|
||||
typedef signed int signed32; /* 32-bit signed integer */
|
||||
typedef signed long long signed64; /* 64 bit signed integer */
|
||||
|
||||
typedef unsigned32 boolean; /* Boolean value */
|
||||
|
||||
typedef float single_precision; /* single precision float */
|
||||
typedef double double_precision; /* double precision float */
|
||||
|
||||
typedef void sparc_isr;
|
||||
typedef void ( *sparc_isr_entry )( void );
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* !ASM */
|
||||
|
||||
#endif
|
||||
/* end of include file */
|
||||
@@ -34,20 +34,18 @@
|
||||
#define MALLOC_0_RETURNS_NULL
|
||||
#endif
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <sys/times.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <setjmp.h>
|
||||
#include <signal.h>
|
||||
#include <time.h>
|
||||
#include <sys/time.h>
|
||||
#include <sys/types.h>
|
||||
#include <errno.h>
|
||||
#include <unistd.h>
|
||||
#include <sys/ipc.h>
|
||||
#include <sys/shm.h>
|
||||
#include <sys/sem.h>
|
||||
#include <string.h> /* memset */
|
||||
|
||||
#ifndef SA_RESTART
|
||||
#define SA_RESTART 0
|
||||
@@ -55,16 +53,16 @@
|
||||
|
||||
typedef struct {
|
||||
jmp_buf regs;
|
||||
unsigned32 isr_level;
|
||||
sigset_t isr_level;
|
||||
} Context_Control_overlay;
|
||||
|
||||
void _CPU_Signal_initialize(void);
|
||||
void _CPU_Stray_signal(int);
|
||||
void _CPU_ISR_Handler(int);
|
||||
|
||||
static sigset_t _CPU_Signal_mask;
|
||||
static Context_Control_overlay _CPU_Context_Default_with_ISRs_enabled;
|
||||
static Context_Control_overlay _CPU_Context_Default_with_ISRs_disabled;
|
||||
sigset_t _CPU_Signal_mask;
|
||||
Context_Control _CPU_Context_Default_with_ISRs_enabled;
|
||||
Context_Control _CPU_Context_Default_with_ISRs_disabled;
|
||||
|
||||
/*
|
||||
* Which cpu are we? Used by libcpu and libbsp.
|
||||
@@ -92,7 +90,7 @@ void _CPU_ISR_From_CPU_Init()
|
||||
|
||||
/*
|
||||
* Block all the signals except SIGTRAP for the debugger
|
||||
* and fatal error signals.
|
||||
* and SIGABRT for fatal errors.
|
||||
*/
|
||||
|
||||
(void) sigfillset(&_CPU_Signal_mask);
|
||||
@@ -100,9 +98,6 @@ void _CPU_ISR_From_CPU_Init()
|
||||
(void) sigdelset(&_CPU_Signal_mask, SIGABRT);
|
||||
(void) sigdelset(&_CPU_Signal_mask, SIGIOT);
|
||||
(void) sigdelset(&_CPU_Signal_mask, SIGCONT);
|
||||
(void) sigdelset(&_CPU_Signal_mask, SIGSEGV);
|
||||
(void) sigdelset(&_CPU_Signal_mask, SIGBUS);
|
||||
(void) sigdelset(&_CPU_Signal_mask, SIGFPE);
|
||||
|
||||
_CPU_ISR_Enable(1);
|
||||
|
||||
@@ -123,16 +118,20 @@ void _CPU_Signal_initialize( void )
|
||||
{
|
||||
struct sigaction act;
|
||||
sigset_t mask;
|
||||
|
||||
|
||||
/* mark them all active except for TraceTrap and Abort */
|
||||
|
||||
mask = _CPU_Signal_mask;
|
||||
|
||||
sigfillset(&mask);
|
||||
sigdelset(&mask, SIGTRAP);
|
||||
sigdelset(&mask, SIGABRT);
|
||||
sigdelset(&mask, SIGIOT);
|
||||
sigdelset(&mask, SIGCONT);
|
||||
sigprocmask(SIG_UNBLOCK, &mask, 0);
|
||||
|
||||
|
||||
act.sa_handler = _CPU_ISR_Handler;
|
||||
act.sa_mask = mask;
|
||||
act.sa_flags = SA_RESTART;
|
||||
|
||||
|
||||
sigaction(SIGHUP, &act, 0);
|
||||
sigaction(SIGINT, &act, 0);
|
||||
sigaction(SIGQUIT, &act, 0);
|
||||
@@ -166,6 +165,7 @@ void _CPU_Signal_initialize( void )
|
||||
#ifdef SIGLOST
|
||||
sigaction(SIGLOST, &act, 0);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/*PAGE
|
||||
@@ -180,6 +180,8 @@ void _CPU_Context_From_CPU_Init()
|
||||
/*
|
||||
* HACK - set the _SYSTEM_ID to 0x20c so that setjmp/longjmp
|
||||
* will handle the full 32 floating point registers.
|
||||
*
|
||||
* NOTE: Is this a bug in HPUX9?
|
||||
*/
|
||||
|
||||
{
|
||||
@@ -193,28 +195,16 @@ void _CPU_Context_From_CPU_Init()
|
||||
* get default values to use in _CPU_Context_Initialize()
|
||||
*/
|
||||
|
||||
|
||||
(void) memset(
|
||||
&_CPU_Context_Default_with_ISRs_enabled,
|
||||
0,
|
||||
sizeof(Context_Control)
|
||||
);
|
||||
(void) memset(
|
||||
&_CPU_Context_Default_with_ISRs_disabled,
|
||||
0,
|
||||
sizeof(Context_Control)
|
||||
);
|
||||
|
||||
_CPU_ISR_Set_level( 0 );
|
||||
_CPU_Context_switch(
|
||||
(Context_Control *) &_CPU_Context_Default_with_ISRs_enabled,
|
||||
(Context_Control *) &_CPU_Context_Default_with_ISRs_enabled
|
||||
&_CPU_Context_Default_with_ISRs_enabled,
|
||||
&_CPU_Context_Default_with_ISRs_enabled
|
||||
);
|
||||
|
||||
|
||||
_CPU_ISR_Set_level( 1 );
|
||||
_CPU_Context_switch(
|
||||
(Context_Control *) &_CPU_Context_Default_with_ISRs_disabled,
|
||||
(Context_Control *) &_CPU_Context_Default_with_ISRs_disabled
|
||||
&_CPU_Context_Default_with_ISRs_disabled,
|
||||
&_CPU_Context_Default_with_ISRs_disabled
|
||||
);
|
||||
}
|
||||
|
||||
@@ -223,16 +213,21 @@ void _CPU_Context_From_CPU_Init()
|
||||
* _CPU_ISR_Get_level
|
||||
*/
|
||||
|
||||
sigset_t GET_old_mask;
|
||||
|
||||
unsigned32 _CPU_ISR_Get_level( void )
|
||||
{
|
||||
sigset_t old_mask;
|
||||
/* sigset_t old_mask; */
|
||||
unsigned32 old_level;
|
||||
|
||||
sigprocmask(SIG_BLOCK, 0, &old_mask);
|
||||
sigprocmask(0, 0, &GET_old_mask);
|
||||
|
||||
if (memcmp((void *)&posix_empty_mask, (void *)&old_mask, sizeof(sigset_t)))
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
if (memcmp((void *)&posix_empty_mask, (void *)&GET_old_mask, sizeof(sigset_t)))
|
||||
old_level = 1;
|
||||
else
|
||||
old_level = 0;
|
||||
|
||||
return old_level;
|
||||
}
|
||||
|
||||
/* _CPU_Initialize
|
||||
@@ -344,7 +339,7 @@ void _CPU_Install_interrupt_stack( void )
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* _CPU_Thread_Idle_body
|
||||
* _CPU_Internal_threads_Idle_thread_body
|
||||
*
|
||||
* Stop until we get a signal which is the logically the same thing
|
||||
* entering low-power or sleep mode on a real processor and waiting for
|
||||
@@ -352,17 +347,10 @@ void _CPU_Install_interrupt_stack( void )
|
||||
* CPU cycles which is again similar to low power mode.
|
||||
*/
|
||||
|
||||
void _CPU_Thread_Idle_body( void )
|
||||
void _CPU_Internal_threads_Idle_thread_body( void )
|
||||
{
|
||||
while (1) {
|
||||
#ifdef RTEMS_DEBUG
|
||||
/* interrupts had better be enabled at this point! */
|
||||
if (_CPU_ISR_Get_level() != 0)
|
||||
abort();
|
||||
#endif
|
||||
while (1)
|
||||
pause();
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/*PAGE
|
||||
@@ -379,6 +367,7 @@ void _CPU_Context_Initialize(
|
||||
boolean _is_fp
|
||||
)
|
||||
{
|
||||
void *source;
|
||||
unsigned32 *addr;
|
||||
unsigned32 jmp_addr;
|
||||
unsigned32 _stack_low; /* lowest "stack aligned" address */
|
||||
@@ -393,28 +382,25 @@ void _CPU_Context_Initialize(
|
||||
* grow up, we build the stack based on the _stack_low address.
|
||||
*/
|
||||
|
||||
_stack_low = (unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT - 1;
|
||||
_stack_low = ((unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT);
|
||||
_stack_low &= ~(CPU_STACK_ALIGNMENT - 1);
|
||||
|
||||
_stack_high = (unsigned32)(_stack_base) + _size;
|
||||
_stack_high = ((unsigned32)(_stack_base) + _size);
|
||||
_stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
|
||||
|
||||
if (_stack_high > _stack_low)
|
||||
_the_size = _stack_high - _stack_low;
|
||||
else
|
||||
_the_size = _stack_low - _stack_high;
|
||||
_the_size = _size & ~(CPU_STACK_ALIGNMENT - 1);
|
||||
|
||||
/*
|
||||
* Slam our jmp_buf template into the context we are creating
|
||||
*/
|
||||
|
||||
if ( _new_level == 0 )
|
||||
*_the_context = *(Context_Control *)
|
||||
&_CPU_Context_Default_with_ISRs_enabled;
|
||||
source = &_CPU_Context_Default_with_ISRs_enabled;
|
||||
else
|
||||
*_the_context = *(Context_Control *)
|
||||
&_CPU_Context_Default_with_ISRs_disabled;
|
||||
source = &_CPU_Context_Default_with_ISRs_disabled;
|
||||
|
||||
memcpy(_the_context, source, sizeof(Context_Control) ); /* sizeof(jmp_buf)); */
|
||||
|
||||
addr = (unsigned32 *)_the_context;
|
||||
|
||||
#if defined(hppa1_1)
|
||||
@@ -425,12 +411,13 @@ void _CPU_Context_Initialize(
|
||||
* See if we are using shared libraries by checking
|
||||
* bit 30 in 24 off of newp. If bit 30 is set then
|
||||
* we are using shared libraries and the jump address
|
||||
* points to the pointer, so we put that into rp instead.
|
||||
* is at what 24 off of newp points to so shove that
|
||||
* into 24 off of newp instead.
|
||||
*/
|
||||
|
||||
if (jmp_addr & 0x40000000) {
|
||||
jmp_addr &= 0xfffffffc;
|
||||
*(addr + RP_OFF) = *(unsigned32 *)jmp_addr;
|
||||
*(addr + RP_OFF) = (unsigned32)*(unsigned32 *)jmp_addr;
|
||||
}
|
||||
#elif defined(sparc)
|
||||
|
||||
@@ -487,7 +474,7 @@ void _CPU_Context_restore(
|
||||
{
|
||||
Context_Control_overlay *nextp = (Context_Control_overlay *)next;
|
||||
|
||||
_CPU_ISR_Enable(nextp->isr_level);
|
||||
sigprocmask( SIG_SETMASK, &nextp->isr_level, 0 );
|
||||
longjmp( nextp->regs, 0 );
|
||||
}
|
||||
|
||||
@@ -496,11 +483,6 @@ void _CPU_Context_restore(
|
||||
* _CPU_Context_switch
|
||||
*/
|
||||
|
||||
static void do_jump(
|
||||
Context_Control_overlay *currentp,
|
||||
Context_Control_overlay *nextp
|
||||
);
|
||||
|
||||
void _CPU_Context_switch(
|
||||
Context_Control *current,
|
||||
Context_Control *next
|
||||
@@ -508,50 +490,33 @@ void _CPU_Context_switch(
|
||||
{
|
||||
Context_Control_overlay *currentp = (Context_Control_overlay *)current;
|
||||
Context_Control_overlay *nextp = (Context_Control_overlay *)next;
|
||||
#if 0
|
||||
int status;
|
||||
#endif
|
||||
|
||||
currentp->isr_level = _CPU_ISR_Disable_support();
|
||||
|
||||
do_jump( currentp, nextp );
|
||||
|
||||
#if 0
|
||||
if (sigsetjmp(currentp->regs, 1) == 0) { /* Save the current context */
|
||||
siglongjmp(nextp->regs, 0); /* Switch to the new context */
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_CORE,
|
||||
TRUE,
|
||||
status
|
||||
);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef RTEMS_DEBUG
|
||||
if (_CPU_ISR_Get_level() == 0)
|
||||
abort();
|
||||
#endif
|
||||
|
||||
_CPU_ISR_Enable(currentp->isr_level);
|
||||
}
|
||||
|
||||
static void do_jump(
|
||||
Context_Control_overlay *currentp,
|
||||
Context_Control_overlay *nextp
|
||||
)
|
||||
{
|
||||
int status;
|
||||
|
||||
/*
|
||||
* Switch levels in one operation
|
||||
*/
|
||||
|
||||
status = sigprocmask( SIG_SETMASK, &nextp->isr_level, ¤tp->isr_level );
|
||||
if ( status )
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_CORE,
|
||||
TRUE,
|
||||
status
|
||||
);
|
||||
|
||||
if (setjmp(currentp->regs) == 0) { /* Save the current context */
|
||||
longjmp(nextp->regs, 0); /* Switch to the new context */
|
||||
_Internal_error_Occurred(
|
||||
if ( status )
|
||||
_Internal_error_Occurred(
|
||||
INTERNAL_ERROR_CORE,
|
||||
TRUE,
|
||||
status
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* _CPU_Save_float_context
|
||||
@@ -657,7 +622,6 @@ void _CPU_ISR_Handler(int vector)
|
||||
|
||||
if (_Thread_Dispatch_disable_level == 0 &&
|
||||
(_Context_Switch_necessary || _ISR_Signals_to_thread_executing)) {
|
||||
_ISR_Signals_to_thread_executing = FALSE;
|
||||
_CPU_ISR_Enable(0);
|
||||
_Thread_Dispatch();
|
||||
}
|
||||
@@ -685,31 +649,17 @@ void _CPU_Stray_signal(int sig_num)
|
||||
|
||||
default:
|
||||
{
|
||||
/*
|
||||
* We avoid using the stdio section of the library.
|
||||
* The following is generally safe
|
||||
*/
|
||||
/*
|
||||
* We avoid using the stdio section of the library.
|
||||
* The following is generally safe.
|
||||
*/
|
||||
|
||||
int digit;
|
||||
int number = sig_num;
|
||||
int len = 0;
|
||||
|
||||
digit = number / 100;
|
||||
number %= 100;
|
||||
if (digit) buffer[len++] = '0' + digit;
|
||||
|
||||
digit = number / 10;
|
||||
number %= 10;
|
||||
if (digit || len) buffer[len++] = '0' + digit;
|
||||
|
||||
digit = number;
|
||||
buffer[len++] = '0' + digit;
|
||||
buffer[ 0 ] = (sig_num >> 4) + 0x30;
|
||||
buffer[ 1 ] = (sig_num & 0xf) + 0x30;
|
||||
buffer[ 2 ] = '\n';
|
||||
|
||||
buffer[ len++ ] = '\n';
|
||||
|
||||
write( 2, "Stray signal ", 13 );
|
||||
write( 2, buffer, len );
|
||||
|
||||
write( 2, "Stray signal 0x", 12 );
|
||||
write( 2, buffer, 3 );
|
||||
}
|
||||
}
|
||||
|
||||
@@ -731,8 +681,7 @@ void _CPU_Stray_signal(int sig_num)
|
||||
case SIGBUS:
|
||||
case SIGSEGV:
|
||||
case SIGTERM:
|
||||
case SIGIOT:
|
||||
_CPU_Fatal_error(0x100 + sig_num);
|
||||
_CPU_Fatal_error(0x100 + sig_num);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -791,12 +740,13 @@ void _CPU_Stop_clock( void )
|
||||
* vector.
|
||||
*/
|
||||
|
||||
(void) memset(&act, 0, sizeof(act));
|
||||
act.sa_handler = SIG_IGN;
|
||||
|
||||
|
||||
sigaction(SIGALRM, &act, 0);
|
||||
|
||||
(void) memset(&new, 0, sizeof(new));
|
||||
new.it_value.tv_sec = 0;
|
||||
new.it_value.tv_usec = 0;
|
||||
|
||||
setitimer(ITIMER_REAL, &new, 0);
|
||||
}
|
||||
|
||||
|
||||
@@ -221,9 +221,9 @@ extern "C" {
|
||||
/*
|
||||
* Does this port provide a CPU dependent IDLE task implementation?
|
||||
*
|
||||
* If TRUE, then the routine _CPU_Thread_Idle_body
|
||||
* If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
|
||||
* must be provided and is the default IDLE thread body instead of
|
||||
* _CPU_Thread_Idle_body.
|
||||
* _Internal_threads_Idle_thread_body.
|
||||
*
|
||||
* If FALSE, then use the generic IDLE thread body if the BSP does
|
||||
* not provide one.
|
||||
@@ -436,27 +436,14 @@ extern "C" {
|
||||
/*
|
||||
* This is really just the area for the following fields.
|
||||
*
|
||||
* jmp_buf regs;
|
||||
* unsigned32 isr_level;
|
||||
* jmp_buf regs;
|
||||
* sigset_t isr_level;
|
||||
*
|
||||
* Doing it this way avoids conflicts between the native stuff and the
|
||||
* RTEMS stuff.
|
||||
*
|
||||
* NOTE:
|
||||
* hpux9 setjmp is optimized for the case where the setjmp buffer
|
||||
* is 8 byte aligned. In a RISC world, this seems likely to enable
|
||||
* 8 byte copies, especially for the float registers.
|
||||
* So we always align them on 8 byte boundaries.
|
||||
*/
|
||||
|
||||
#ifdef __GNUC__
|
||||
#define CONTEXT_STRUCTURE_ALIGNMENT __attribute__ ((aligned (8)))
|
||||
#else
|
||||
#define CONTEXT_STRUCTURE_ALIGNMENT
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
char Area[ CPU_CONTEXT_SIZE_IN_BYTES ] CONTEXT_STRUCTURE_ALIGNMENT;
|
||||
char Area[ CPU_CONTEXT_SIZE_IN_BYTES ];
|
||||
} Context_Control;
|
||||
|
||||
typedef struct {
|
||||
@@ -468,7 +455,13 @@ typedef struct {
|
||||
|
||||
/*
|
||||
* The following table contains the information required to configure
|
||||
* the UNIX Simulator specific parameters.
|
||||
* the XXX processor specific parameters.
|
||||
*
|
||||
* NOTE: The interrupt_stack_size field is required if
|
||||
* CPU_ALLOCATE_INTERRUPT_STACK is defined as TRUE.
|
||||
*
|
||||
* The pretasking_hook, predriver_hook, and postdriver_hook,
|
||||
* and the do_zero_of_workspace fields are required on ALL CPUs.
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
@@ -478,10 +471,7 @@ typedef struct {
|
||||
void (*idle_task)( void );
|
||||
boolean do_zero_of_workspace;
|
||||
unsigned32 interrupt_stack_size;
|
||||
unsigned32 extra_mpci_receive_server_stack;
|
||||
void * (*stack_allocate_hook)( unsigned32 );
|
||||
void (*stack_free_hook)( void* );
|
||||
/* end of required fields */
|
||||
unsigned32 extra_system_initialization_stack;
|
||||
} rtems_cpu_table;
|
||||
|
||||
/*
|
||||
@@ -491,7 +481,7 @@ typedef struct {
|
||||
* _CPU_Context_Initialize.
|
||||
*/
|
||||
|
||||
SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
|
||||
EXTERN Context_Control_fp _CPU_Null_fp_context;
|
||||
|
||||
/*
|
||||
* On some CPUs, RTEMS supports a software managed interrupt stack.
|
||||
@@ -506,8 +496,8 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
|
||||
* CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
|
||||
*/
|
||||
|
||||
SCORE_EXTERN void *_CPU_Interrupt_stack_low;
|
||||
SCORE_EXTERN void *_CPU_Interrupt_stack_high;
|
||||
EXTERN void *_CPU_Interrupt_stack_low;
|
||||
EXTERN void *_CPU_Interrupt_stack_high;
|
||||
|
||||
/*
|
||||
* With some compilation systems, it is difficult if not impossible to
|
||||
@@ -519,7 +509,7 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high;
|
||||
* sequence (if a dispatch is necessary).
|
||||
*/
|
||||
|
||||
SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
|
||||
EXTERN void (*_CPU_Thread_dispatch_pointer)();
|
||||
|
||||
/*
|
||||
* Nothing prevents the porter from declaring more CPU specific variables.
|
||||
@@ -552,11 +542,11 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
|
||||
|
||||
/*
|
||||
* Amount of extra stack (above minimum stack size) required by
|
||||
* MPCI receive server thread. Remember that in a multiprocessor
|
||||
* system this thread must exist and be able to process all directives.
|
||||
* system initialization thread. Remember that in a multiprocessor
|
||||
* system the system intialization thread becomes the MP server thread.
|
||||
*/
|
||||
|
||||
#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
|
||||
#define CPU_SYSTEM_INITIALIZATION_THREAD_EXTRA_STACK 0
|
||||
|
||||
/*
|
||||
* This defines the number of entries in the ISR_Vector_table managed
|
||||
@@ -883,7 +873,7 @@ void _CPU_ISR_install_vector(
|
||||
void _CPU_Install_interrupt_stack( void );
|
||||
|
||||
/*
|
||||
* _CPU_Thread_Idle_body
|
||||
* _CPU_Internal_threads_Idle_thread_body
|
||||
*
|
||||
* This routine is the CPU dependent IDLE thread body.
|
||||
*
|
||||
@@ -891,7 +881,7 @@ void _CPU_Install_interrupt_stack( void );
|
||||
* is TRUE.
|
||||
*/
|
||||
|
||||
void _CPU_Thread_Idle_body( void );
|
||||
void _CPU_Internal_threads_Idle_thread_body( void );
|
||||
|
||||
/*
|
||||
* _CPU_Context_switch
|
||||
|
||||
@@ -21,6 +21,82 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* _Addresses_Add_offset
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function is used to add an offset to a base address.
|
||||
* It returns the resulting address. This address is typically
|
||||
* converted to an access type before being used further.
|
||||
*/
|
||||
|
||||
STATIC INLINE void *_Addresses_Add_offset (
|
||||
void *base,
|
||||
unsigned32 offset
|
||||
);
|
||||
|
||||
/*
|
||||
* _Addresses_Subtract_offset
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function is used to subtract an offset from a base
|
||||
* address. It returns the resulting address. This address is
|
||||
* typically converted to an access type before being used further.
|
||||
*/
|
||||
|
||||
STATIC INLINE void *_Addresses_Subtract_offset(
|
||||
void *base,
|
||||
unsigned32 offset
|
||||
);
|
||||
|
||||
/*
|
||||
* _Addresses_Subtract
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function is used to subtract two addresses. It returns the
|
||||
* resulting offset.
|
||||
*/
|
||||
|
||||
STATIC INLINE unsigned32 _Addresses_Subtract (
|
||||
void *left,
|
||||
void *right
|
||||
);
|
||||
|
||||
/*
|
||||
* _Addresses_Is_aligned
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the given address is correctly
|
||||
* aligned for this processor and FALSE otherwise. Proper alignment
|
||||
* is based on correctness and efficiency.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Addresses_Is_aligned (
|
||||
void *address
|
||||
);
|
||||
|
||||
/*
|
||||
* _Addresses_Is_in_range
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the given address is within the
|
||||
* memory range specified and FALSE otherwise. base is the address
|
||||
* of the first byte in the memory range and limit is the address
|
||||
* of the last byte in the memory range. The base address is
|
||||
* assumed to be lower than the limit address.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Addresses_Is_in_range (
|
||||
void *address,
|
||||
void *base,
|
||||
void *limit
|
||||
);
|
||||
|
||||
#include <rtems/score/address.inl>
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -18,7 +18,6 @@
|
||||
#define __API_EXTENSIONS_h
|
||||
|
||||
#include <rtems/score/chain.h>
|
||||
#include <rtems/score/thread.h>
|
||||
|
||||
/*
|
||||
* The control structure which defines the points at which an API
|
||||
@@ -27,23 +26,18 @@
|
||||
|
||||
typedef void (*API_extensions_Predriver_hook)(void);
|
||||
typedef void (*API_extensions_Postdriver_hook)(void);
|
||||
typedef void (*API_extensions_Postswitch_hook)(
|
||||
Thread_Control *
|
||||
);
|
||||
|
||||
|
||||
typedef struct {
|
||||
Chain_Node Node;
|
||||
API_extensions_Predriver_hook predriver_hook;
|
||||
API_extensions_Postdriver_hook postdriver_hook;
|
||||
API_extensions_Postswitch_hook postswitch_hook;
|
||||
Chain_Node Node;
|
||||
API_extensions_Predriver_hook predriver_hook;
|
||||
API_extensions_Postdriver_hook postdriver_hook;
|
||||
} API_extensions_Control;
|
||||
|
||||
/*
|
||||
* This is the list of API extensions to the system initialization.
|
||||
*/
|
||||
|
||||
SCORE_EXTERN Chain_Control _API_extensions_List;
|
||||
EXTERN Chain_Control _API_extensions_List;
|
||||
|
||||
/*
|
||||
* _API_extensions_Initialization
|
||||
@@ -88,15 +82,5 @@ void _API_extensions_Run_predriver( void );
|
||||
|
||||
void _API_extensions_Run_postdriver( void );
|
||||
|
||||
/*
|
||||
* _API_extensions_Run_postswitch
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* XXX
|
||||
*/
|
||||
|
||||
void _API_extensions_Run_postswitch( void );
|
||||
|
||||
#endif
|
||||
/* end of include file */
|
||||
|
||||
@@ -40,8 +40,8 @@ extern "C" {
|
||||
|
||||
#if ( CPU_USE_GENERIC_BITFIELD_DATA == TRUE )
|
||||
|
||||
#ifndef SCORE_INIT
|
||||
extern const unsigned char __log2table[256];
|
||||
#ifndef INIT
|
||||
extern const unsigned char __log2table[256];
|
||||
#else
|
||||
const unsigned char __log2table[256] = {
|
||||
7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4,
|
||||
|
||||
@@ -84,14 +84,47 @@ void _Chain_Initialize(
|
||||
);
|
||||
|
||||
/*
|
||||
* _Chain_Get_first_unprotected
|
||||
* _Chain_Initialize_empty
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine initializes the specified chain to contain zero nodes.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef USE_INLINES
|
||||
Chain_Node *_Chain_Get_first_unprotected(
|
||||
|
||||
STATIC INLINE void _Chain_Initialize_empty(
|
||||
Chain_Control *the_chain
|
||||
);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* _Chain_Are_nodes_equal
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if LEFT and RIGHT are equal,
|
||||
* and FALSE otherwise.
|
||||
*
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Chain_Are_nodes_equal(
|
||||
Chain_Node *left,
|
||||
Chain_Node *right
|
||||
);
|
||||
|
||||
/*
|
||||
* _Chain_Extract_unprotected
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine extracts the_node from the chain on which it resides.
|
||||
* It does NOT disable interrupts to insure the atomicity of the
|
||||
* extract operation.
|
||||
*
|
||||
*/
|
||||
|
||||
STATIC INLINE void _Chain_Extract_unprotected(
|
||||
Chain_Node *the_node
|
||||
);
|
||||
|
||||
/*
|
||||
* _Chain_Extract
|
||||
@@ -108,6 +141,22 @@ void _Chain_Extract(
|
||||
Chain_Node *the_node
|
||||
);
|
||||
|
||||
/*
|
||||
* _Chain_Get_unprotected
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function removes the first node from the_chain and returns
|
||||
* a pointer to that node. If the_chain is empty, then NULL is returned.
|
||||
* It does NOT disable interrupts to insure the atomicity of the
|
||||
* get operation.
|
||||
*
|
||||
*/
|
||||
|
||||
STATIC INLINE Chain_Node *_Chain_Get_unprotected(
|
||||
Chain_Control *the_chain
|
||||
);
|
||||
|
||||
/*
|
||||
* _Chain_Get
|
||||
*
|
||||
@@ -124,6 +173,37 @@ Chain_Node *_Chain_Get(
|
||||
Chain_Control *the_chain
|
||||
);
|
||||
|
||||
/*
|
||||
* _Chain_Get_first_unprotected
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function removes the first node from the_chain and returns
|
||||
* a pointer to that node. It does NOT disable interrupts to insure
|
||||
* the atomicity of the get operation.
|
||||
*
|
||||
*/
|
||||
|
||||
STATIC INLINE Chain_Node *_Chain_Get_first_unprotected(
|
||||
Chain_Control *the_chain
|
||||
);
|
||||
|
||||
/*
|
||||
* _Chain_Insert_unprotected
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine inserts the_node on a chain immediately following
|
||||
* after_node. It does NOT disable interrupts to insure the atomicity
|
||||
* of the extract operation.
|
||||
*
|
||||
*/
|
||||
|
||||
STATIC INLINE void _Chain_Insert_unprotected(
|
||||
Chain_Node *after_node,
|
||||
Chain_Node *the_node
|
||||
);
|
||||
|
||||
/*
|
||||
* _Chain_Insert
|
||||
*
|
||||
@@ -140,6 +220,22 @@ void _Chain_Insert(
|
||||
Chain_Node *the_node
|
||||
);
|
||||
|
||||
/*
|
||||
* _Chain_Append_unprotected
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine appends the_node onto the end of the_chain.
|
||||
* It does NOT disable interrupts to insure the atomicity of the
|
||||
* append operation.
|
||||
*
|
||||
*/
|
||||
|
||||
STATIC INLINE void _Chain_Append_unprotected(
|
||||
Chain_Control *the_chain,
|
||||
Chain_Node *the_node
|
||||
);
|
||||
|
||||
/*
|
||||
* _Chain_Append
|
||||
*
|
||||
@@ -156,9 +252,177 @@ void _Chain_Append(
|
||||
Chain_Node *the_node
|
||||
);
|
||||
|
||||
#ifndef __RTEMS_APPLICATION__
|
||||
/*
|
||||
* _Chain_Prepend_unprotected
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine prepends the_node onto the front of the_chain.
|
||||
* It does NOT disable interrupts to insure the atomicity of the
|
||||
* prepend operation.
|
||||
*
|
||||
*/
|
||||
|
||||
STATIC INLINE void _Chain_Prepend_unprotected(
|
||||
Chain_Control *the_chain,
|
||||
Chain_Node *the_node
|
||||
);
|
||||
|
||||
/*
|
||||
* _Chain_Prepend
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine prepends the_node onto the front of the_chain.
|
||||
* It disables interrupts to insure the atomicity of the
|
||||
* prepend operation.
|
||||
*
|
||||
*/
|
||||
|
||||
STATIC INLINE void _Chain_Prepend(
|
||||
Chain_Control *the_chain,
|
||||
Chain_Node *the_node
|
||||
);
|
||||
|
||||
/*
|
||||
* _Chain_Head
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns a pointer to the first node on the chain.
|
||||
*
|
||||
*/
|
||||
|
||||
STATIC INLINE Chain_Node *_Chain_Head(
|
||||
Chain_Control *the_chain
|
||||
);
|
||||
|
||||
/*
|
||||
* _Chain_Tail
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns a pointer to the last node on the chain.
|
||||
*
|
||||
*/
|
||||
|
||||
STATIC INLINE Chain_Node *_Chain_Tail(
|
||||
Chain_Control *the_chain
|
||||
);
|
||||
|
||||
/*
|
||||
* _Chain_Is_head
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_node is the head of the_chain and
|
||||
* FALSE otherwise.
|
||||
*
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Chain_Is_head(
|
||||
Chain_Control *the_chain,
|
||||
Chain_Node *the_node
|
||||
);
|
||||
|
||||
/*
|
||||
* _Chain_Is_tail
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_node is the tail of the_chain and
|
||||
* FALSE otherwise.
|
||||
*
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Chain_Is_tail(
|
||||
Chain_Control *the_chain,
|
||||
Chain_Node *the_node
|
||||
);
|
||||
|
||||
/*
|
||||
* _Chain_Is_first
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_node is the first node on a chain and
|
||||
* FALSE otherwise.
|
||||
*
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Chain_Is_first(
|
||||
Chain_Node *the_node
|
||||
);
|
||||
|
||||
/*
|
||||
* _Chain_Is_last
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_node is the last node on a chain and
|
||||
* FALSE otherwise.
|
||||
*
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Chain_Is_last(
|
||||
Chain_Node *the_node
|
||||
);
|
||||
|
||||
/*
|
||||
* _Chain_Is_empty
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if there a no nodes on the_chain and
|
||||
* FALSE otherwise.
|
||||
*
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Chain_Is_empty(
|
||||
Chain_Control *the_chain
|
||||
);
|
||||
|
||||
/*
|
||||
* _Chain_Has_only_one_node
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if there is only one node on the_chain and
|
||||
* FALSE otherwise.
|
||||
*
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Chain_Has_only_one_node(
|
||||
Chain_Control *the_chain
|
||||
);
|
||||
|
||||
/*
|
||||
* _Chain_Is_null
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_chain is NULL and FALSE otherwise.
|
||||
*
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Chain_Is_null(
|
||||
Chain_Control *the_chain
|
||||
);
|
||||
|
||||
/*
|
||||
* _Chain_Is_null_node
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_node is NULL and FALSE otherwise.
|
||||
*
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Chain_Is_null_node(
|
||||
Chain_Node *the_node
|
||||
);
|
||||
|
||||
#include <rtems/score/chain.inl>
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -35,7 +35,7 @@ extern "C" {
|
||||
* currently executing thread and given to the heir thread.
|
||||
*/
|
||||
|
||||
SCORE_EXTERN volatile boolean _Context_Switch_necessary;
|
||||
EXTERN boolean _Context_Switch_necessary;
|
||||
|
||||
/*
|
||||
* _Context_Initialize
|
||||
|
||||
@@ -21,7 +21,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef SCORE_INIT
|
||||
#ifdef INIT
|
||||
|
||||
const char _Copyright_Notice[] =
|
||||
"COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.\n\
|
||||
|
||||
@@ -195,6 +195,41 @@ unsigned32 _CORE_message_queue_Flush_support(
|
||||
CORE_message_queue_Control *the_message_queue
|
||||
);
|
||||
|
||||
/*
|
||||
* _CORE_message_queue_send
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine sends a message to the end of the specified message queue.
|
||||
*
|
||||
*/
|
||||
|
||||
STATIC INLINE CORE_message_queue_Status _CORE_message_queue_Send(
|
||||
CORE_message_queue_Control *the_message_queue,
|
||||
void *buffer,
|
||||
unsigned32 size,
|
||||
Objects_Id id,
|
||||
CORE_message_queue_API_mp_support_callout api_message_queue_mp_support
|
||||
);
|
||||
|
||||
/*
|
||||
*
|
||||
* _CORE_message_queue_Urgent
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine sends a message to the front of the specified message queue.
|
||||
*
|
||||
*/
|
||||
|
||||
STATIC INLINE CORE_message_queue_Status _CORE_message_queue_Urgent(
|
||||
CORE_message_queue_Control *the_message_queue,
|
||||
void *buffer,
|
||||
unsigned32 size,
|
||||
Objects_Id id,
|
||||
CORE_message_queue_API_mp_support_callout api_message_queue_mp_support
|
||||
);
|
||||
|
||||
/*
|
||||
*
|
||||
* _CORE_message_queue_Broadcast
|
||||
@@ -261,9 +296,144 @@ void _CORE_message_queue_Seize(
|
||||
Watchdog_Interval timeout
|
||||
);
|
||||
|
||||
#ifndef __RTEMS_APPLICATION__
|
||||
/*
|
||||
* _CORE_message_queue_Allocate_message_buffer
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function allocates a message buffer from the inactive
|
||||
* message buffer chain.
|
||||
*/
|
||||
|
||||
STATIC INLINE CORE_message_queue_Buffer_control *
|
||||
_CORE_message_queue_Allocate_message_buffer (
|
||||
CORE_message_queue_Control *the_message_queue
|
||||
);
|
||||
|
||||
/*
|
||||
* _CORE_message_queue_Free_message_buffer
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine frees a message buffer to the inactive
|
||||
* message buffer chain.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _CORE_message_queue_Free_message_buffer (
|
||||
CORE_message_queue_Control *the_message_queue,
|
||||
CORE_message_queue_Buffer_control *the_message
|
||||
);
|
||||
|
||||
/*
|
||||
* _CORE_message_queue_Copy_buffer
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine copies the contents of the source message buffer
|
||||
* to the destination message buffer.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _CORE_message_queue_Copy_buffer (
|
||||
void *source,
|
||||
void *destination,
|
||||
unsigned32 size
|
||||
);
|
||||
|
||||
/*
|
||||
* _CORE_message_queue_Get_pending_message
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function removes the first message from the_message_queue
|
||||
* and returns a pointer to it.
|
||||
*/
|
||||
|
||||
STATIC INLINE
|
||||
CORE_message_queue_Buffer_control *_CORE_message_queue_Get_pending_message (
|
||||
CORE_message_queue_Control *the_message_queue
|
||||
);
|
||||
|
||||
/*
|
||||
* _CORE_message_queue_Is_priority
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the priority attribute is
|
||||
* enabled in the attribute_set and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _CORE_message_queue_Is_priority(
|
||||
CORE_message_queue_Attributes *the_attribute
|
||||
);
|
||||
|
||||
/*
|
||||
* _CORE_message_queue_Append
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine places the_message at the rear of the outstanding
|
||||
* messages on the_message_queue.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _CORE_message_queue_Append (
|
||||
CORE_message_queue_Control *the_message_queue,
|
||||
CORE_message_queue_Buffer_control *the_message
|
||||
);
|
||||
|
||||
/*
|
||||
* _CORE_message_queue_Prepend
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine places the_message at the rear of the outstanding
|
||||
* messages on the_message_queue.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _CORE_message_queue_Prepend (
|
||||
CORE_message_queue_Control *the_message_queue,
|
||||
CORE_message_queue_Buffer_control *the_message
|
||||
);
|
||||
|
||||
/*
|
||||
* _CORE_message_queue_Is_null
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_message_queue is TRUE and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _CORE_message_queue_Is_null (
|
||||
CORE_message_queue_Control *the_message_queue
|
||||
);
|
||||
|
||||
/*
|
||||
* _CORE_message_queue_Is_notify_enabled
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if notification is enabled on this message
|
||||
* queue and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _CORE_message_queue_Is_notify_enabled (
|
||||
CORE_message_queue_Control *the_message_queue
|
||||
);
|
||||
|
||||
/*
|
||||
* _CORE_message_queue_Set_notify
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine initializes the notification information for the_message_queue.
|
||||
*/
|
||||
|
||||
STATIC INLINE void _CORE_message_queue_Set_notify (
|
||||
CORE_message_queue_Control *the_message_queue,
|
||||
CORE_message_queue_Notify_Handler the_handler,
|
||||
void *the_argument
|
||||
);
|
||||
|
||||
#include <rtems/score/coremsg.inl>
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -158,9 +158,85 @@ void _CORE_mutex_Flush(
|
||||
unsigned32 status
|
||||
);
|
||||
|
||||
#ifndef __RTEMS_APPLICATION__
|
||||
/*
|
||||
* _CORE_mutex_Is_locked
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine returns TRUE if the mutex specified is locked and FALSE
|
||||
* otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _CORE_mutex_Is_locked(
|
||||
CORE_mutex_Control *the_mutex
|
||||
);
|
||||
|
||||
/*
|
||||
* _CORE_mutex_Is_fifo
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine returns TRUE if the mutex's wait discipline is FIFO and FALSE
|
||||
* otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _CORE_mutex_Is_fifo(
|
||||
CORE_mutex_Attributes *the_attribute
|
||||
);
|
||||
|
||||
/*
|
||||
* _CORE_mutex_Is_priority
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine returns TRUE if the mutex's wait discipline is PRIORITY and
|
||||
* FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _CORE_mutex_Is_priority(
|
||||
CORE_mutex_Attributes *the_attribute
|
||||
);
|
||||
|
||||
/*
|
||||
* _CORE_mutex_Is_inherit_priority
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine returns TRUE if the mutex's wait discipline is
|
||||
* INHERIT_PRIORITY and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _CORE_mutex_Is_inherit_priority(
|
||||
CORE_mutex_Attributes *the_attribute
|
||||
);
|
||||
|
||||
/*
|
||||
* _CORE_mutex_Is_priority_ceiling
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine returns TRUE if the mutex's wait discipline is
|
||||
* PRIORITY_CEILING and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _CORE_mutex_Is_priority_ceiling(
|
||||
CORE_mutex_Attributes *the_attribute
|
||||
);
|
||||
|
||||
/*
|
||||
* _CORE_mutex_Is_nesting_allowed
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine returns TRUE if the mutex allows a task to obtain a
|
||||
* semaphore more than once and nest.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _CORE_mutex_Is_nesting_allowed(
|
||||
CORE_mutex_Attributes *the_attribute
|
||||
);
|
||||
|
||||
#include <rtems/score/coremutex.inl>
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -143,9 +143,32 @@ void _CORE_semaphore_Flush(
|
||||
unsigned32 status
|
||||
);
|
||||
|
||||
#ifndef __RTEMS_APPLICATION__
|
||||
/*
|
||||
* _CORE_semaphore_Get_count
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This routine returns the current count associated with the semaphore.
|
||||
*/
|
||||
|
||||
STATIC INLINE unsigned32 _CORE_semaphore_Get_count(
|
||||
CORE_semaphore_Control *the_semaphore
|
||||
);
|
||||
|
||||
/*
|
||||
* _CORE_semaphore_Is_priority
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the priority attribute is
|
||||
* enabled in the attribute_set and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _CORE_semaphore_Is_priority(
|
||||
CORE_semaphore_Attributes *the_attribute
|
||||
);
|
||||
|
||||
#include <rtems/score/coresem.inl>
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -40,7 +40,7 @@ typedef unsigned32 rtems_debug_control;
|
||||
* This variable contains the current debug level.
|
||||
*/
|
||||
|
||||
SCORE_EXTERN rtems_debug_control _Debug_Level;
|
||||
EXTERN rtems_debug_control _Debug_Level;
|
||||
|
||||
/*
|
||||
* _Debug_Manager_initialization
|
||||
|
||||
@@ -214,9 +214,189 @@ void _Heap_Walk(
|
||||
boolean do_dump
|
||||
);
|
||||
|
||||
#ifndef __RTEMS_APPLICATION__
|
||||
/*
|
||||
* _Heap_Head
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns the head of the specified heap.
|
||||
*/
|
||||
|
||||
STATIC INLINE Heap_Block *_Heap_Head (
|
||||
Heap_Control *the_heap
|
||||
);
|
||||
|
||||
/*
|
||||
* _Heap_Tail
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns the tail of the specified heap.
|
||||
*/
|
||||
|
||||
STATIC INLINE Heap_Block *_Heap_Tail (
|
||||
Heap_Control *the_heap
|
||||
);
|
||||
|
||||
/*
|
||||
* _Heap_Previous_block
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns the address of the block which physically
|
||||
* precedes the_block in memory.
|
||||
*/
|
||||
|
||||
STATIC INLINE Heap_Block *_Heap_Previous_block (
|
||||
Heap_Block *the_block
|
||||
);
|
||||
|
||||
/*
|
||||
* _Heap_Next_block
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns the address of the block which physically
|
||||
* follows the_block in memory.
|
||||
*/
|
||||
|
||||
STATIC INLINE Heap_Block *_Heap_Next_block (
|
||||
Heap_Block *the_block
|
||||
);
|
||||
|
||||
/*
|
||||
* _Heap_Block_at
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function calculates and returns a block's location (address)
|
||||
* in the heap based upad a base address and an offset.
|
||||
*/
|
||||
|
||||
STATIC INLINE Heap_Block *_Heap_Block_at(
|
||||
void *base,
|
||||
unsigned32 offset
|
||||
);
|
||||
|
||||
/*PAGE
|
||||
*
|
||||
* _Heap_User_block_at
|
||||
*
|
||||
*/
|
||||
|
||||
STATIC INLINE Heap_Block *_Heap_User_block_at(
|
||||
void *base
|
||||
);
|
||||
|
||||
/*
|
||||
* _Heap_Is_previous_block_free
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the previous block of the_block
|
||||
* is free, and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Heap_Is_previous_block_free (
|
||||
Heap_Block *the_block
|
||||
);
|
||||
|
||||
/*
|
||||
* _Heap_Is_block_free
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the block is free, and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Heap_Is_block_free (
|
||||
Heap_Block *the_block
|
||||
);
|
||||
|
||||
/*
|
||||
* _Heap_Is_block_used
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the block is currently allocated,
|
||||
* and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Heap_Is_block_used (
|
||||
Heap_Block *the_block
|
||||
);
|
||||
|
||||
/*
|
||||
* _Heap_Block_size
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns the size of the_block in bytes.
|
||||
*/
|
||||
|
||||
STATIC INLINE unsigned32 _Heap_Block_size (
|
||||
Heap_Block *the_block
|
||||
);
|
||||
|
||||
/*
|
||||
* _Heap_Start_of_user_area
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns the starting address of the portion of the block
|
||||
* which the user may access.
|
||||
*/
|
||||
|
||||
STATIC INLINE void *_Heap_Start_of_user_area (
|
||||
Heap_Block *the_block
|
||||
);
|
||||
|
||||
/*
|
||||
* _Heap_Is_block_in
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns TRUE if the_block is within the memory area
|
||||
* managed by the_heap, and FALSE otherwise.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Heap_Is_block_in (
|
||||
Heap_Control *the_heap,
|
||||
Heap_Block *the_block
|
||||
);
|
||||
|
||||
|
||||
/*
|
||||
* _Heap_Is_page_size_valid
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function validates a specified heap page size. If the page size
|
||||
* is 0 or if lies outside a page size alignment boundary it is invalid
|
||||
* and FALSE is returned. Otherwise, the page size is valid and TRUE is
|
||||
* returned.
|
||||
*/
|
||||
|
||||
STATIC INLINE boolean _Heap_Is_page_size_valid(
|
||||
unsigned32 page_size
|
||||
);
|
||||
|
||||
/*
|
||||
* _Heap_Build_flag
|
||||
*
|
||||
* DESCRIPTION:
|
||||
*
|
||||
* This function returns the block flag composed of size and in_use_flag.
|
||||
* The flag returned is suitable for use as a back or front flag in a
|
||||
* heap block.
|
||||
*/
|
||||
|
||||
STATIC INLINE unsigned32 _Heap_Build_flag (
|
||||
unsigned32 size,
|
||||
unsigned32 in_use_flag
|
||||
);
|
||||
|
||||
#include <rtems/score/heap.inl>
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -29,8 +29,7 @@ extern "C" {
|
||||
|
||||
typedef enum {
|
||||
INTERNAL_ERROR_CORE,
|
||||
INTERNAL_ERROR_RTEMS_API,
|
||||
INTERNAL_ERROR_POSIX_API
|
||||
INTERNAL_ERROR_RTEMS_API
|
||||
} Internal_errors_Source;
|
||||
|
||||
/*
|
||||
@@ -52,8 +51,7 @@ typedef enum {
|
||||
INTERNAL_ERROR_OUT_OF_PACKETS,
|
||||
INTERNAL_ERROR_OUT_OF_GLOBAL_OBJECTS,
|
||||
INTERNAL_ERROR_OUT_OF_PROXIES,
|
||||
INTERNAL_ERROR_INVALID_GLOBAL_ID,
|
||||
INTERNAL_ERROR_BAD_STACK_HOOK
|
||||
INTERNAL_ERROR_INVALID_GLOBAL_ID
|
||||
} Internal_errors_Core_list;
|
||||
|
||||
/*
|
||||
@@ -70,7 +68,7 @@ typedef struct {
|
||||
* When a fatal error occurs, the error information is stored here.
|
||||
*/
|
||||
|
||||
SCORE_EXTERN Internal_errors_Information Internal_errors_What_happened;
|
||||
EXTERN Internal_errors_Information Internal_errors_What_happened;
|
||||
|
||||
/*
|
||||
* _Internal_error_Occurred
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user