Guest systems in paravirtualization environments run usually in user
mode. Thus it is not possible to directly access the PSR and TBR
registers. Use functions instead of inline assembler to access these
registers if RTEMS_PARAVIRT is defined.
The last optimization missed was incorrect in regards to
PSR write instruction delay must be 3 instructions.
New optimizations:
* align to 32-byte cache line.
* rearrange code into three "blocks" of 4 instructions that
is executed by syscall 2 and 3. This is to optimize for
16/32 byte cache lines.
* use delay-slot instruction in trap table to reduce by one
instruction.
* use the fact that "wr %PSR" implements XOR to reduce by
one instruction.
The exit SPARC system call doesn't have a function entry
point like the others do. This is probably why people use
TA 0x0 instruction directly for shutting down the system.
This commit deletes all RTEMS ChangeLog files. These files have been abandoned
since converting to git version control. The historical data may be recovered
by checking out any commit before this one. Most of the contents of these
ChangeLog files can also be found in the git log.
Two external ChangeLog files, ChangeLog.slac and ChangeLog.zlib, remain.
Script does what is expected and tries to do it as
smartly as possible.
+ remove occurrences of two blank comment lines
next to each other after Id string line removed.
+ remove entire comment blocks which only exited to
contain CVS Ids
+ If the processing left a blank line at the top of
a file, it was removed.
The low level routines can be used in different occasions, it will be
required when accessing PCI.
Note the difference between byteorder.h (inlined functions) and access.S
where the functions will be declared in the library archive librtemscpu.a.
Function names starting with _ are in library and can be referenced by
function pointers.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
PR 1249/build
* configure.ac: Jerry Needell <jerry.needell@unh.edu> reported that the
leon3 was left out of the cache enable logic. Thus the cache
management support code was empty on LEON3 CPUs.
