* Coding style cleanups.
* Use OS reserved trap 0x89 for IRQ Disable
* Use OS reserved trap 0x8A for IRQ Enable
* Add to SPARC CPU supplement documentation
This will result in faster Disable/Enable code since the
system trap handler does not need to decode which function
the user wants. Besides the IRQ disable/enabled can now
be inline which avoids the caller to take into account that
o0-o7+g1-g4 registers are destroyed by trap handler.
It was also possible to reduce the interrupt trap handler by
five instructions due to this.
Previously, bankValidate() could be called (e.g., BSP_flashWrite() -> regionCheckAndErase() -> argcheck() -> bankValidate()) without the probe having happened. When it then invoked BSP_flashCheckId(), unmapped memory could be read, possibly causing a fatal exception.
Save five instructions on underflow handling.
By using an optimized trap entry we can move instructions from
the window underflow function into the trap entry vector. By
setting WIM=0 and using RESTORE it is possible to move the
new WIM register content from the trapped window into the
to-be-restored register window. It is then possible to avoid
the WIM write delay.
By using a optimized trap entry we can move instructions from
the window overflow function into the trap entry vector. By
using the saved locals instead of g1 we don't need to save
that register temporarily. Also spead out non store instructions
inbetween stores to use the write buffer better.
This was flagged by CodeSonar. It should be impossible to get an
incorrect baud number back but ensure this in debug mode. The _Assert()
keeps their scanner from evaluating for divide by 0 past this point.
Make sure also the size is cache aligned since otherwise we may have
some overlap with the next allocation block. A cache invalidate on this
area would be fatal.
Reduce non-IRQ stacks to size zero. All non-IRQ stacks overlap now the
IRQ stack. This is all right since the SVC stack is used only during
startup and here interrupts are disabled. The other exception stacks
lead to a system termination by default, so we can here also use the IRQ
stack since interrupts are disabled on exception entry.
