This adds the set of functions necessary to allow more generic handling
of machine exceptions. This initial patch offers the ability to
manipulate a CPU_Exception_frame and resume execution using that
exception information with or without thread dispatch. These functions
are gated behind the RTEMS_EXCEPTION_EXTENSIONS configuration option.
Using 32bit types like uint32_t for pointers creates issues on 64 bit
architectures like AArch64. Replaced occurrences of these with
uintptr_t, which will work for both 32 and 64 bit architectures. Added
hex_decode_addr function to rtems-debugger.
Mention that resetting the processor usage time of tasks has no impact
on the period status and statistics.
Remove no longer relevant RTEMS_NOT_DEFINED error status.
Update #4528.
The rate monotonic period statistics were affected by
rtems_cpu_usage_reset(). The logic to detect and work around a CPU
usage reset was broken.
The Thread_Contol::cpu_time_used is changed to contain the processor
time used throughout the entire lifetime of the thread. The new member
Thread_Contol::cpu_time_used_at_last_reset is added to contain the
processor time used at the time of the last reset through
rtems_cpu_usage_reset(). This decouples the resets of the CPU usage and
the rate monotonic period statistics.
Update #4528.
The spconfig01 and spmisc01 tests were disabled for all AArch64 BSPs due
to a toolchain issue preventing them from compiling correctly. The
binutils version that contains the fix has been released and integrated
into RSB such that these two tests now build and operate correctly.
Add a stack allocator hook specifically for allocation of IDLE thread stacks.
This allows the user to decide if IDLE thread stacks are statically allocated
or handled by the same custom allocator mechanism as other thread stacks.
Closes#4524.
Do not use a direct thread dispatch in
_Thread_queue_Surrender_priority_ceiling() since it may be used in condition
variables using POSIX mutexes.
Close#4526.
Set the postponed jobs count to zero in rtems_rate_monotonic_cancel() so that
rtems_rate_monotonic_get_status() returns a consistent status for inactive
periods.
Update #4511.
The schedule operation is only called by rtems_task_mode(). It is
called if preempt mode of the executing thread changes from disabled to
enabled. Since the EDF SMP scheduler does not support the disabled
preemption mode, the schedule operation is never called.
The utimbuf structs in fsimfsconfig01 and fsimfsconfig02 were
being passed to utime uninitialized. This did not cause problems until
utime was changed to use utimensat behind the scenes. Now that
utimensat is called, the values of the utimbuf struct are checked, and
EINVAL is set for invalid values. The utimebuf structs in these tests
could contain invalid values since they are uninitialized.
By zero-initializing the utimbuf structs, we ensure that they pass the
checks in utimensat and that errno is set to the expected ENOTSUP.
Context validation for AArch64 was ported from the ARM implementation
without a reinterpretation of the actual requirements. The spcontext01
test just happened to pass because the set of scratch registers in ARM
is a subset of the scratch registers in AArch64.
Replace the boolen return value with the new enum
Thread_queue_Deadlock_status. This improves the code readability.
Improve documentation. Shorten function names.
For uniprocessor configurations, this patch removes dead code in the
_Thread_queue_Surrender() and _Thread_queue_Surrender_priority_ceiling()
functions.
Dead code is removed from _Thread_queue_Surrender_sticky().
This function was unused. It was a relict of the thread queue rework done
during the SMP support development. In an early stage, the extract operation
was called with a NULL thread queue. However, this is no longer the case. The
extract operation is only called if we have a non-NULL thread queue.
ARM's GICv2 is configurable and its attributes vary between
implementations including omission of specific interrupts. This allows
BSPs to accomodate those varying implementations with customized
attribute sets.
The order in which step checks for 1 and 2 are not rigidly defined and
may actually occur in either order depending on how the threads execute.
This waits for the job to complete to enforce the existing ordering.
This adds the SMP function that supports spinup of additional CPU cores
using the ARM standard PSCI inteface. This interface is provided by QEMU
as well as ARM Trusted Firmware running in monitor mode (EL3) on ARMv7 and
AArch64 CPUs. This supports activation va SMC or HVC instructions
depending on BSP configuration.
