This refactors the AArch64 exception handling to remove the mutable code
sections that are generally flagged as a bad idea by code analysis
tools. This also removes any casting between data pointers and function
pointers to avoid the need to use pragmas to disable warnings about such
casting.
This adds support for a the Image header protocol similar to the zImage
protocol that Linux kernels use to describe their expectations of the
system configuration.
The AArch64-specific timer selection mechanism was using the wrong macro
for selecting the timer interrupt and would therefore partially ignore
configurations that selected the use of virtual timers. The virtual
timer will now be used correctly when selected.
The functions lpc24xx_uart_set_register() and
lpc24xx_uart_set_register() were unused if all of the
feature macros LPC24XX_CONFIG_CONSOLE and LPC24XX_CONFIG_UART_[123]
were undefined.
lpc32xx_mlc_write_blocks() had a different prototype in the header
from the implementation. Changed to match the prototype and Doxygen.
LPC32XX_SCRATCH_AREA_SIZE was tested with "ifdef" not "if" which
resulted in it being used as an array size when undefined or
set to 0.
This header file defines multiple empty structures which are
reported as errors by the test spstdc17 using GCC 15. Added an element
named "unused" to each structure. The macro LPC32XX_FILL() was
checked to ensure it handles the modified structure correctly.
Closes#5295.
Removed all uses and implementations of set_vector() function across ERC32,
LEON2, and LEON3 BSPs. Replaced with rtems_interrupt_handler_install() and
rtems_interrupt_entry_install().
- Added ERC32_Clear_and_unmask_interrupt() and LEON_Clear_and_unmask_interrupt()
for unmasking logic previously in set_vector().
- Deleted set_vector() definitions and implementations in each BSP.
- Updated related obj.yml files.
- Replaced set_vector() with rtems_interrupt_catch() in shared/gnatcommon.c.
This BSP supports a custom STM32U5 based board. It uses a similar
structure like the existing STM32H7 BSP and therefore should be well
adaptable to other boards.
Co-authored-by: Christian Mauderer <christian.mauderer@embedded-brains.de>
Include armv7m_cachel1.h in core_cm33.h file to allow access to
cache functions.
Co-authored-by: Christian Mauderer <christian.mauderer@embedded-brains.de>
Files are imported from https://github.com/ARM-software/CMSIS_5 revision
55b19837f5703e418ca37894d5745b1dc05e4c91
Like already checked in RTEMS commit
6b2318acef, the project still don't have a
NOTICE file.
Avoid reading from the pl011 data register unnecessarily. There is no
need to preserve the contents of this register as it is not normal
memory. This unnecessary read causes console spam when running under the
Xen hypervisor when the read FIFO is empty since the read is not
expected.
Before, the console driver needed
`BSP_CONSOLE_USE_INTERRUPTS` to be defined or it
would not build. The intent was to use polled
mode if the macro was equal to zero.
This change makes it so interrupt mode is used if
the macro is defined and polled mode is used if
the macro is not defined.
The old logic would lead to an error when
multiprocessing was enabled and
`LEON3_GPTIMER_BASE` was defined due to
`leon3_timer_core_index` being undefined.
The new logic fixes this and keeps the same
intent:
- If multiprocessing is not enabled, the timer
index is 0
- If multiprocessing is enabled and
`LEON3_GPTIMER_BASE` is defined, the timer
index is twice the CPU boot index
- If multiprocessing is enabled and
`LEON3_GPTIMER_BASE` is not defined, we
fallback to the old logic using the GPTIMER
core index.
Close#5258
The gen5200, gen83xx, and tqm8xx BSP families have multiple variants
which produced the same stray semi-colon warning from GCC 15 for
using LINKER_SYMBOLS() with a semi-colon at the end of the line.
Closes#5277.
This zlib source is a hacked down version just for the decompression
phase for the bootloader used by this family of BSPs. The proper
fix is to redo the hackery with a new version of zlib. But that
is risky so this is just addressing the warnings.
Updates #5276
GCC 14 generates an error for the wrong signature function being
passed in. The underlying type was a void * so adjusting the
signature of the ISR handler was not an option. Added cast.
Closes#5272
Provide missing GCC atomics helpers as part of BSPs where GCC
does not know how to provide it since the CPU's ISA has no
atomic instructions. The implementation provided in
bsps/shared/atomics/__atomic_test_and_set.c should work
on any single core CPU.
The BSPs that need thie function tend to have older cores. This
is the list of BSPs:
arm - csb336, csb337, csb637, edb7312, gumstix, kit637_v6, lpc24xx_ea,
lpc24xx_ncs_ram, lpc24xx_ncs_rom_ext, lpc24xx_ncs_rom_int,
lpc24xx_plx800_ram, lpc24xx_plx800_rom_int, lpc32xx_mzx,
lpc32xx_mzx_stage_1, lpc32xx_mzx_stage_2, lpc32xx_phycore,
rtl22xx, rtl22xx_t, smdk2410
m68k - av5282, mcf5329
mips - jmr3904
moxie - moxiesim
nios2 - nios2_iss
riscv - grv32i, grv32im, niosvc10lp, noel32im, rv32i, rv32im,
sparc - ut699
Applied suggested formatting changes to the following files which
were modified for technical reasons in the previous commit.
bsps/powerpc/gen5200/include/tm27.h
bsps/powerpc/mvme5500/include/tm27.h
bsps/powerpc/psim/include/tm27.h
The gen5200, mvme5500, and psim BSP families had an implementation of
tm27.h which used stub functions with casts as null handlers to fill
in the IRQ structure. The IRQ structure as also missing a field. The
change was to use a set of appropriately signatured stub functions
and correct the structure initialization.
This code likely has produced warnings for a long time but with
GCC 14, these warnings turned into errors.
Closes#5266
This updates the AArch64 Raspberry Pi BSP to use the watchdog to perform
the system reset instead of attempting to use the PSCI reset which isn't
present on the Raspberry Pi platform.
* Cleaned up the uC5282 ISR stuff to make the casts and whatnot more
readable. Also made the offsets relative to the VBR (which is at 0x0
for this BSP) to silence a GCC warning.
* Refactored the default exception handler to map a struct to the stack
instead of taking the address of pc and under-indexing it. The
compiler was not particularly happy about the previous implementation.
