If the RTEMS_INTERRUPT_LOCK_NEEDS_OBJECT define has a non-zero value,
then the interrupt lock operations require an object of type
rtems_interrupt_lock, otherwise no lock object is required.
This indication can be used to avoid the space overhead for lock objects
when they are not needed. In this case, the lock operations will not
use a lock objects parameter.
Update #4957 and #5038.
This adds error reporting for ZynqMP including L1 and L2 cache, on-chip
memory (OCM) error correcting code (ECC), and DDR ECC. OCM ECC supports
fault injection from within RTEMS. DDR ECC technically supports fault
injection as well, but requires that the program injecting faults
operate exclusively outside of DDR. The AArch64 port is not currently
capable of operating exclusively in OCM due to size constraints and
would need to be booted via JTAG or via a non-relocating u-boot to
accomplish this.
When starting multitasking there is a chance an interrupt could be fired
while rsp is still pointing to the ISR stack area if we load rflags
before rsp on "_CPU_Context_restore"
This test was broken by b031cf2b19 since
it expects the macros to evaluate to an empty string for non-SMP builds.
This updates the check for the new content.
Remove ancient SCCS tags from the tree, automated scripting, with two
minor fixup to keep things compiling. All the common forms in the tree
were removed with a perl script.
Sponsored by: Netflix
The interrupt context save is now done in the BSP. This avoids an issue
where a register is modified by the interrupt handler before it is
saved. Specifically, the MSR register was modified by the `addi`
instruction in the interrupt handler before the MSR was saved. This
caused the MSR to be saved with the wrong value.
Closes#4962
## spec/stm32h7: Default nucleo-h755zi BSP to build for CORE_M7
Some of the STM32H7 parts have a secondary Cortex M4 core included and require the user to select which core they are compiling for. The `arm/nucleo-h755zi` BSP was lacking a default core selection, causing the BSP to fail to build with the default options selected. This PR changes the default option to select the larger Cortex M7 core by default.
Use first 1GiB of the DDR RAM with the exception of a potential 64KiB NULL
pointer protection area by default. The upper part of the DDR RAM may be used
by the RPU or for dynamic memory.
The i.MXRT1166 has three iomux controllers. The driver in RTEMS
(originally for i.MX6) doesn't support that. Switching to absolute
addresses for the pins in the FDT works around that.
Compared to changing the IOMUX driver, it has the following advantages:
- If a devicetree is written, the pinctrl-groups don't have to be split
up between different iomux controllers which makes device trees simpler
to read.
- A driver or application doesn't has to handle multiple pinctrl-groups
which simplifies the drivers.
The C files that provide the device trees are generated with
rtems-bin2c. Due to that, the license information in these files is
lost. Therefore this patch adds the header manually. Also adapt the
commands that are used to generate the files to reflect that.
