* shared/include/cpuIdent.c, shared/include/cpuIdent.h: Added support
for e500v2. Removed IVPR/IVOR/HWIVOR features since they are included
in Book E.
* new-exceptions/bspsupport/vectors.h,
new-exceptions/bspsupport/ppc_exc.S,
new-exceptions/bspsupport/ppc_exc_address.c,
new-exceptions/bspsupport/ppc_exc_categories.c,
new-exceptions/bspsupport/ppc_exc_initialize.c,
new-exceptions/bspsupport/ppc_exc_prologue.c: Added support for
e500v2. Added exception vector defines for Book E types. Removed
e200 exception vector defines. Added e500 exception vector defines.
Unified IVOR calculation for e200 and e500 (e200z1 has hard wired
IVOR values).
PR 1599/cpukit
* new-exceptions/bspsupport/ppc_exc_hdl.c: Rename
_Context_Switch_necessary to _Thread_Dispatch_necessary to more
properly reflect the intent.
PR 1573/cpukit
* mpc5xx/irq/irq.c, mpc5xx/irq/irq_asm.S,
new-exceptions/bspsupport/ppc_exc.S,
new-exceptions/bspsupport/ppc_exc_asm_macros.h,
new-exceptions/bspsupport/ppc_exc_hdl.c: Add a per cpu data structure
which contains the information required by RTEMS for each CPU core.
This encapsulates information such as thread executing, heir, idle
and dispatch needed.
* new-exceptions/bspsupport/ppc_exc_categories.c:
PSIM *must*not* hook SYS vector which is used e.g.,
for firmware I/O.
Added entries for AltiVec on PSIM.
* new-exceptions/bspsupport/vectors_init.c: added
features to C_exception_handler() (the default global
handler):
- try to catch recursion
- print info about context where the exception occurred
(ISR or task with task ID).
- suspend offending task rather than spinning forever.
* new-exceptions/bspsupport/vectors_init.c: must not
align start of stack downwards (we don't 'own' memory
below start). Instead, use original boundaries but
align the stack pointer as required.
Added test to verify that R13 was loaded with _SDA_BASE_
during early initialization (low-level assembly code
relies on it).
* new-exceptions/bspsupport/ppc_exc_asm_macros.h: Added
a test to TEST_LOCK_crit so that a context switch is
always prevented if MSR_CE is not set in the interrupt mask.
(Support mode where the user wants to leave MSR_CE always enabled
but abstains from calling OS primitives from the exception
handler.)
* new-exceptions/bspsupport/ppc_exc_asm_macros.S,
new-exceptions/bspsupport/ppc_exc_bspsupp.h,
new-exceptions/bspsupport/ppc_exc_hdl.c,
new-exceptions/bspsupport/vectors_init.c:
fixed and enabled stack-switching algorithm which figures out
if we already run on the ISR stack rather than relying on the
_ISR_Nest_level.
Added 'ppc_exc_crit_always_enabled' variable which defines
the semantics of critical interrupts. Added a test to
TEST_LOCK_crit so that calling ppc_exc_wrapup() (and
possibly the dispatcher) is always skipped if the BSP/user
wants to leave critical interrupts always enabled (at the
expense of having no OS support).
changed TEST_LOCK_mchk so that asynchronous machine-check
handlers never call ppc_exc_wrapup() (and the dispatcher).
We don't want to disable MSR_ME ever (to avoid checkstops)
and hence asynchronous MEs must not use OS services anyways.
added and commented new variables 'ppc_exc_intr_stack_size'
'ppc_exc_crit_always_enabled'.
* new-exceptions/bspsupport/irq.c: don't disable irqs
at the interrupt controller (PIC) during initialization -- this
caused problems where some BSPs's BSP_disable_irq_at_pic() routine
did not ignore IRQ lines associated with cascaded PICs.
Rely on the BSP (BSP_setup_the_pic()) to provide a good
initial setup.
* new-exceptions/bspsupport/ppc_exc_asm_macros.h,
new-exceptions/bspsupport/ppc_exc.S,
new-exceptions/bspsupport/README,
new-exceptions/bspsupport/ppc_exc_hdl.c:
Thomas Doerfler clarified (thanks!) that raising an
exception and executing the 1st instruction is not
an atomical operation. I added a fix to the code that
checks if a lower-priority interrupt is under way:
we now not only test if the 'lock' variable was set
but also check if the interrupted PC points to the
'write lock' instruction.
Added more comments and updated README.
* Makefile.am, new-exceptions/bspsupport/README:
provide new irq_bspsupport.rel which was
split out of exc_bspsupport.rel to provide finer-grained
control over what BSPs want to use.
* new-exceptions/e500_raw_exc_init.c: map DEC
exception to ASM_BOOKE_DEC_VECTOR instead of ASM_DEC_VECTOR.
Fixed wrong mapping of ASM_BOOKE_FIT_VECTOR
(was ASM_BOOKE_PIT_VECTOR).
* new-exceptions/raw_exception.c, new_exceptions/raw_exception.h,
new_exceptions/bspsupport/irq.c: renamed ASM_BOOKE_PIT_VECTOR
to ASM_BOOKE_DEC_VECTOR to be closer to 'official'
nomenclature.
* new-exceptions/bspsupport/ppc_exc_hdl.c: make sure
RI is set in the exception frame and panic if it isn't
(state info might have been lost). This only affects
classic PPC.
* new-exceptions/bspsupport/README,
new-exceptions/bspsupport/ppc_exc_bspsupp.h
new-exceptions/bspsupport/vectors_init.c:
added crude test to make sure MMU maps memory as
write-back enabled.
* new-exceptions/bspsupport/ppc_exc_test.c,
new-exceptions/bspsupport/vectors_init.c,
new-exceptions/bspsupport/ppc_exc_bspsupp.h,
new-exceptions/bspsupport/README,
new-exceptions/bspsupport/irq_supp.h:
Added README and some comments; now use TRAP exception
in ppc_exc_test.c so that it works on PSIM.
