ARM's GICv2 is configurable and its attributes vary between
implementations including omission of specific interrupts. This allows
BSPs to accomodate those varying implementations with customized
attribute sets.
This adds the SMP function that supports spinup of additional CPU cores
using the ARM standard PSCI inteface. This interface is provided by QEMU
as well as ARM Trusted Firmware running in monitor mode (EL3) on ARMv7 and
AArch64 CPUs. This supports activation va SMC or HVC instructions
depending on BSP configuration.
Certain files related to the Zynq BSP's I2C driver are useable by the ZynqMP BSP as well.
Moved these files to shared directory in anticipation of I2C support for ZynqMP.
This simplifies the implementation a bit. Declare _TOD_Days_to_date[] in
<rtems/score/todimpl.h>. Make _TOD_Days_per_month[] and
_TOD_Days_since_last_leap_year[] static.
Update #4338.
Rename LEON3_FATAL_INVALID_CACHE_CONFIG_MAIN_PROCESSOR in
LEON3_FATAL_INVALID_CACHE_CONFIG_BOOT_PROCESSOR since the term
"boot processor" is used elsewhere in the code base.
It wasn't possible to keep the CS line low between multiple message
descriptors in one transfer. This patch reworks the driver so that it is
possible.
Update #4180
The Pi firmware added a wfe(wait for event), the cores 1-3 wait
for the start address being written to the mailbox register, followed
by a SEV poke to the mailbox that acts as a wfe wake-up event.
Move _CPU_Fatal_halt() declaration to <rtems/score/cpuimpl.h> and make sure it
is a proper declaration of a function which does not return. Fix the type of
the error code. If necessary, add the implementation to cpu.c. Implementing
_CPU_Fatal_halt() as a function makes it possible to wrap this function for
example to fully test _Terminate().
Do not return a status code in bsp_interrupt_facility_initialize() since this
leads to unreachable code in bsp_interrupt_initialize(). Use RTEMS_DEBUG
assertions in bsp_interrupt_facility_initialize() if necessary.
Add default implementations for bsp_interrupt_get_affinity() and
bsp_interrupt_set_affinity() which are required to link all tests in SMP
configurations.
Update #3269.
Add rtems_interrupt_entry_remove(). Split up irq-generic.c into several files.
In particular, place all functions which use dynamic memory into their own
file.
Add optional macros to let the BSP customize the vector installation after
installing the first entry and the vector removal before removing the last
entry:
* bsp_interrupt_vector_install()
* bsp_interrupt_vector_remove()
Use these new customization options in the m68k/genmcf548x BSP so re-use the
generic interrupt controller support.
Update #3269.
Return RTEMS_INCORRECT_STATE instead of RTEMS_INTERNAL_ERROR in case the
interrupt support is not initialized. This is similar to
rtems_timer_server_fire_after() for example.
Update #3269.
Add rtems_interrupt_raise_on() and rtems_interrupt_clear().
Add a default implementation which just returns RTEMS_UNSATISFIED for
valid parameters.
Update #3269.
Add RTEMS_FATAL_SOURCE_SPURIOUS_INTERRUPT as the fatal source for
spurious interrupts. Use the interrupt vector number of the spurious
interrupt for the fatal code.
Update #3269.
When compiling the lwIP port for the TMS570, there
were issues with the BSP. Headers are expected in a folder
named ti_herc which did not exist. This fixes the issue.
Furthermore, there were multiple warnings about define redefinitions.
This was fixed as well.
These patches were submitted a few months ago, but it was found out
that the default-by-family: [] were missing in the GPIO .yml lines.
This was fixed in this patch.
This patch accounts for different pins for the ETH peripheral
on STM32H7 devices. For example, the Nucleo H743ZI has slightly
different pins than other STM32H7 boards.
Fully support the interrupt extension API to set/get the interrupt affinity.
Remove LEON3_irq_to_cpu which defined the interrupt to processor mapping in a
BSP-specific way.
Update #3269.
Skip the data cache initialization if we are a secondary processor.
The bug was introduced by e164df5e33 and
did not show up in tests using Qemu since the data cache behaviour is
not emulated.
