Use a processor-specific interrupt frame during context switches in case
the executing thread is longer executes on the processor and the heir
thread is about to start execution. During this period we must not use
a thread stack for interrupt processing.
Update #2809.
We must not load registers (e.g. PSR) from the heir context area before
the heir stopped execution.
With this patch the write to PSR is divided into two steps. We first update
the current window pointer and then we restore the status registers and
enable traps. This allows us to move the first write to PSR to be before
the write to WIM, as there is now no risk that we get an interrupt where
the CWP and WIM would be inconsistent. We only need to make sure that we
do not use any of the non-global registers or instructions that affects
CWP for three instructions after the write.
In the earlier code the non-global %o1 register was used right after the
write to PSR, which required the use of three nop:s.
According to the C11 and C++11 memory models only a read-modify-write
operation guarantees that we read the last value written in modification
order. Avoid the sequential consistent thread fence and instead use the
inter-processor interrupt to set the thread dispatch necessary
indicator.
The SPARC ABI is a bit special with respect to the floating point context.
The complete floating point context is volatile. Thus from an ABI point
of view nothing needs to be saved and restored during a context switch.
Instead the floating point context must be saved and restored during
interrupt processing. Historically the deferred floating point switch is
used for SPARC and the complete floating point context is saved and
restored during a context switch to the new floating point unit owner.
This is a bit dangerous since post-switch actions (e.g. signal handlers)
and context switch extensions may silently corrupt the floating point
context. The floating point unit is disabled for interrupt handlers.
Thus in case an interrupt handler uses the floating point unit then this
will result in a trap.
On SMP configurations the deferred floating point switch is not
supported in principle. So use here a safe floating point support. Safe
means that the volatile floating point context is saved and restored
around a thread dispatch issued during interrupt processing. Thus
post-switch actions and context switch extensions may safely use the
floating point unit.
Update #2270.
* Coding style cleanups.
* Use OS reserved trap 0x89 for IRQ Disable
* Use OS reserved trap 0x8A for IRQ Enable
* Add to SPARC CPU supplement documentation
This will result in faster Disable/Enable code since the
system trap handler does not need to decode which function
the user wants. Besides the IRQ disable/enabled can now
be inline which avoids the caller to take into account that
o0-o7+g1-g4 registers are destroyed by trap handler.
It was also possible to reduce the interrupt trap handler by
five instructions due to this.
Fix context switch on SMP for ARM, PowerPC and SPARC.
Atomically test and set the is executing indicator of the heir context
to ensure that at most one processor uses the heir context. Break the
busy wait loop also due to heir updates.
We must not alter the is executing indicator in
_CPU_Context_Initialize() since this would cause an invalid state during
a self restart.
The is executing indicator must be valid at creation time since
otherwise _Thread_Kill_zombies() uses an undefined value for not started
threads. This could result in a system life lock.
The current implementation of task migration in RTEMS has some
implications with respect to the interrupt latency. It is crucial to
preserve the system invariant that a task can execute on at most one
processor in the system at a time. This is accomplished with a boolean
indicator in the task context. The processor architecture specific
low-level task context switch code will mark that a task context is no
longer executing and waits that the heir context stopped execution
before it restores the heir context and resumes execution of the heir
task. So there is one point in time in which a processor is without a
task. This is essential to avoid cyclic dependencies in case multiple
tasks migrate at once. Otherwise some supervising entity is necessary to
prevent life-locks. Such a global supervisor would lead to scalability
problems so this approach is not used. Currently the thread dispatch is
performed with interrupts disabled. So in case the heir task is
currently executing on another processor then this prolongs the time of
disabled interrupts since one processor has to wait for another
processor to make progress.
It is difficult to avoid this issue with the interrupt latency since
interrupts normally store the context of the interrupted task on its
stack. In case a task is marked as not executing we must not use its
task stack to store such an interrupt context. We cannot use the heir
stack before it stopped execution on another processor. So if we enable
interrupts during this transition we have to provide an alternative task
independent stack for this time frame. This issue needs further
investigation.
Use register g6 for the per-CPU control of the current processor. The
register g6 is reserved for the operating system by the SPARC ABI. On
Linux register g6 is used for a similar purpose with the same method
since 1996.
The register g6 must be initialized during system startup and then must
remain unchanged.
Since the per-CPU control is used in all critical sections of the
operating system, this is a performance optimization for the operating
system core procedures. An additional benefit is that the low-level
context switch and interrupt processing code is now identical on non-SMP
and SMP configurations.
The registers g2 through g4 are reserved for applications. GCC uses
them as volatile registers by default. So they are treated like
volatile registers in RTEMS as well.
The _CPU_Context_switch() is a normal function call. The following
registers are volatile (the caller must assume that the register
contents are destroyed by the callee) according to "SYSTEM V APPLICATION
BINARY INTERFACE - SPARC Processor Supplement", Third Edition: g1, o0,
o1, o2, o3, o4, o5. Drop these registers from the context.
Ensure that offset defines match the structure offsets.
_CPU_Context_switch_to_first_task_smp() branches to
done_flushing which requires o3 to be initalized with
"self per-CPU control", this adds initialization of
o3. This problem only affects SMP, see commit
f8ad6c6f7f were usage of o3 was intruduced.
Move the _CPU_Context_switch(), _CPU_Context_restore() and
_CPU_Context_switch_to_first_task_smp() code since the method to obtain
the processor index is BSP specific.
As a side-effect the PR2082 is fixed with this and later changes.
The commit restores the _ISR_Handler code to the original version in
"cpukit/score/sparc/cpu_asm.S" in commit
6d42b4c60a. A list of reverted changes
follows.
commit c236082873
Author: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Tue Jul 30 15:54:53 2013 +0200
smp: Provide cache optimized Per_CPU_Control
Delete _Per_CPU_Information_p.
This commit was completely reverted.
commit e517714b7c
Author: Jennifer Averett <jennifer.averett@oarcorp.com>
Date: Tue Feb 26 12:31:23 2013 -0600
sparc: Remove dead code that was leftover from SMP development.
This commit was completely reverted.
commit 47a61aa16f
Author: Joel Sherrill <joel.sherrill@OARcorp.com>
Date: Fri Oct 7 14:35:03 2011 +0000
2011-10-07 Daniel Hellstrom <daniel@gaisler.com>
PR 1933/cpukit
* shared/irq_asm.S: From code inspection I have found the following
issues (most SMP), and some improvements in irq_asm.S. I would need a
long test with interrupts to verify the interrupt handler better,
however I can not see that these patches hurt. Please see comment per
hunk below, One should go through the file to indent delay-slots
correctly, I have fixed some in the patch areas. An extra space is
added in front of delay slots to indicate a delay slot.
This commit was completely reverted.
commit 0bd3f7e5d1
Author: Jennifer Averett <Jennifer.Averett@OARcorp.com>
Date: Thu Jul 28 17:33:07 2011 +0000
2011-07-28 Jennifer Averett <Jennifer.Averett@OARcorp.com>
PR 1801
* shared/irq_asm.S: Modifications to synch the sparc with the smp
working tree.
This commit was completely reverted.
commit 5d69cd33e9
Author: Joel Sherrill <joel.sherrill@OARcorp.com>
Date: Wed Mar 16 20:05:30 2011 +0000
2011-03-16 Jennifer Averett <jennifer.averett@OARcorp.com>
PR 1729/cpukit
* shared/irq_asm.S: New file.
The parts modifying the original code of _ISR_Handler were reverted.
Only the content move remains.
Script does what is expected and tries to do it as
smartly as possible.
+ remove occurrences of two blank comment lines
next to each other after Id string line removed.
+ remove entire comment blocks which only exited to
contain CVS Ids
+ If the processing left a blank line at the top of
a file, it was removed.
PR 1933/cpukit
* shared/irq_asm.S: From code inspection I have found the following
issues (most SMP), and some improvements in irq_asm.S. I would need a
long test with interrupts to verify the interrupt handler better,
however I can not see that these patches hurt. Please see comment per
hunk below, One should go through the file to indent delay-slots
correctly, I have fixed some in the patch areas. An extra space is
added in front of delay slots to indicate a delay slot.
