Replace the variant patterns in the default-by-variant list with an
explicit list of matching BSPs.
The change was tested by comparing the output of
./waf bspdefaults
before and after the change.
Low-end configurations may want to have the HTIF support removed.
Enable the option by default. Fix formatting. Fix node validity
checks.
Updates #4779.
The address of the nandpsu peripheral is specific to the ZynqMP SoC and
not relevant to other devices that might have one or more instances of
this peripheral.
This adds Xilinx's driver for the Xilinx NAND controller embedded in the
ZynqMP SoC. Within that device alone, it is possible to access this
peripheral from MicroBlaze, ARMv7, and ARMv8 cores. This has been added
to the hardware ZynqMP BSPs since QEMU does not support emulation of
this peripheral. This driver supports polled operation only. The
imported files are and should be able to remain unmodified. Import
information is kept in bsps/shared/dev/nand/VERSION.
This support code is necessary for many Xilinx-provided bare metal device
drivers supported on ARM, AArch64, and MicroBlaze platforms. Support for
all of these architectures is kept under bsps/include due to multiple
architecture variants being supported which requires complex logic in
the build system. The imported files are and should be able to remain
unmodified. Import information is kept in bsps/shared/xil/VERSION.
Currently generic RISC-V BSPs (riscv/riscv) that start with rv64 and not
rv64*_medany will start at 0x70000000. This adds high maintenance overhead
and deviates from almost all other RISC-V-based OSes and baremetal programs
that start at 0x80000000. Further, testing now has to account for an extra
parameter (medany or not) that doubles the number of BSPs need to be
tested.
This commit defaults all RV64 BSPs to use medany code model to allow starting
all BSPs at 0x80000000. BSPs that require different code models and/or
start addresses are custom and need to add their own entries.
Updates #4775
With the old build system in RTEMS 5 that was possible by just
overwriting BOARD_Sdram_Config and setting a custom
ATSAM_MEMORY_SDRAM_SIZE during building the BSP. In the new build system
that ATSAM_MEMORY_SDRAM_SIZE is set exclusively by the selected SDRAM
chip.
This patch adds the possibility to specify a "custom-0x100000" or
similar as SDRAM type where the number gives the SDRAM size.
This enables the tracing of interrupt entry/exit events through an
application configuration option. The interrupt processing can be
viewed with Trace Compass using rtems-record-lttng from the RTEMS Tools.
Update #4769.
This adds a BSP variant for the ZynqMP BSP family to support the
Innoflight CFC-400X platform. To properly support the CFC-400X, device
trees were added to the ZynqMP platform due to both the optional
management interface as well as alternate physical configuration of the
ethernet interfaces.
By default, allocate the IDLE task storage areas from the RTEMS Workspace.
This avoids having to estimate the thread-local storage size in the default
configuration.
Add the application configuration option CONFIGURE_IDLE_TASK_STORAGE_SIZE to
request a static allocation of the task storage area for IDLE tasks.
Update #3835.
Update #4524.
Add the INTERNAL_ERROR_IDLE_THREAD_CREATE_FAILED fatal error in case the
creation of an idle thread fails. This may happen due to a failing create
extension provided by the application.
This patch adds new Raspberry pi 4B AArch64 BSP to the RTEMS Family. Currently
only LP64 ABI is supported. ILP32 is not supported. RAM starts from 0x80000 in
64Bit kernel mode and MMU from 0x0. All Raspberrypi Pi 4B models and Raspberry
Pi 400 are supported. All the IRQs are similiar to the older Raspberry pi 2 ARM
BSP.
Raspberry Pi 4B has 2 types of UARTs. Only PL011 serial is supported currently.
Mini-UART is not supported. Mini-UART is default UART on the board so it needs
to be disabled by adding "dtoverlay=disable-bt" to the config.txt. No support
for additional 4 PL011-UARTs on the board.
The raspberrypi.h includes many of the address required for the future
development of the RPi 4B BSP. This includes peripherals, ARM Timer, VideoCore
Timer, Watchdog, Mailbox, AUX, FIQs and IRQs.
The Microchip PolarFire SoC support is implemented as a
riscv BSP variant to boot with any individual hart(cpu core)
or SMP based on the boot HARTID configurable and support
components are 4 CPU Cores (U54), Interrupt controller (PLIC),
Timer (CLINT), UART.
There is not just big-endian on ARM. We have two variants BE32
(obsolete) and BE8. The Cortex-R5F processor supports only BE8,
however, some TMS570 variants are BE32 internally. In GCC 8 and later,
the --be8 option is passed to the linker based on the selected
architecture or CPU. Use BE32 by default for the TMS570 BSP.
In GCC, see:
commit 63d03dcecdafe34715282a5155cfc2162375feca
Author: Richard Earnshaw <rearnsha@arm.com>
Date: Mon Jul 3 13:22:05 2017 +0000
[arm] Clean up generation of BE8 format images.
Added support for Cobham Gaisler NOEL-V systems. The NOEL-V support
is implemented as a riscv BSP. Both 32-bit and 64-bit processor
systems are supported. Cobham Gaisler's NOEL-V RISC-V processor IP
is described here:
https://www.gaisler.com/NOELV
Compatible with the following NOEL-V FPGA example design ranges
available from Cobham Gaisler. Follow the links for free
bit-streams, DTS/DTB, user's manuals and quick-start guides:
- NOEL-ARTYA7-EX (https://www.gaisler.com/NOEL-ARTYA7)
- NOEL-PF-EX (https://www.gaisler.com/NOEL-PF)
- NOEL-XCKU-EX (https://www.gaisler.com/NOEL-XCKU)
Uses the shared GRLIB APBUART console driver "apbuart_termios.c".
APBUART devices are probed using device tree.
Closes#4225.
The ABI flags for the amd64 BSP contain the -Werror=return-type flag. There is no reason for this to be there so it has been removed. The same option has also been removed amd64.cfg file.
- Versal has IO mapped to the upper 64bit address space and
needs full 64bit addresses.
- Add xilinx_versal_aiedge for custom hardware
- Make the hardware settings the defaults and qemu as variants
Closes#4693
This adds the configure option CONFIGURE_POSIX_TIMERS_FACE_BEHAVIOR
which allows the application to choose whether to have the POSIX
timer_create() function follow the behavior defined by POSIX or
the FACE Technical Standard.
Updates #4691.
rtl-mdreloc-arm.c was used as the basis for rtl-mdreloc-aarch64.c. This lead
to some code being shared by the two files. The code was consolidated into
rtl-unwind-arm.c.
Closes#4686
