This adds a test to very that remounting a completely used, but empty
NOR JFFS2 filesystem is possible. Previously, this triggered an edge
condition in the JFFS2 scan code that prevented remount of a correctly
formed and uncorrupted filesystem.
The RAM origin had an unnecessary alignment requirement and the RAM
lenght had a reference that couldn't possibly be used. This removes
those obsolete option specifiers.
When the switch to waf occurred, the SMP support in i386 was left out
causing it to accumulate a minor amount of cruft. This enables SMP for
the i386 BSPs that support it and updates them for the API drift that
has occurred since the change.
This enables the VME support for the MVME2500. Note that the PCIe
support from libbsd is used. So you need the related libbsd patches for
this to work.
If the drivers in libbsd are not enabled, the linker should not pick up
anything from this patch.
Remove obsolete tms570ls3137_hdk_with_loader BSP variant. With the new
memory origin/size build options this variant is no longer required.
Update #4982.
Hi all, this is my first email patch submission and my first contribution to RTEMS, so please give any
feedback you have!
This patch enables interrupt driven data reception on USART ports on
STM32F4 series chips. This feature is gated behind the config flag
BSP_CONSOLE_USE_INTERRUPTS. If this flag is not set to True, the older
polling implementation will be used. I tested this feature on STM32F401CE
(blackpill) and STM32 Nucleo F411RE boards, with both capable of keeping
up with a 115200 baud continous data stream. With the older polling
implementation, both would drop bytes at 9600 baud. In addition, I
updated the implementation of usart_set_attributes to support changing
the baud rate of the USART port based on the input speed.
With this, it is possible to use GPIOs as CS pins in the LPSPI. To avoid
additional complexity, the GPIOs will have the same limitations as the
native (hardware) CS pins.
The GPIO CS feature adds a number of extra code when starting SPI
transfers on this controller. Therefore it is possible to disable the
additional code by just setting the IMXRT_LPSPI_MAX_CS option to 0. In
that case only native CS pins are supported.
At the moment, this feature is only enabled on i.MXRT1166 by default
because it is not tested on i.MXRT1050. But it should work there too.
For uniprocessor configurations, the selection of
RTEMS_MULTIPROCESSOR_RESOURCE_SHARING results in a priority ceiling
mutex.
Build the MrsP validation tests only if RTEMS_SMP is enabled.
Update #3716.
The code coverage build is usually done without compiler optimizations.
This results in long performance test runtimes and useless performance
results.
Enable an individual testsuite only through the corresponding enable.
Use BUILD_TESTS to change the default value of the individual testsuite
enable options. This allows the user to enable all testsuites with
specific exceptions.
For example, this builds all testsuites except the benchmarks:
[arch/bsp]
BUILD_TESTS = True
BUILD_BENCHMARKS = False
This fixes some issues in the Xilinx support code that are critical to
support the Cortex-R5F cores present in my Xilinx SoCs. The imported
Cortex-R5 xil_cache.c matches the existing information in
bsps/shared/xil/VERSION.
Merge the timecounter and CPU counter support for the leon3 BSP family.
Remove now unused functions from the CPU counter support of the erc32
and leon3 BSPs.
Update #4954.
