Remove the thread action handler parameter from
_Thread_Action_initialize() and instead set it later in
_Thread_Add_post_switch_action(). This avoids a dependency on the
thread action handler via the thread initialization.
Make rtems_initialize_data_structures(),
rtems_initialize_before_drivers() and rtems_initialize_device_drivers()
static. Rename rtems_initialize_start_multitasking() to
rtems_initialize_executive() and call the registered system
initialization handlers in this function. Add system initialization API
available via #include <rtems/sysinit.h>. Update the documentation
accordingly.
This is no functional change, only the method to call the existing
initialization routines changes. Instead of direct function calls a
table of function pointers contained in the new RTEMS system
initialization linker set is used. This table looks like this (the
actual addresses depend on the target).
nm *.exe | grep _Linker | sort
0201a2d0 D _Linker_set__Sysinit_begin
0201a2d0 D _Linker_set__Sysinit_bsp_work_area_initialize
0201a2d4 D _Linker_set__Sysinit_bsp_start
0201a2d8 D _Linker_set__Sysinit_rtems_initialize_data_structures
0201a2dc D _Linker_set__Sysinit_bsp_libc_init
0201a2e0 D _Linker_set__Sysinit_rtems_initialize_before_drivers
0201a2e4 D _Linker_set__Sysinit_bsp_predriver_hook
0201a2e8 D _Linker_set__Sysinit_rtems_initialize_device_drivers
0201a2ec D _Linker_set__Sysinit_bsp_postdriver_hook
0201a2f0 D _Linker_set__Sysinit_end
Add test sptests/spsysinit01.
Update #2408.
We must not load registers (e.g. PSR) from the heir context area before
the heir stopped execution.
With this patch the write to PSR is divided into two steps. We first update
the current window pointer and then we restore the status registers and
enable traps. This allows us to move the first write to PSR to be before
the write to WIM, as there is now no risk that we get an interrupt where
the CWP and WIM would be inconsistent. We only need to make sure that we
do not use any of the non-global registers or instructions that affects
CWP for three instructions after the write.
In the earlier code the non-global %o1 register was used right after the
write to PSR, which required the use of three nop:s.
We must ensure that the Thread_Control::Wait information update is
visible to the target thread before we update its wait flags, otherwise
we may return out of date events or a wrong status.
This reverts the relevant part of commit
da06fe948c. The acquire/release order is
superfluous for the next ticket increment. The mutual exclusion is
guaranteed by the acquire load from and release store to the next
serving atomic variable.
According to the C11 and C++11 memory models only a read-modify-write
operation guarantees that we read the last value written in modification
order. Avoid the sequential consistent thread fence and instead use the
inter-processor interrupt to set the thread dispatch necessary
indicator.
This patch adds a brief description of how context state is saved into the
SP on exception entry, and makes a few changes to _ARMV7M_Exception_default
in order to make it a bit more efficient. I also removed the unused 'v7mfsz'
input parameter.
This should apply over Sudarshan's patch.
