- Add the section alignment to the size as the allocator may not
provide correctly aligned memory
- Only include symbols in the section when locating symbols. The
powerpc was incorrectly adding SDATA BSS symbols to the BSS offset
overrunning the section
Closes#4950
- Load symbols before allocation.
- Parse reloc records and place any reloc recs in a cache to use
while the allocator is locked.
- Relocate symbols after section allocation.
- Split section loading into allocation/locating and loading.
- Update all arch back-ends with a new reloc interface to control
tramp handling.
- Add `-a` and `-t` to the object list shell command.
Closes#3741
- Add support for architecure sections that can be handled by the
architecture back end.
- Add trampoline/fixup support for PowerPC. This means the PowerPC
now supports large memory loading of applications.
- Add a bit allocator to manage small block based regions of memory.
- Add small data (sdata/sbss) support for the PowerPC. The support
makes the linker allocated small data region of memory a global
resource available to libdl loaded object files.
Updates #3687
Updates #3685
- Add trampolines to support relocs that are out of range on
support architectures.
- Support not loading separate text/data sections in an object
file if the symbol provided in the section is a duplicate.
A base image may have pulled in part of an object and another
part needs to be dynamically loaded.
- Refactor the unresolved handling to scale to hundreds of
unresolved symbols when loading large number of files.
Updates #3685
- Trampolines or fixups for veneers provide long jump support
for instruciton sets that implement short relative address
branches. The linker provides trampolines when creating a
static image. This patch adds trampoline support to libdl
and the ARM architecture.
- The dl09 test requires enough memory so modules are outside
the relative branch instruction ranges for the architecture.
Updates #3685
- Load archive symbol tables to support searching of archives
for symbols.
- Search archive symbols and load the object file that contains
the symbol.
- Search the global and archives until all remaining unresolved symbols
are not found. Group the loaded object files in the pending queue.
- Run the object file and loaded dependents as a group before adding to the
main object list.
- Remove orphaned object files after references are removed.
Updates #3686
Tracking references lets us manage when an object file can be
unloaded. If an object file has references to it, it cannot be
unloaded.
Modules that depend on each other cannot be unloaded.
Updates #3605
The use of separate text and data results in uninitialised variables
being placed in the common section. There is no section in ELF for
the common variables so the loader needs to create the section and
allocate the variables in that section. This patch does that.
The patch adds a second pass over the symbols.
The issue can also be seen as a section 65522 error.
Updates #3604
The ARM C++ exception ABI uses an address ordered index table to
locate the correct frame data and this requires the EXIDX sections are
loaded in the order the order the matching text is loaded.
The EXIDX sections set the SHF_LINK_ORDER flag and link field. This patch
adds support to load those flagged sections in the linked-to section
order.
Updates #2955.
Closes#2959
Use of rtems_cache_get_maximal_line_size() is more descriptive
choice. The min/max data/instruction cache line size is not critical
there, value is used for optimization only to use single operation
for directly following sections.
Memory content changes caused by relocation has to be
propagated to memory/cache level which is used/snooped
during instruction cache fill.
Closes#2438
Synchronize each cluster of sections of the same type separately
to support even cases where text and data are allocated from different
areas (for example due allocation from different MPU protection regions).
rtems_cache_instruction_sync_after_code_change is called even to data
sections. Propagation of data only changes should not require cache
maintenance operation on sane SMP mutithread capable systems if barrier
instruction is added but be on safe side even for case where self
modifying code uses data sections initial values etc.
