The number of GPIO devices along with each of their particular
configurations is application-specific. Encoding this information as
build options also introduced a lot of clutter.
The new amd64efi BSP supports:
- multiboot2 boot format. Runs well with GRUB.
- console based on either EFI simple text output or GOP-based framebuffer
- clock based on EFI event/timer API
- early console using either hard-wired PC-AT serial or just memory buffer
- with EFI support disabled the BSP is more or less equivalent to amd64 BSP
with multiboot2 support
Do not warn about excessive shifts in imported Xilinx driver code when
building with the ILP32 ABI. The two instances of this warning produce
the desired effect of setting the upper address bits to 0.
This allows any builds targeting an installed RTEMS BSP to override
headers in the installed BSP reliably, including headers previously
installed by that or other builds. This includes applications, network
stacks, libraries, and any other builds.
Closes#4896
This patch includes the spec/build options for the riscv kendrytek210
BSP variant. It includes options to allow the frdme310arty console
UART to be used on multiple BSPS, device tree options, memory
options, and other required options for the variant.
Updates #4876
This imports the full xil_exception.h instead of an empty stub. This is
required for some Xilinx drivers. The imported files adhere to the
current VERSION file.
The objxilinxsupport build object was accidentally included twice in
some of the ZynqMP BSPs by two different drivers that required it. This
commit manually deduplicates the inclusions by moving that inclusion to
the BSP. Duplication of object inclusions is considered a bug and can
cause race conditions in the build system.
The QSPI memory is initialized and used only when the BSP configure file
sets QSPI memory size to non-zero value. Currently QSPI is run in memory
mapped mode which allows future RTEMS binary linkage and upload into QSPI
memory.
Sponsored-By: Precidata
This adds helper functions for working with NOR flash connected to the
Xilinx GQSPI controller. The helper functions are based on Xilinx's
QSPIPSU flash interrupt example.
Merge the "default" and "default-by-variant" attributes. Use an
"enabled-by" expression to select the default value based on the enabled
set. This makes it possible to select default values depending on other
options. For example you could choose memory settings based on whether
RTEMS_SMP is enabled or disabled.
The change was tested by comparing the output of
./waf bspdefaults
before and after the change.
Replace the variant patterns in the default-by-variant list with an
explicit list of matching BSPs.
The change was tested by comparing the output of
./waf bspdefaults
before and after the change.
Low-end configurations may want to have the HTIF support removed.
Enable the option by default. Fix formatting. Fix node validity
checks.
Updates #4779.
The address of the nandpsu peripheral is specific to the ZynqMP SoC and
not relevant to other devices that might have one or more instances of
this peripheral.
This adds Xilinx's driver for the Xilinx NAND controller embedded in the
ZynqMP SoC. Within that device alone, it is possible to access this
peripheral from MicroBlaze, ARMv7, and ARMv8 cores. This has been added
to the hardware ZynqMP BSPs since QEMU does not support emulation of
this peripheral. This driver supports polled operation only. The
imported files are and should be able to remain unmodified. Import
information is kept in bsps/shared/dev/nand/VERSION.
This support code is necessary for many Xilinx-provided bare metal device
drivers supported on ARM, AArch64, and MicroBlaze platforms. Support for
all of these architectures is kept under bsps/include due to multiple
architecture variants being supported which requires complex logic in
the build system. The imported files are and should be able to remain
unmodified. Import information is kept in bsps/shared/xil/VERSION.
Currently generic RISC-V BSPs (riscv/riscv) that start with rv64 and not
rv64*_medany will start at 0x70000000. This adds high maintenance overhead
and deviates from almost all other RISC-V-based OSes and baremetal programs
that start at 0x80000000. Further, testing now has to account for an extra
parameter (medany or not) that doubles the number of BSPs need to be
tested.
This commit defaults all RV64 BSPs to use medany code model to allow starting
all BSPs at 0x80000000. BSPs that require different code models and/or
start addresses are custom and need to add their own entries.
Updates #4775
With the old build system in RTEMS 5 that was possible by just
overwriting BOARD_Sdram_Config and setting a custom
ATSAM_MEMORY_SDRAM_SIZE during building the BSP. In the new build system
that ATSAM_MEMORY_SDRAM_SIZE is set exclusively by the selected SDRAM
chip.
This patch adds the possibility to specify a "custom-0x100000" or
similar as SDRAM type where the number gives the SDRAM size.
This enables the tracing of interrupt entry/exit events through an
application configuration option. The interrupt processing can be
viewed with Trace Compass using rtems-record-lttng from the RTEMS Tools.
Update #4769.
