This patch adds support for the Kendryte K210 RISC-V BSP variant.
The SoC uses the existing Interrupt Controller, Timer, and console UART.
It only needs SoC specific initialization and an embedded device tree binary
similar to the polarfire SoC BSP.
Updates #4876
This patch adds the k210 device tree source and the corresponding
device tree blob encoded in the header which is used for the
embedded device tree blob for the Kendryte K210 BSP variant.
Updates #4876
Use the mtimecmp from the PLIC/CLINT initialization in the clock driver. This
register is defined by the device tree and does not assume a fixed mapping.
In SMP configurations, check that we run on a configured processor. If not,
then there is not much that can be done since we do not have a stack available
for this processor. Just loop forever in this case. Do this in assemlby to
ensure that no stack memory is used.
Low-end configurations may want to have the HTIF support removed.
Enable the option by default. Fix formatting. Fix node validity
checks.
Updates #4779.
This patch changes the license to BSD-2 for all source files where the
copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research.
Some files also includes copyright right statements from OAR and/or
embedded Brains in addition to Gaisler.
Updates #3053.
In SMP configurations, there may be no software interrupt handler
installed when the software interrupt is processed. Add the new
interrupt handler dispatch variant
bsp_interrupt_handler_dispatch_unlikely() for this special case.
This fixes a problem with parsing the FDT compatible property by
replacing the RISCV_CONSOLE_IS_COMPATIBLE macro with calls to
the fdt_stringlist_contains function. The macro only works when
the compatible FDT entry is a single string and not a list of
strings. The new call will compare each item in the string list.
Close#4728.
The Microchip PolarFire SoC support is implemented as a
riscv BSP variant to boot with any individual hart(cpu core)
or SMP based on the boot HARTID configurable and support
components are 4 CPU Cores (U54), Interrupt controller (PLIC),
Timer (CLINT), UART.
Add the basic Microchip PolarFire SoC device tree source and blob
The mpfs-dtb.h is generated by the bin2hex
https://github.com/padmaraob/bin2hex
1.Compile and build the bin2hex.c
$ gcc -o bin2hex bin2hex.c
2.Generate the mpfs.dtb from the mpfs.dts
$ dtc -O dtb -o mpfs.dtb mpfs.dts
3.Generate the mpfs-dtb.h Header file from the mpfs.dtb.
$ ./bin2hex mpfs.dtb
Note: Resending after learning how to use git send-email, please disregard previous message.
This fixes the riscv fe310 console driver fe310_uart_read function. The function
reads the RX status/data register to check if data is available, but discards
the data and reads it a seconds time.
Also cleared the interrupt enable bit in the first_open function.
Close#4719
Added support for Cobham Gaisler NOEL-V systems. The NOEL-V support
is implemented as a riscv BSP. Both 32-bit and 64-bit processor
systems are supported. Cobham Gaisler's NOEL-V RISC-V processor IP
is described here:
https://www.gaisler.com/NOELV
Compatible with the following NOEL-V FPGA example design ranges
available from Cobham Gaisler. Follow the links for free
bit-streams, DTS/DTB, user's manuals and quick-start guides:
- NOEL-ARTYA7-EX (https://www.gaisler.com/NOEL-ARTYA7)
- NOEL-PF-EX (https://www.gaisler.com/NOEL-PF)
- NOEL-XCKU-EX (https://www.gaisler.com/NOEL-XCKU)
Uses the shared GRLIB APBUART console driver "apbuart_termios.c".
APBUART devices are probed using device tree.
Closes#4225.
This is required for ISA 2.0 support, see chapter
"Zicsr", Control and Status Register (CSR) Instructions, Version 2.0
in
RISC-V Instruction Set Manual, Volume I: RISC-V User-Level ISA
Move _CPU_Fatal_halt() declaration to <rtems/score/cpuimpl.h> and make sure it
is a proper declaration of a function which does not return. Fix the type of
the error code. If necessary, add the implementation to cpu.c. Implementing
_CPU_Fatal_halt() as a function makes it possible to wrap this function for
example to fully test _Terminate().
Do not return a status code in bsp_interrupt_facility_initialize() since this
leads to unreachable code in bsp_interrupt_initialize(). Use RTEMS_DEBUG
assertions in bsp_interrupt_facility_initialize() if necessary.
