On most i.MX* the upper bits in SW_PAD_CTL are reserved. On some chips,
like the i.MXRT1166, they are a domain write protection. Setting them to
1 can have unexpected side effects.
The device tree uses these bits for some flags. Make sure that they are
not accidentally written to some value.
The different variants of the i.MXRT have some minimal differences in
the fsl_flexspi_nor_config.h. Make sure that the header supports the
different chips.
The defines for the different clock frequencies in the
fsl_clock_config.h do not represent the clock frequencies that have been
set up in the registers. Remove them to avoid someone trusting in
correct values.
If a different chip variant is used in the i.mxrt BSP, a different
header would have to be included. Make sure that the fsl-edma driver
uses a header that doesn't have to be adapted.
The mcux_sdk has a different interface for getting the clock for
IMXRT11xx than for getting it in IMXRT10xx. Adapt simple drivers to
support that interface.
The number of GPIO devices along with each of their particular
configurations is application-specific. Encoding this information as
build options also introduced a lot of clutter.
The new amd64efi BSP supports:
- multiboot2 boot format. Runs well with GRUB.
- console based on either EFI simple text output or GOP-based framebuffer
- clock based on EFI event/timer API
- early console using either hard-wired PC-AT serial or just memory buffer
- with EFI support disabled the BSP is more or less equivalent to amd64 BSP
with multiboot2 support
The library is imported in minimalist version just to support future
amd64efi BSP.
The FreeBSD tree commit id with imported libefi version is:
ce7b20e5129cf0f269951b313d336a9c7d54d790
The MMU must be enabled during mapping changes and TLB invalidations.
When this is not the case, TLB updates do not occur correctly in all
cases. This is especially apparent when changing a block entry to a
table entry when remapping small memory ranges in an otherwise
contiguous block.
This patch adds support for the Kendryte K210 RISC-V BSP variant.
The SoC uses the existing Interrupt Controller, Timer, and console UART.
It only needs SoC specific initialization and an embedded device tree binary
similar to the polarfire SoC BSP.
Updates #4876
This patch adds the k210 device tree source and the corresponding
device tree blob encoded in the header which is used for the
embedded device tree blob for the Kendryte K210 BSP variant.
Updates #4876
The existing include path only works from inside the RTEMS build. This
fixes the include path to work both in the RTEMS build and with builds
of external apps since this file gets installed with the BSP.
Use the mtimecmp from the PLIC/CLINT initialization in the clock driver. This
register is defined by the device tree and does not assume a fixed mapping.
In SMP configurations, check that we run on a configured processor. If not,
then there is not much that can be done since we do not have a stack available
for this processor. Just loop forever in this case. Do this in assemlby to
ensure that no stack memory is used.
Interrupts must be disabled during MMU remapping since the majority of
RTEMS including interrupts expects normal memory mapping semantics such
as unaligned accesses.
