The previous implementation used an instruction cache line size of 0,
this is a bogus value. Use a instruction cache line size of 64 since
the L2 cache may have a line size of 32 or 64. A greater value should
cause no harm.
Use a FLUSH operation for _CPU_cache_invalidate_instruction_range().
This is a preperation step to support the L2 cache.
The SPARC processors supported by RTEMS have no built-in CPU counter
support. We have to use some hardware counter module for this purpose.
The BSP must provide a 32-bit register which contains the current CPU
counter value and a function for the difference calculation. It can use
for example the GPTIMER instance used for the clock driver.
The 32-bit ABIs for thread-local storage (TLS) and EABI read-only
small-data area have a conflicting register (r2) usage. Use the System
V small-data instead (here r2 is system reserved).
Remove RTEMS_COMPILER_PURE_ATTRIBUTE from _SMP_Get_current_processor()
and all _CPU_SMP_Get_current_processor(). Make inline ASM statements
volatile again. Test smptests/smpmigration01 showed that GCC optimizes
too much otherwise.
Wait for per-CPU changes into PER_CPU_STATE_READY_TO_BEGIN_MULTITASKING
later. There is no need to delay the initialization of the main
processor at this point.
Since the per-CPU SMP lock must be acquired and released to send the
message a single interrupt broadcast operations offers no benefits. If
synchronization is required, then a SMP barrier must be used anyway.
Use rtems_fatal() instead of _CPU_Fatal_halt() to shutdown processors in
SMP configurations since this allows intervention of BSP or application
specific fatal extensions.
Merge RTEMS_FATAL_SOURCE_BSP_GENERIC and RTEMS_FATAL_SOURCE_BSP_SPECIFIC
into new fatal source RTEMS_FATAL_SOURCE_BSP. This makes it easier to
figure out the code position given a fatal source and code.
Move _SMP_Request_other_cores_to_shutdown() invocation from
rtems_shutdown_executive() to _Internal_error_Occurred() to allow a
proper shutdown on SMP configurations even in the error case.
Disable interrupts as the first step in _Internal_error_Occurred() to
get a defined execution context for the fatal extensions.
Make _ISR_Disable_without_giant() available for non-SMP configurations.
Do not return to BSP context in the exit() shutdown path. This makes it
possible to re-use the initialization stack. It can be used for the
interrupt stack for example. On targets with a small RAM this is a
considerable benefit.
This change eliminates also some special cases and simplifies the code.
Delete _Thread_Set_global_exit_status(),
_Thread_Get_global_exit_status() and _Thread_Stop_multitasking().
Merge systems states SYSTEM_STATE_SHUTDOWN and SYSTEM_STATE_FAILED into
new system state SYSTEM_STATE_TERMINATED. This reflects that all system
termination paths end up in _Internal_error_Occurred().
Instead of SPRG0 (= special purpose register 272) use the new global
symbol _PPC_INTERRUPT_DISABLE_MASK to store the interrupt disable mask.
The benefit is that it is now possible to disable interrupts without
further run-time initialization in boot_card().
At least on Freescale e500 cores this leads also to a faster execution
since the mfmsr and mfspr instruction require four cycles to complete.
The instructions to load the mask value can execute while the mfmsr is
in progress.
Move SMP interrupt stack initialization for secondary processors from
_SMP_Handler_initialize() to _ISR_Handler_initialization() to avoid code
duplication. Apply _CPU_Interrupt_stack_setup() to all interrupt
stacks.
