This was tracked as PR91.
* rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
is used to specify if the port uses the standard macro for this (FALSE).
A TRUE setting indicates the port provides its own implementation.
* rtems/score/c_isr.inl: Deleted and contents merged into cpu.c.
* cpu.c: Received contents of c_isr.inl.
* Makefile.am: Deleted reference to c_isr.inl.
This modification is part of the submitted modifications necessary to
support the IBM PPC405 family. This submission was reviewed by
Thomas Doerfler <Thomas.Doerfler@imd-systems.de> who ensured it did
not negatively impact the ppc403 BSPs. The submission and tracking
process was captured as PR50.
* ppc403/console/console405.c ppc403/tty_drv/.cvsignore,
ppc403/tty_drv/Makefile.am, ppc403/tty_drv/tty_drv.c,
ppc403/tty_drv/tty_drv.h: New files.
* Makefile.am, README, configure.ac, old_exception_processing/cpu.c,
old_exception_processing/cpu.h, ppc403/Makefile.am,
ppc403/clock/clock.c, ppc403/console/Makefile.am,
ppc403/console/console.c, ppc403/ictrl/ictrl.c, ppc403/ictrl/ictrl.h,
ppc403/timer/timer.c: Modified.
* new_exception_processing/cpu.h, old_exception_processing/cpu.c:
old_exception_processing/cpu.h, Added _CPU_Initialize_vectors().
In particular, spurious vector initialization had to be moved
on old exception processing model.
<charles.gauthier@iit.nrc.ca>, and Darlene A. Stewart
<Darlene.Stewart@nrc.ca> to add support for a number of very
significant things:
+ BSPs for many variations on the Motorola MBX8xx board series
+ Cache Manager including initial support for m68040
and PowerPC
+ Rework of mpc8xx libcpu code so all mpc8xx CPUs now use
same code base.
+ Rework of eth_comm BSP to utiltize above.
John reports this works on the 821 and 860
