-- configure now fails to detect the toolchain for linux-posix.
As work-around, I have reverted to the old behavior of RTEMS_TARGET_CPU_NAME,
thus no_cpu/no_bsp will fail badly in configure again.
> When I run my script that just repeatedly builds different targets, some
> of them die with an error like this:
>
> Making all RTEMS_BSP=gen68360 in cpugmake[5]: Entering directory
> `/usr1/rtems/build/build-m68k-rtems/c/src/exec/score/cpu'
> Making all RTEMS_BSP=gen68360 in @RTEMS_CPU@
> /bin/sh: @RTEMS_CPU@: No such file or directory
> gmake[5]: *** [all] Error 1
> gmake[5]: Leaving directory
> `/usr1/rtems/build/build-m68k-rtems/c/src/exec/score/cpu'
>
> It is not always the same variable substitution that fails. Sometimes it
> is @INSTALL@. But reliably, it is a variable substitution that is
> failing.
>
> Do you have any idea why this happens?
Yep, I think I know what's going on.
AC_SUBST(RTEMS_CPU) is missing in configure.ins, thus @RTEMS_CPU@ in
target.cfg.in doesn't get substituted correctly, causing the bug above. Due
to the redundancy of RTEMS_CPU, other most BSPs don't seem to be affected.
Other similar problems probably exist for the unix/posix bsp and the hppa.1
cpu, because their */tools/*Makefile.ams require RTEMS_CPU, too.
This patch should fix the nastiest configuration bugs for no_cpu/no_bsp.
With this patch applied, configure --target=no_cpu-rtems now correctly
acknowledges its configuration, but later fails building when trying to
build libcsupport (I leave this problem for you :-).
Fixes/Changes:
* aclocal/canonicalize-target-name.m4: use RTEMS_CPU instead of
target_cpu, switch to a native compiler setup if target = no_cpu*rtems,
ie. implicitly use host=target (native) and RTEMS_CPU=no_cpu for
--target=no_cpu*rtems.
* add no_bsp/bsp_specs (Support -qrtems, -qrtems_debug; please check
before adding :-)
* Use RTEMS_CANONICALIZE_TARGET_CPU instead of AC_CANONICAL_SYSTEM in
toplevel/configure.in
* All references to $target_cpu in aclocal/*.m4, Makefile.ins and *.cfg
files changed to RTEMS_CPU
* bug fixes to exec/score/cpu/no_cpu/wrap (This part of the patch may
result into patch rejections, because your recently posted patch may
also have addressed this problem).
After applying this patch, please do:
cvs add c/src/lib/libbsp/no_cpu/no_bsp/bsp_specs
./autogen
described in the message following this paragraph. This patch also includes
a mcp750 BSP.
From valette@crf.canon.fr Mon Jun 14 10:03:08 1999
Date: Tue, 18 May 1999 01:30:14 +0200 (CEST)
From: VALETTE Eric <valette@crf.canon.fr>
To: joel@oarcorp.com
Cc: raguet@crf.canon.fr, rtems-snapshots@oarcorp.com, valette@crf.canon.fr
Subject: Questions/Suggestion regarding RTEMS PowerPC code (long)
Dear knowledgeable RTEMS powerpc users,
As some of you may know, I'm currently finalizing a port
of RTEMS on a MCP750 Motorola board. I have done most
of it but have some questions to ask before submitting
the port.
In order to understand some of the changes I have made
or would like to make, maybe it is worth describing the
MCP750 Motorola board.
the MCP750 is a COMPACT PCI powerpc board with :
1) a MPC750 233 MHz processor,
2) a raven bus bridge/PCI controller that
implement an OPENPIC compliant interrupt controller,
3) a VIA 82C586 PCI/ISA bridge that offers a PC
compliant IO for keyboard, serial line, IDE, and
the well known PC 8259 cascaded PIC interrupt
architecture model,
4) a DEC 21140 Ethernet controller,
5) the PPCBUG Motorola firmware in flash,
6) A DEC PCI bridge,
This architecture is common to most Motorola 60x/7xx
board except that :
1) on VME board, the DEC PCI bridge is replaced by
a VME chipset,
2) the VIA 82C586 PCI/ISA bridge is replaced by
another bridge that is almost fully compatible
with the via bridge...
So the port should be a rather close basis for many
60x/7xx motorola board...
On this board, I already have ported Linux 2.2.3 and
use it both as a development and target board.
Now the questions/suggestions I have :
1) EXCEPTION CODE
-------------------
As far as I know exceptions on PPC are handled like
interrupts. I dislike this very much as :
a) Except for the decrementer exception (and
maybe some other on mpc8xx), exceptions are
not recoverable and the handler just need to print
the full context and go to the firmware or debugger...
b) The interrupt switch is only necessary for the
decrementer and external interrupt (at least on
6xx,7xx).
c) The full context for exception is never saved and
thus cannot be used by debugger... I do understand
the most important for interrupts low level code
is to save the minimal context enabling to call C
code for performance reasons. On non recoverable
exception on the other hand, the most important is
to save the maximum information concerning proc status
in order to analyze the reason of the fault. At
least we will need this in order to implement the
port of RGDB on PPC
==> I wrote an API for connecting raw exceptions (and thus
raw interrupts) for mpc750. It should be valid for most
powerpc processors... I hope to find a way to make this coexist
with actual code layout. The code is actually located
in lib/libcpu/powerpc/mpc750 and is thus optional
(provided I write my own version of exec/score/cpu/powerpc/cpu.c ...)
See remark about files/directory layout organization in 4)
2) Current Implementation of ISR low level code
-----------------------------------------------
I do not understand why the MSR EE flags is cleared
again in exec/score/cpu/powerpc/irq_stubs.S
#if (PPC_USE_SPRG)
mfmsr r5
mfspr r6, sprg2
#else
lwz r6,msr_initial(r11)
lis r5,~PPC_MSR_DISABLE_MASK@ha
ori r5,r5,~PPC_MSR_DISABLE_MASK@l
and r6,r6,r5
mfmsr r5
#endif
Reading the doc, when a decrementer interrupt or an
external interrupt is active, the MSR EE flag is already
cleared. BTW if exception/interrupt could occur, it would
trash SRR0 and SRR1. In fact the code may be useful to set
MSR[RI] that re-enables exception processing. BTW I will need
to set other value in MSR to handle interrupts :
a) I want the MSR[IR] and MSR[DR] to be set for
performance reasons and also because I need DBAT
support to have access to PCI memory space as the
interrupt controller is in the PCI space.
Reading the code, I see others have the same kind of request :
/* SCE 980217
*
* We need address translation ON when we call our ISR routine
mtmsr r5
*/
This is just another prof that even the lowest level
IRQ code is fundamentally board dependent and
not simply processor dependent especially when
the processor use external interrupt controller
because it has a single interrupt request line...
Note that if you look at the PPC code high level interrupt
handling code, as the "set_vector" routine that really connects
the interrupt is in the BSP/startup/genpvec.c,
the fact that IRQ handling is BSP specific is DE-FACTO
acknowledged.
I know I have already expressed this and understand that this
would require some heavy change in the code but believe
me you will reach a point where you will not be able
to find a compatible while optimum implementation for low level
interrupt handling code...) In my case this is already true...
So please consider removing low level IRQ handling from
exec/score/cpu/* and only let there exception handling code...
Exceptions are usually only processor dependent and do
not depend on external hardware mechanism to be masked or
acknowledged or re-enabled (there are probably exception but ...)
I have already done this for pc386 bsp but need to make it again.
This time I will even propose an API.
3) R2/R13 manipulation for EABI implementation
----------------------------------------------
I do not understand the handling of r2 and r13 in the
EABI case. The specification for r2 says pointer to sdata2,
sbss2 section => constant. However I do not see -ffixed-r2
passed to any compilation system in make/custom/*
(for info linux does this on PPC).
So either this is a default compiler option when choosing
powerpc-rtems and thus we do not need to do anything with
this register as all the code is compiled with this compiler
and linked together OR this register may be used by rtems code
and then we do not need any special initialization or
handling.
The specification for r13 says pointer to the small data
area. r13 argumentation is the same except that as far
as I know the usage of the small data area requires
specific compiler support so that access to variables is
compiled via loading the LSB in a register and then
using r13 to get full address... It is like a small
memory model and it was present in IBM C compilers.
=> I propose to suppress any specific code for r2 and
r13 in the EABI case.
4) Code layout organization (yes again :-))
-------------------------------------------
I think there are a number of design flaws in the way
the code is for ppc organized and I will try to point them out.
I have been beaten by this again on this new port, and
was beaten last year while modifying code for pc386.
a) exec/score/cpu/* vs lib/libcpu/cpu/*.
I think that too many things are put in exec/score/cpu that
have nothing to do with RTEMS internals but are rather
related to CPU feature.
This include at least :
a) registers access routine (e.g GET_MSR_Value),
b) interrupt masking/unmasking routines,
c) cache_mngt_routine,
d) mmu_mngt_routine,
e) Routines to connect the raw_exception, raw_interrupt
handler,
b) lib/libcpu/cpu/powerpc/*
With a processor family as exuberant as the powerpc family,
and their well known subtle differences (604 vs 750) or
unfortunately majors (8xx vs 60x) the directory structure
is fine (except maybe the names that are not homogeneous)
powerpc
ppc421 mpc821 ...
I only needed to add mpc750. But the fact that libcpu.a was not
produced was a pain and the fact that this organization may
duplicates code is also problematic.
So, except if the support of automake provides a better solution
I would like to propose something like this :
powerpc
mpc421 mpc821 ... mpc750 shared wrapup
with the following rules :
a) "shared" would act as a source container for sources that may
be shared among processors. Needed files would be compiled inside
the processor specific directory using the vpath Makefile
mechanism. "shared" may also contain compilation code
for routine that are really shared and not worth to inline...
(did not found many things so far as registers access routine
ARE WORTH INLINING)... In the case something is compiled there,
it should create libcpushared.a
b) layout under processor specific directory is free provided
that
1)the result of the compilation process exports :
libcpu/powerpc/"PROC"/*.h in $(PROJECT_INCLUDE)/libcpu
2) each processor specific directory creates
a library called libcpuspecific.a
Note that this organization enables to have a file that
is nearly the same than in shared but that must differ
because of processor differences...
c) "wrapup" should create libcpu.a using libcpushared.a
libcpuspecific.a and export it $(PROJECT_INCLUDE)/libcpu
The only thing I have no ideal solution is the way to put shared
definitions in "shared" and only processor specific definition
in "proc". To give a concrete example, most MSR bit definition
are shared among PPC processors and only some differs. if we create
a single msr.h in shared it will have ifdef. If in msr.h we
include libcpu/msr_c.h we will need to have it in each prowerpc
specific directory (even empty). Opinions are welcomed ...
Note that a similar mechanism exist in libbsp/i386 that also
contains a shared directory that is used by several bsp
like pc386 and i386ex and a similar wrapup mechanism...
NB: I have done this for mpc750 and other processors could just use
similar Makefiles...
c) The exec/score/cpu/powerpc directory layout.
I think the directory layout should be the same than the
libcpu/powerpc. As it is not, there are a lot of ifdefs
inside the code... And of course low level interrupt handling
code should be removed...
Besides that I do not understand why
1) things are compiled in the wrap directory,
2) some includes are moved to rtems/score,
I think the "preinstall" mechanism enables to put
everything in the current directory (or better in a per processor
directory),
5) Interrupt handling API
-------------------------
Again :-). But I think that using all the features the PIC
offers is a MUST for RT system. I already explained in the
prologue of this (long and probably boring) mail that the MCP750
boards offers an OPENPIC compliant architecture and that
the VIA 82586 PCI/ISA bridge offers a PC compatible IO and
PIC mapping. Here is a logical view of the RAVEN/VIA 82586
interrupt mapping :
--------- 0 ------
| OPEN | <-----|8259|
| PIC | | | 2 ------
|(RAVEN)| | | <-----|8259|
| | | | | | 11
| | | | | | <----
| | | | | |
| | | | | |
--------- ------ | |
^ ------
| VIA PCI/ISA bridge
| x
-------- PCI interrupts
OPENPIC offers interrupt priorities among PCI interrupts
and interrupt selective masking. The 8259 offers the same kind
of feature. With actual powerpc interrupt code :
1) there is no way to specify priorities among
interrupts handler. This is REALLY a bad thing.
For me it is as importnat as having priorities
for threads...
2) for my implementation, each ISR should
contain the code that acknowledge the RAVEN
and 8259 cascade, modify interrupt mask on both
chips, and reenable interrupt at processor level,
..., restore then on interrupt return,.... This code
is actually similar to code located in some
genpvec.c powerpc files,
3) I must update _ISR_Nesting_level because
irq.inl use it...
4) the libchip code connects the ISR via set_vector
but the libchip handler code does not contain any code to
manipulate external interrupt controller hardware
in order to acknoledge the interrupt or re-enable
them (except for the target hardware of course)
So this code is broken unless set_vector adds an
additionnal prologue/epilogue before calling/returning
from in order to acknoledge/mask the raven and the
8259 PICS... => Anyway already EACH BSP MUST REWRITE
PART OF INTERRUPT HANDLING CODE TO CORRECTLY IMPLEMENT
SET_VECTOR.
I would rather offer an API similar to the one provided
in libbsp/i386/shared/irq/irq.h so that :
1) Once the driver supplied methods is called the
only things the ISR has to do is to worry about the
external hardware that triggered the interrupt.
Everything on openpic/VIA/processor would have been
done by the low levels (same things as set-vector)
2) The caller will need to supply the on/off/isOn
routine that are fundamental to correctly implements
debuggers/performance monitoring is a portable way
3) A globally configurable interrupt priorities
mechanism...
I have nothing against providing a compatible
set_vector just to make libchip happy but
as I have already explained in other
mails (months ago), I really think that the ISR
connection should be handled by the BSP and that no
code containing irq connection should exist the
rtems generic layers... Thus I really dislike
libchip on this aspect because in a long term
it will force to adopt the less reach API
for interrupt handling that exists (set_vector).
Additional note : I think the _ISR_Is_in_progress()
inline routine should be :
1) Put in a processor specific section,
2) Should not rely on a global variable,
As :
a) on symmetric MP, there is one interrupt level
per CPU,
b) On processor that have an ISP (e,g 68040),
this variable is useless (MSR bit testing could
be used)
c) On PPC, instead of using the address of the
variable via __CPU_IRQ_info.Nest_level a dedicated
SPR could be used.
NOTE: most of this is also true for _Thread_Dispatch_disable_level
END NOTE
--------
Please do not take what I said in the mail as a criticism for
anyone who submitted ppc code. Any code present helped me
a lot understanding PPC behavior. I just wanted by this
mail to :
1) try to better understand the actual code,
2) propose concrete ways of enhancing current code
by providing an alternative implementation for MCP750. I
will make my best effort to try to brake nothing but this
is actually hard due to the file layout organisation.
3) make understandable some changes I will probably make
if joel let me do them :-)
Any comments/objections are welcomed as usual.
--
__
/ ` Eric Valette
/-- __ o _. Canon CRF
(___, / (_(_(__ Rue de la touche lambert
35517 Cesson-Sevigne Cedex
FRANCE
Tel: +33 (0)2 99 87 68 91 Fax: +33 (0)2 99 84 11 30
E-mail: valette@crf.canon.fr
I have made test with the Dec21140 driver and it appears that all
works fine even if the cache is enabled for the memory space in
which the incoming and outcoming Ethernet frames are stored.
I have had #ifdef to "comment" the code. If you want to disable
cache, you only have to #define the name. It could be mandatory
for some BSPs.
University of British Columbia. The BSP is for:
Yes, this is the "entry model" of a series of boards from Technologic
Systems. Costs <$200 I believe. They have a WWW page at www.t-systems.com.
I am letting them know about the availability of this BSP too.
This one is an enhancement to acpolish.
It replaces some Makefile variables by others variable in Makefile.ins
(tries to use unique name for some variables). It therefore eases
parsing Makefile.ins for further automatic Makefile.in conversions in
future.
To apply:
cd <rtems-source-tree>
sh <path-to>/rtems-rc-19990407-8.sh
./autogen
2) ./c/src/lib/libbsp/i386/go32/startup
> all: ${ARCH} $(SRCS) $(PGM)
> $(INSTALL_CHANGE) ${PROJECT_RELEASE}/lib
>
>
This also is very questionable, because it means "install
$(PROJECT_RELEASE)/$/lib to the void". I think, removing the
INSTALL_CHANGE is the right way to fix it.
1) ./c/src/lib/libbsp/i386/i386ex/startup/Makefile.in
> preinstall:
> $(INSTALL_CHANGE) ${IMPORT_SRC} .
>
> # ${CP} ${IMPORT_SRC} .
>
>
>
This fragment is broken, because IMPORT_SRC is always empty.
IMO, the fix would be to remove this fragment or to replace it with
test -z "${IMPORT_SRC}" || cp ${IMPORT_SRC} .
if an external shell variable IMPORT_SRC shall be supported by this
Makefile, which IMO should not be done.
This first one below looked like it only belonged in a
virtual memory environment. The second one was causing
problems without the PROVIDE() - I don't know why.
Installing of bsp_specs for aliased bsps is broken. Instead of installing
RTEMS_BSP_FAMILY/bsp_specs, RTEMS_BSP/bsp_specs was tried to be installed.
The patch below should fix this problem (tested with mips64orion p4600 and
p4650).
This patch addresses a few minor issues and contains a few (minor)
preparations for automake.
* configure.in: Fix for handing c/src/tests subdirectory handling (FIX)
* aclocal/rtems-top.m4:
+ Add TARGET_SUBDIR and --with-target-subdir (preparation of future
enhancements for cross-compiling)
+ Activate RTEMS_ROOT handling (automake preparation)
* automake/*.am: replace comments "#" with "##" so that comments won't
get included into Makefile.in's anymore
* c/update-tools/* automake support (NEW)
* ./autogen update/enhancement (cf. ./autogen for details)
After applying this patch please run:
./autogen
cvs add c/update-tools/configure.in
cvs add c/update-tools/Makefile.am
cvs add c/update-tools/aclocal.m4
In your various bsp_specs files, even when ecrti.o is defined as a
startfile, ecrtn.o is not defined as an endfile. Instead it seems to
be in the library list - untidy.
I'd like to make the following change which adds the m360 structure
information to the debugging symbols in the final executable. This
makes it much easier to use the debugger to look at the elements of
the m360 structure.
Emmanuel Raguet <raguet@crf.canon.fr> to eliminate a problem
during the boot process on the pc386 BSP. On fast PC's the
calibration routine would hand.
