The LEON2 and ERC32 maps the new macros to CPU0 since they do not
support SMP. With the LEON3 a specific CPU's interrupt controller
registers can be modified using macros.
Call rtems_termios_dequeue_characters() only in case all characters of
the last write handler invocation have been transmitted. This avoids
problems with pppstart() since the start line discipline does not know
how many characters have been dequeued and assumes the maximum.
Add a simple Termios console driver using a table for statically
registered devices used in console_initialize() and dynamic installation
via console_device_install().
Move interrupt lock to device context and expose only this structure to
the read, write and set attributes device handler. This makes these
device handler independent of the general Termios infrastructure
suitable for direct use in printk() support.
By removing the bsp_reset() mechanism and instead relying on the
CPU_Fatal_halt() routine SMP and single-core can halt by updating
the _Internal_errors_What_happened structure and set the state to
SYSTEM_STATE_TERMINATED (the generic way). This will be better
for test scripts and debugger that can generically look into why
the OS stopped.
For SMP systems, only the fatal-reporting CPU waits until all other
CPUs are powered down (with a time out of one clock tick). The
reason why a fatal stop happend may be because CPU0 was soft-locked
up so we can never trust that CPU0 should do the halt for us.
The Fatal_halt handler now have two options, either halt
as before or enter system error state to return to
debugger or simulator. The exit-code is now also
propagated to the debugger which is very useful for
testing.
The CPU_Fatal_halt handler was split up into two, since
the only the LEON3 support the CPU power down.
The LEON3 halt now uses the power-down instruction to save
CPU power. This doesn't stop a potential watch-dog timer
from expiring.
Instead of calling the system call TA instruction directly it
is better paractise to isolate the trap implementation to the
system call functions.
BSP_fatal_exit() is added.
Added simple math to caclulate register values for the PLL
and for the prescalers. It will try to keep 48MHz for the USB OTG FS.
Also it will set latency on the Flash memory for the high speeds.
Limitations:
It is assumed that 1MHz resolution is enough.
Best fits for the clocks are achieved with multiplies of 42MHz.
Even though APB1, APB2 and AHB are calculated user is still required
to provide correct values for the bsp configuration for the:
STM32F4_PCLK1
STM32F4_PCLK2
STM32F4_HCLK (= system clock)
as those are used for the peripheral clocking calculations.
The LEON3_MP_IRQ define is used to pick the IRQ to be used by the
shared memory driver and for inter-processor interrupts. On some LEON3
systems, for example the GR712RC, the default value of 14 is not suitable.
To make this value configurable from the application, it is replaced with
a weakly linked variable that can be overridden from the application.
crt.h defines such lovely constants as "RED" and "GREEN" which
have a nasty habit of conflicting with non-BSP code. There is
no reason to include this private .h from bsp.h and pollute the
namespace for applications.
This change starts with removing the effectively empty file
timerdrv.h. The prototypes for benchmark_timer_XXX() were in
btimer.h which was not universally used. Thus every use of
timerdrv.h had to be changed to btimer.h. Then the prototypes
for benchmark_timer_read() had to be adjusted to return
benchmark_timer_t rather than int or uint32_t.
I took this opportunity to also correct the file headers to
separate the copyright from the file description comments which
is needed to ensure the copyright isn't propagated into Doxygen
output.
Implement new cache functions for or1k and create new bspstart function
for or1ksim to initialize instruction and data caches. Also, sim.cfg
is modified to enable/confiure cache units.
Modify README to provide instruction on how to run or1ksim BSP on
latest or1ksim emulator built from github repo and add commands
to run or1ksim BSP on QEMU.
This patch avoids unexpected behavior when initializing tick timer registers.
Initializing these registers fires unexpected exceptions and interrupts even
though RTEMS has not enabled interrupts yet. So, a little long interval added
to allow RTEMS to finish the remaining initialization work before running the
application. The tick timer interval is adjusted to reflect an accurate
timing for RTEMS applications.
This patch allocate a space in the stack to account for red-zone
that gcc may utilize for the use of leaf functions. Care must be
taken to handle this red-zone from many places:
1- Upon creation of a new thread stack.
2- Once an interrupt entred.
Also moving the enable-thread-dispach() and increment ISR level before
checking if dispatch needed was required.
The previous modifications solved the printf bug which disabled ticker
to output strings after context switches that arise from Thread_Delay_ended.
Do not invalidate the entire L2 cache since it is a uniform cache in
_CPU_cache_invalidate_entire_instruction(). For consitency do not touch
the L2 cache even for the range function
_CPU_cache_invalidate_instruction_range().
